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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 942
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T763 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3934216263 Mar 14 01:11:26 PM PDT 24 Mar 14 01:11:27 PM PDT 24 101374892 ps
T764 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.887150026 Mar 14 01:11:32 PM PDT 24 Mar 14 01:11:35 PM PDT 24 347612553 ps
T765 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2431639477 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:33 PM PDT 24 13253692 ps
T766 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2790808442 Mar 14 01:11:32 PM PDT 24 Mar 14 01:11:33 PM PDT 24 19844204 ps
T96 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2845836529 Mar 14 01:11:45 PM PDT 24 Mar 14 01:11:46 PM PDT 24 14229895 ps
T767 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.68001018 Mar 14 01:11:41 PM PDT 24 Mar 14 01:11:42 PM PDT 24 42138414 ps
T768 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1291824176 Mar 14 01:11:49 PM PDT 24 Mar 14 01:11:50 PM PDT 24 35436120 ps
T769 /workspace/coverage/cover_reg_top/27.gpio_intr_test.59795052 Mar 14 01:11:39 PM PDT 24 Mar 14 01:11:40 PM PDT 24 15714720 ps
T770 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2775056685 Mar 14 01:11:40 PM PDT 24 Mar 14 01:11:41 PM PDT 24 21944050 ps
T107 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3465938008 Mar 14 01:11:32 PM PDT 24 Mar 14 01:11:33 PM PDT 24 488245850 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2250740590 Mar 14 01:11:29 PM PDT 24 Mar 14 01:11:30 PM PDT 24 265848299 ps
T772 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3337419904 Mar 14 01:11:54 PM PDT 24 Mar 14 01:11:55 PM PDT 24 47542100 ps
T773 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2711698682 Mar 14 01:11:23 PM PDT 24 Mar 14 01:11:26 PM PDT 24 357174207 ps
T108 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2932612761 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:30 PM PDT 24 27490867 ps
T774 /workspace/coverage/cover_reg_top/17.gpio_intr_test.642781447 Mar 14 01:11:40 PM PDT 24 Mar 14 01:11:41 PM PDT 24 14923271 ps
T47 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3378906548 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:33 PM PDT 24 189939203 ps
T775 /workspace/coverage/cover_reg_top/39.gpio_intr_test.4252684880 Mar 14 01:11:41 PM PDT 24 Mar 14 01:11:42 PM PDT 24 36086365 ps
T776 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1482490749 Mar 14 01:11:45 PM PDT 24 Mar 14 01:11:47 PM PDT 24 27382341 ps
T777 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3437294235 Mar 14 01:11:47 PM PDT 24 Mar 14 01:11:48 PM PDT 24 30877361 ps
T778 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.59225900 Mar 14 01:11:26 PM PDT 24 Mar 14 01:11:28 PM PDT 24 349974321 ps
T779 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2616074547 Mar 14 01:11:26 PM PDT 24 Mar 14 01:11:28 PM PDT 24 167754909 ps
T780 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3945227425 Mar 14 01:11:27 PM PDT 24 Mar 14 01:11:28 PM PDT 24 37352382 ps
T781 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1187132827 Mar 14 01:11:33 PM PDT 24 Mar 14 01:11:33 PM PDT 24 22765905 ps
T782 /workspace/coverage/cover_reg_top/13.gpio_intr_test.328648826 Mar 14 01:11:32 PM PDT 24 Mar 14 01:11:33 PM PDT 24 14792657 ps
T783 /workspace/coverage/cover_reg_top/35.gpio_intr_test.872601070 Mar 14 01:11:38 PM PDT 24 Mar 14 01:11:39 PM PDT 24 42570389 ps
T784 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1314473889 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:30 PM PDT 24 23663754 ps
T785 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3601098581 Mar 14 01:11:43 PM PDT 24 Mar 14 01:11:43 PM PDT 24 56287811 ps
T51 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2178648840 Mar 14 01:11:43 PM PDT 24 Mar 14 01:11:45 PM PDT 24 120414967 ps
T786 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2423322583 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:33 PM PDT 24 49142578 ps
T97 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2346256042 Mar 14 01:11:24 PM PDT 24 Mar 14 01:11:25 PM PDT 24 28115073 ps
T787 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3250066590 Mar 14 01:11:49 PM PDT 24 Mar 14 01:11:49 PM PDT 24 13461932 ps
T788 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.822734382 Mar 14 01:11:27 PM PDT 24 Mar 14 01:11:29 PM PDT 24 27734925 ps
T789 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2205492085 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:33 PM PDT 24 234075134 ps
T790 /workspace/coverage/cover_reg_top/18.gpio_intr_test.869524718 Mar 14 01:11:41 PM PDT 24 Mar 14 01:11:42 PM PDT 24 44800196 ps
T791 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1417870911 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:30 PM PDT 24 78216027 ps
T792 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3290686810 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:30 PM PDT 24 34740048 ps
T793 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2342239768 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:33 PM PDT 24 58082523 ps
T794 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.932366719 Mar 14 01:11:25 PM PDT 24 Mar 14 01:11:29 PM PDT 24 174079932 ps
T795 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1917377889 Mar 14 01:11:29 PM PDT 24 Mar 14 01:11:31 PM PDT 24 39718324 ps
T796 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2202136547 Mar 14 01:11:30 PM PDT 24 Mar 14 01:11:31 PM PDT 24 16305248 ps
T797 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2069402252 Mar 14 01:11:45 PM PDT 24 Mar 14 01:11:47 PM PDT 24 258761987 ps
T798 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4120295809 Mar 14 01:11:46 PM PDT 24 Mar 14 01:11:48 PM PDT 24 74256641 ps
T799 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3888947874 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:29 PM PDT 24 53787648 ps
T800 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2994271224 Mar 14 01:11:55 PM PDT 24 Mar 14 01:11:56 PM PDT 24 35455856 ps
T801 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.990202968 Mar 14 01:11:26 PM PDT 24 Mar 14 01:11:27 PM PDT 24 618476414 ps
T802 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3744310472 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:30 PM PDT 24 71661106 ps
T803 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2065563217 Mar 14 01:11:30 PM PDT 24 Mar 14 01:11:31 PM PDT 24 12846983 ps
T804 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2486010545 Mar 14 01:11:26 PM PDT 24 Mar 14 01:11:27 PM PDT 24 24773357 ps
T805 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.172350030 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:30 PM PDT 24 318369549 ps
T98 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2098135976 Mar 14 01:11:25 PM PDT 24 Mar 14 01:11:26 PM PDT 24 50904819 ps
T806 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3452523903 Mar 14 01:11:26 PM PDT 24 Mar 14 01:11:28 PM PDT 24 22289520 ps
T807 /workspace/coverage/cover_reg_top/6.gpio_intr_test.54220348 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:29 PM PDT 24 13338719 ps
T808 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3349637747 Mar 14 01:11:55 PM PDT 24 Mar 14 01:11:55 PM PDT 24 15554741 ps
T99 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.830771626 Mar 14 01:11:25 PM PDT 24 Mar 14 01:11:27 PM PDT 24 139027167 ps
T809 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2393455352 Mar 14 01:11:24 PM PDT 24 Mar 14 01:11:25 PM PDT 24 129424935 ps
T810 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3583957479 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:35 PM PDT 24 58622867 ps
T52 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.544572559 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:30 PM PDT 24 396063093 ps
T811 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2554212466 Mar 14 01:11:40 PM PDT 24 Mar 14 01:11:40 PM PDT 24 13597031 ps
T812 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3414385721 Mar 14 01:11:30 PM PDT 24 Mar 14 01:11:31 PM PDT 24 33977460 ps
T813 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3100639287 Mar 14 01:11:43 PM PDT 24 Mar 14 01:11:44 PM PDT 24 13577439 ps
T101 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2131932394 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:31 PM PDT 24 11376138 ps
T814 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.321435112 Mar 14 01:11:47 PM PDT 24 Mar 14 01:11:50 PM PDT 24 41554072 ps
T815 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1881410862 Mar 14 01:11:29 PM PDT 24 Mar 14 01:11:31 PM PDT 24 58285988 ps
T816 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.260875812 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:34 PM PDT 24 25599905 ps
T817 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1441951214 Mar 14 01:11:40 PM PDT 24 Mar 14 01:11:41 PM PDT 24 66401443 ps
T818 /workspace/coverage/cover_reg_top/25.gpio_intr_test.819929103 Mar 14 01:11:51 PM PDT 24 Mar 14 01:11:51 PM PDT 24 48499124 ps
T819 /workspace/coverage/cover_reg_top/29.gpio_intr_test.484065812 Mar 14 01:11:47 PM PDT 24 Mar 14 01:11:48 PM PDT 24 54870730 ps
T820 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3936683741 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:30 PM PDT 24 36663496 ps
T821 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3058046502 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:29 PM PDT 24 95785263 ps
T822 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1882759052 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:33 PM PDT 24 93777246 ps
T823 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1235818213 Mar 14 01:11:50 PM PDT 24 Mar 14 01:11:51 PM PDT 24 20294344 ps
T824 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1434407152 Mar 14 01:11:49 PM PDT 24 Mar 14 01:11:50 PM PDT 24 18898076 ps
T825 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.4139895523 Mar 14 01:11:51 PM PDT 24 Mar 14 01:11:53 PM PDT 24 181360566 ps
T826 /workspace/coverage/cover_reg_top/22.gpio_intr_test.256222561 Mar 14 01:11:50 PM PDT 24 Mar 14 01:11:51 PM PDT 24 96605299 ps
T827 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.507480522 Mar 14 01:11:43 PM PDT 24 Mar 14 01:11:44 PM PDT 24 24076175 ps
T828 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2947426702 Mar 14 01:11:52 PM PDT 24 Mar 14 01:11:54 PM PDT 24 44732086 ps
T53 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3446475594 Mar 14 01:11:27 PM PDT 24 Mar 14 01:11:29 PM PDT 24 183472704 ps
T829 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3008188226 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:32 PM PDT 24 62625763 ps
T830 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3151839780 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:29 PM PDT 24 56667816 ps
T831 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2308417157 Mar 14 01:11:47 PM PDT 24 Mar 14 01:11:48 PM PDT 24 33129071 ps
T832 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1002663 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:29 PM PDT 24 41345398 ps
T833 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4136831631 Mar 14 01:11:27 PM PDT 24 Mar 14 01:11:28 PM PDT 24 65606354 ps
T834 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2778537203 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:29 PM PDT 24 31380778 ps
T835 /workspace/coverage/cover_reg_top/10.gpio_intr_test.27253886 Mar 14 01:11:31 PM PDT 24 Mar 14 01:11:33 PM PDT 24 32200686 ps
T836 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3008872059 Mar 14 01:11:33 PM PDT 24 Mar 14 01:11:34 PM PDT 24 17893299 ps
T837 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.453084683 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:30 PM PDT 24 68169868 ps
T838 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1709170587 Mar 14 01:11:30 PM PDT 24 Mar 14 01:11:31 PM PDT 24 29975174 ps
T54 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.193404212 Mar 14 01:11:48 PM PDT 24 Mar 14 01:11:49 PM PDT 24 158041207 ps
T839 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.934325661 Mar 14 01:11:30 PM PDT 24 Mar 14 01:11:31 PM PDT 24 13444757 ps
T840 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1109759381 Mar 14 01:11:33 PM PDT 24 Mar 14 01:11:34 PM PDT 24 85095299 ps
T841 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4271391816 Mar 14 01:11:27 PM PDT 24 Mar 14 01:11:28 PM PDT 24 300877791 ps
T842 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1851769509 Mar 14 01:11:28 PM PDT 24 Mar 14 01:11:31 PM PDT 24 39303960 ps
T843 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3015417363 Mar 14 01:08:53 PM PDT 24 Mar 14 01:08:54 PM PDT 24 98364013 ps
T844 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3557073288 Mar 14 01:08:26 PM PDT 24 Mar 14 01:08:28 PM PDT 24 41507433 ps
T845 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2680914752 Mar 14 01:08:11 PM PDT 24 Mar 14 01:08:12 PM PDT 24 355488877 ps
T846 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.475507016 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:43 PM PDT 24 131179167 ps
T847 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3645135891 Mar 14 01:08:39 PM PDT 24 Mar 14 01:08:40 PM PDT 24 301318127 ps
T848 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3059440633 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:29 PM PDT 24 34361244 ps
T849 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2238877671 Mar 14 01:08:31 PM PDT 24 Mar 14 01:08:33 PM PDT 24 54460355 ps
T850 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3980305672 Mar 14 01:08:28 PM PDT 24 Mar 14 01:08:30 PM PDT 24 365271369 ps
T851 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2590807639 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:28 PM PDT 24 203371343 ps
T852 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3365202880 Mar 14 01:08:39 PM PDT 24 Mar 14 01:08:40 PM PDT 24 58717607 ps
T853 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999302429 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:28 PM PDT 24 204912487 ps
T854 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1321703027 Mar 14 01:08:26 PM PDT 24 Mar 14 01:08:27 PM PDT 24 57325472 ps
T855 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1886211537 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:42 PM PDT 24 102044210 ps
T856 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2546927538 Mar 14 01:08:40 PM PDT 24 Mar 14 01:08:41 PM PDT 24 75313263 ps
T857 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3130765244 Mar 14 01:08:29 PM PDT 24 Mar 14 01:08:31 PM PDT 24 29111439 ps
T858 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3869419654 Mar 14 01:08:53 PM PDT 24 Mar 14 01:08:54 PM PDT 24 137399851 ps
T859 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.188766547 Mar 14 01:08:39 PM PDT 24 Mar 14 01:08:40 PM PDT 24 151905330 ps
T860 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1103304186 Mar 14 01:08:10 PM PDT 24 Mar 14 01:08:11 PM PDT 24 70024112 ps
T861 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1425657279 Mar 14 01:08:51 PM PDT 24 Mar 14 01:08:52 PM PDT 24 19663062 ps
T862 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3696113412 Mar 14 01:08:51 PM PDT 24 Mar 14 01:08:52 PM PDT 24 48765565 ps
T863 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3187661706 Mar 14 01:08:40 PM PDT 24 Mar 14 01:08:41 PM PDT 24 257797743 ps
T864 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2186286725 Mar 14 01:08:28 PM PDT 24 Mar 14 01:08:29 PM PDT 24 173479978 ps
T865 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3349565741 Mar 14 01:08:26 PM PDT 24 Mar 14 01:08:27 PM PDT 24 82272527 ps
T866 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3884167497 Mar 14 01:08:51 PM PDT 24 Mar 14 01:08:52 PM PDT 24 21685921 ps
T867 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2813088187 Mar 14 01:08:52 PM PDT 24 Mar 14 01:08:53 PM PDT 24 333748084 ps
T868 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.852859745 Mar 14 01:08:06 PM PDT 24 Mar 14 01:08:07 PM PDT 24 34456902 ps
T869 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3728556209 Mar 14 01:08:50 PM PDT 24 Mar 14 01:08:52 PM PDT 24 481500937 ps
T870 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.841898490 Mar 14 01:08:10 PM PDT 24 Mar 14 01:08:11 PM PDT 24 283391297 ps
T871 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.950854614 Mar 14 01:08:12 PM PDT 24 Mar 14 01:08:14 PM PDT 24 320837205 ps
T872 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2228519267 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:28 PM PDT 24 132332584 ps
T873 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2813673492 Mar 14 01:08:51 PM PDT 24 Mar 14 01:08:53 PM PDT 24 51346846 ps
T874 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3126554873 Mar 14 01:08:26 PM PDT 24 Mar 14 01:08:27 PM PDT 24 37376877 ps
T875 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.354323901 Mar 14 01:08:50 PM PDT 24 Mar 14 01:08:52 PM PDT 24 169673852 ps
T876 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2001137670 Mar 14 01:08:51 PM PDT 24 Mar 14 01:08:52 PM PDT 24 307897200 ps
T877 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3913044763 Mar 14 01:08:11 PM PDT 24 Mar 14 01:08:12 PM PDT 24 362816467 ps
T878 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3215318802 Mar 14 01:08:29 PM PDT 24 Mar 14 01:08:30 PM PDT 24 99499503 ps
T879 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2268723328 Mar 14 01:08:26 PM PDT 24 Mar 14 01:08:27 PM PDT 24 111456798 ps
T880 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1265053339 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:42 PM PDT 24 86440743 ps
T881 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4090382281 Mar 14 01:08:26 PM PDT 24 Mar 14 01:08:28 PM PDT 24 165986650 ps
T882 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2771084403 Mar 14 01:08:17 PM PDT 24 Mar 14 01:08:18 PM PDT 24 234599951 ps
T883 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3615890015 Mar 14 01:08:39 PM PDT 24 Mar 14 01:08:40 PM PDT 24 188095998 ps
T884 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1561854246 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:28 PM PDT 24 146129070 ps
T885 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3953805480 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:29 PM PDT 24 124116102 ps
T886 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3717267998 Mar 14 01:08:40 PM PDT 24 Mar 14 01:08:41 PM PDT 24 71009564 ps
T887 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3475523649 Mar 14 01:08:53 PM PDT 24 Mar 14 01:08:55 PM PDT 24 36081521 ps
T888 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3088070978 Mar 14 01:08:43 PM PDT 24 Mar 14 01:08:44 PM PDT 24 171040721 ps
T889 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3417388267 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:42 PM PDT 24 110603275 ps
T890 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1235829208 Mar 14 01:08:29 PM PDT 24 Mar 14 01:08:30 PM PDT 24 124517435 ps
T891 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3897057732 Mar 14 01:08:28 PM PDT 24 Mar 14 01:08:30 PM PDT 24 50521490 ps
T892 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.4093206735 Mar 14 01:08:16 PM PDT 24 Mar 14 01:08:18 PM PDT 24 34658556 ps
T893 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.754691180 Mar 14 01:08:40 PM PDT 24 Mar 14 01:08:42 PM PDT 24 59526924 ps
T894 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2412004189 Mar 14 01:08:28 PM PDT 24 Mar 14 01:08:29 PM PDT 24 52856694 ps
T895 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894856560 Mar 14 01:08:39 PM PDT 24 Mar 14 01:08:41 PM PDT 24 77453945 ps
T896 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1275913112 Mar 14 01:08:29 PM PDT 24 Mar 14 01:08:31 PM PDT 24 36468484 ps
T897 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2759851990 Mar 14 01:08:39 PM PDT 24 Mar 14 01:08:41 PM PDT 24 135392065 ps
T898 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1463369825 Mar 14 01:08:51 PM PDT 24 Mar 14 01:08:52 PM PDT 24 247354804 ps
T899 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3228452916 Mar 14 01:08:51 PM PDT 24 Mar 14 01:08:52 PM PDT 24 495575765 ps
T900 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1270616838 Mar 14 01:08:42 PM PDT 24 Mar 14 01:08:43 PM PDT 24 57844507 ps
T901 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.634149408 Mar 14 01:08:26 PM PDT 24 Mar 14 01:08:27 PM PDT 24 609102330 ps
T902 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.452976667 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:43 PM PDT 24 75715746 ps
T903 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.672258769 Mar 14 01:08:13 PM PDT 24 Mar 14 01:08:15 PM PDT 24 107417600 ps
T904 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3946149731 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:42 PM PDT 24 1233618202 ps
T905 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1610109 Mar 14 01:08:42 PM PDT 24 Mar 14 01:08:43 PM PDT 24 545700849 ps
T906 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1615250690 Mar 14 01:08:52 PM PDT 24 Mar 14 01:08:54 PM PDT 24 89526038 ps
T907 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1266647937 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:42 PM PDT 24 42059888 ps
T908 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3961374023 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:28 PM PDT 24 174397035 ps
T909 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.967339797 Mar 14 01:08:51 PM PDT 24 Mar 14 01:08:52 PM PDT 24 54950978 ps
T910 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.767729624 Mar 14 01:08:50 PM PDT 24 Mar 14 01:08:52 PM PDT 24 358999905 ps
T911 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3326189968 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:43 PM PDT 24 67451708 ps
T912 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2158993706 Mar 14 01:08:17 PM PDT 24 Mar 14 01:08:19 PM PDT 24 81487431 ps
T913 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3931545795 Mar 14 01:08:39 PM PDT 24 Mar 14 01:08:41 PM PDT 24 149208780 ps
T914 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3857708447 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:42 PM PDT 24 699141624 ps
T915 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.40143820 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:43 PM PDT 24 70216223 ps
T916 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3116956917 Mar 14 01:08:28 PM PDT 24 Mar 14 01:08:29 PM PDT 24 32846408 ps
T917 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.209659680 Mar 14 01:08:40 PM PDT 24 Mar 14 01:08:41 PM PDT 24 202695738 ps
T918 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3316387915 Mar 14 01:08:38 PM PDT 24 Mar 14 01:08:39 PM PDT 24 46696456 ps
T919 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2457101296 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:28 PM PDT 24 81694613 ps
T920 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.825154686 Mar 14 01:08:40 PM PDT 24 Mar 14 01:08:41 PM PDT 24 284939993 ps
T921 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1335334614 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:43 PM PDT 24 77449468 ps
T922 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2649322214 Mar 14 01:08:16 PM PDT 24 Mar 14 01:08:18 PM PDT 24 100847520 ps
T923 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1985442676 Mar 14 01:08:51 PM PDT 24 Mar 14 01:08:52 PM PDT 24 41898618 ps
T924 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.971487909 Mar 14 01:08:55 PM PDT 24 Mar 14 01:08:57 PM PDT 24 87729707 ps
T925 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.214365 Mar 14 01:08:49 PM PDT 24 Mar 14 01:08:51 PM PDT 24 50396712 ps
T926 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.78852570 Mar 14 01:08:28 PM PDT 24 Mar 14 01:08:30 PM PDT 24 92250127 ps
T927 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1322101265 Mar 14 01:08:29 PM PDT 24 Mar 14 01:08:30 PM PDT 24 29981844 ps
T928 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4084390568 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:42 PM PDT 24 107968175 ps
T929 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4273364421 Mar 14 01:08:15 PM PDT 24 Mar 14 01:08:16 PM PDT 24 36971437 ps
T930 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2665189948 Mar 14 01:08:49 PM PDT 24 Mar 14 01:08:51 PM PDT 24 321748021 ps
T931 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1416571492 Mar 14 01:08:40 PM PDT 24 Mar 14 01:08:41 PM PDT 24 59932108 ps
T932 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2819265315 Mar 14 01:08:29 PM PDT 24 Mar 14 01:08:31 PM PDT 24 277013391 ps
T933 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.462187342 Mar 14 01:08:41 PM PDT 24 Mar 14 01:08:43 PM PDT 24 192917174 ps
T934 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.828473583 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:28 PM PDT 24 105794697 ps
T935 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2474880150 Mar 14 01:08:27 PM PDT 24 Mar 14 01:08:28 PM PDT 24 123038477 ps
T936 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3462272807 Mar 14 01:08:53 PM PDT 24 Mar 14 01:08:54 PM PDT 24 48402696 ps
T937 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2488340311 Mar 14 01:08:19 PM PDT 24 Mar 14 01:08:20 PM PDT 24 33951492 ps
T938 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.297032555 Mar 14 01:08:28 PM PDT 24 Mar 14 01:08:29 PM PDT 24 33767810 ps
T939 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3219285352 Mar 14 01:08:39 PM PDT 24 Mar 14 01:08:40 PM PDT 24 73267438 ps
T940 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2761771789 Mar 14 01:08:52 PM PDT 24 Mar 14 01:08:53 PM PDT 24 94072026 ps
T941 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3589289775 Mar 14 01:08:11 PM PDT 24 Mar 14 01:08:12 PM PDT 24 79788770 ps
T942 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1213116137 Mar 14 01:08:16 PM PDT 24 Mar 14 01:08:17 PM PDT 24 303002636 ps

Test location /workspace/coverage/default/36.gpio_full_random.3935945907
Short name T14
Test name
Test status
Simulation time 110511225 ps
CPU time 0.85 seconds
Started Mar 14 01:24:15 PM PDT 24
Finished Mar 14 01:24:17 PM PDT 24
Peak memory 196256 kb
Host smart-028f70a3-072b-4d95-922b-4a9f551fa5c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935945907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3935945907
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.806017406
Short name T76
Test name
Test status
Simulation time 119553231 ps
CPU time 2.52 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:35 PM PDT 24
Peak memory 198488 kb
Host smart-32766721-86c4-4681-8e40-4e5739aac364
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806017406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.806017406
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1079508873
Short name T22
Test name
Test status
Simulation time 120162233 ps
CPU time 3.64 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 198336 kb
Host smart-c321d520-05c5-4b36-96f6-4126a4dc20cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079508873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1079508873
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.4171357711
Short name T34
Test name
Test status
Simulation time 101596041789 ps
CPU time 1396.94 seconds
Started Mar 14 01:24:33 PM PDT 24
Finished Mar 14 01:47:51 PM PDT 24
Peak memory 198528 kb
Host smart-ae6de81b-27d3-4c1a-8c05-a82beff924a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4171357711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.4171357711
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2646511495
Short name T2
Test name
Test status
Simulation time 193363585 ps
CPU time 2.45 seconds
Started Mar 14 01:23:28 PM PDT 24
Finished Mar 14 01:23:30 PM PDT 24
Peak memory 198332 kb
Host smart-9a251647-a0f4-4800-ba42-75d2594de31d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646511495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2646511495
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3934667185
Short name T37
Test name
Test status
Simulation time 575073642 ps
CPU time 1.2 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 198188 kb
Host smart-807a83c5-f618-4292-a8fa-6f749120ca89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934667185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3934667185
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.888415117
Short name T86
Test name
Test status
Simulation time 38567409 ps
CPU time 0.88 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 196760 kb
Host smart-0320ec1c-30a2-4aad-b2a1-bbc474d12f40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888415117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.888415117
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2565172520
Short name T45
Test name
Test status
Simulation time 13715170 ps
CPU time 0.61 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:30 PM PDT 24
Peak memory 194792 kb
Host smart-28e5b1b9-bd25-4b18-81f7-f51f0003a361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565172520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2565172520
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1860584192
Short name T12
Test name
Test status
Simulation time 197801669 ps
CPU time 1.44 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 197020 kb
Host smart-78bb8308-c8f8-4d70-8130-2921f2265a49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860584192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1860584192
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3693755928
Short name T41
Test name
Test status
Simulation time 256905912 ps
CPU time 0.85 seconds
Started Mar 14 01:22:38 PM PDT 24
Finished Mar 14 01:22:40 PM PDT 24
Peak memory 213716 kb
Host smart-73b1d98e-a54e-4309-b3b2-e2615a37ea38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693755928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3693755928
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.830771626
Short name T99
Test name
Test status
Simulation time 139027167 ps
CPU time 0.91 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:27 PM PDT 24
Peak memory 196244 kb
Host smart-badff453-1f76-4c27-8747-a460ba023ba7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830771626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.830771626
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2762628069
Short name T106
Test name
Test status
Simulation time 51032504 ps
CPU time 0.65 seconds
Started Mar 14 01:11:12 PM PDT 24
Finished Mar 14 01:11:13 PM PDT 24
Peak memory 195500 kb
Host smart-5a6965e7-75cf-412d-8a95-f57a46ce150a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762628069 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2762628069
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3446475594
Short name T53
Test name
Test status
Simulation time 183472704 ps
CPU time 1.39 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 198120 kb
Host smart-961fc8da-e6f9-484d-8f88-356f0e9eee47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446475594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3446475594
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2273671994
Short name T111
Test name
Test status
Simulation time 120663965 ps
CPU time 1.46 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 198232 kb
Host smart-86041574-3f42-4d8c-bd92-773f7b6a63e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273671994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2273671994
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1881410862
Short name T815
Test name
Test status
Simulation time 58285988 ps
CPU time 2.13 seconds
Started Mar 14 01:11:29 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 197216 kb
Host smart-aab92923-a72f-4f20-809d-9d189de03e17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881410862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1881410862
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2393455352
Short name T809
Test name
Test status
Simulation time 129424935 ps
CPU time 0.68 seconds
Started Mar 14 01:11:24 PM PDT 24
Finished Mar 14 01:11:25 PM PDT 24
Peak memory 194844 kb
Host smart-8aa7a88e-8be4-49ff-b502-d432ebf91acc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393455352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2393455352
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3452523903
Short name T806
Test name
Test status
Simulation time 22289520 ps
CPU time 0.97 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 197920 kb
Host smart-44269daa-83d0-42f0-8964-f9d3ca54b022
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452523903 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3452523903
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2266639524
Short name T754
Test name
Test status
Simulation time 42962829 ps
CPU time 0.63 seconds
Started Mar 14 01:11:13 PM PDT 24
Finished Mar 14 01:11:14 PM PDT 24
Peak memory 195592 kb
Host smart-3cf09975-c009-482e-a62d-4b51266c742a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266639524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2266639524
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3934216263
Short name T763
Test name
Test status
Simulation time 101374892 ps
CPU time 0.57 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:27 PM PDT 24
Peak memory 193696 kb
Host smart-75657e38-cc97-4745-8f44-518ccdc7beae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934216263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3934216263
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.385189440
Short name T760
Test name
Test status
Simulation time 224441529 ps
CPU time 1.4 seconds
Started Mar 14 01:11:23 PM PDT 24
Finished Mar 14 01:11:24 PM PDT 24
Peak memory 198116 kb
Host smart-a75e3501-194f-4766-9567-b9546ad6d84d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385189440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.385189440
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4017582228
Short name T49
Test name
Test status
Simulation time 67479945 ps
CPU time 1.16 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198200 kb
Host smart-7d762907-5ca3-4675-b1a9-74a81ff6d337
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017582228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.4017582228
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2342239768
Short name T793
Test name
Test status
Simulation time 58082523 ps
CPU time 0.77 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 196096 kb
Host smart-4e392074-94f5-4529-a9f3-65a18fa6b118
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342239768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2342239768
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.772311722
Short name T100
Test name
Test status
Simulation time 221653590 ps
CPU time 2.19 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 198120 kb
Host smart-2191e44c-bfc1-4682-b7cc-4ced4ff71d15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772311722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.772311722
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3776479730
Short name T87
Test name
Test status
Simulation time 19288190 ps
CPU time 0.64 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:26 PM PDT 24
Peak memory 194912 kb
Host smart-d9fb1202-52e0-4ee0-9a30-600661525885
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776479730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3776479730
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2125573164
Short name T746
Test name
Test status
Simulation time 138795473 ps
CPU time 1.02 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198068 kb
Host smart-bdfe1200-42b9-4d81-be1d-830310fdbd5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125573164 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2125573164
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2486010545
Short name T804
Test name
Test status
Simulation time 24773357 ps
CPU time 0.61 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:27 PM PDT 24
Peak memory 194456 kb
Host smart-c7969cde-ebb1-4c1b-9984-d5831500ee11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486010545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2486010545
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2613226463
Short name T753
Test name
Test status
Simulation time 39455535 ps
CPU time 0.6 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:26 PM PDT 24
Peak memory 193840 kb
Host smart-4c902ed7-e740-430c-8be2-fcf75118321b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613226463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2613226463
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.990202968
Short name T801
Test name
Test status
Simulation time 618476414 ps
CPU time 0.85 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:27 PM PDT 24
Peak memory 196596 kb
Host smart-8cfbcc7e-e81c-4f3f-8be1-08fa9cd17a37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990202968 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.990202968
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.260875812
Short name T816
Test name
Test status
Simulation time 25599905 ps
CPU time 1.4 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:34 PM PDT 24
Peak memory 198212 kb
Host smart-b37a6cb1-7fc3-41ab-9022-e35b50d68e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260875812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.260875812
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3822472114
Short name T39
Test name
Test status
Simulation time 292185276 ps
CPU time 1.18 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 197840 kb
Host smart-9995bdee-5752-4b36-9298-673c23c9759a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822472114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3822472114
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.591682459
Short name T741
Test name
Test status
Simulation time 218523201 ps
CPU time 1.66 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 198288 kb
Host smart-758675d2-981c-4b56-bb18-f30f496ca020
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591682459 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.591682459
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3058046502
Short name T821
Test name
Test status
Simulation time 95785263 ps
CPU time 0.63 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 194724 kb
Host smart-baf31b9f-63b5-4853-8a23-739ed9879787
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058046502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3058046502
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.27253886
Short name T835
Test name
Test status
Simulation time 32200686 ps
CPU time 0.6 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 193784 kb
Host smart-5903362a-f22e-48a2-a7d9-4385b397d605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27253886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.27253886
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3008188226
Short name T829
Test name
Test status
Simulation time 62625763 ps
CPU time 0.79 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:32 PM PDT 24
Peak memory 196348 kb
Host smart-e294ba23-95eb-4d99-b436-7342d25627f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008188226 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3008188226
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1851769509
Short name T842
Test name
Test status
Simulation time 39303960 ps
CPU time 1.96 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 198200 kb
Host smart-99c215c2-f1c0-443a-b6da-b13301a18827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851769509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1851769509
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3290686810
Short name T792
Test name
Test status
Simulation time 34740048 ps
CPU time 1.3 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198312 kb
Host smart-bf6d0393-79f6-4e14-ade4-0d6ff0bd4de7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290686810 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3290686810
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2131932394
Short name T101
Test name
Test status
Simulation time 11376138 ps
CPU time 0.61 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 193700 kb
Host smart-0c25f04b-8cc7-4d17-8df5-409af82abb2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131932394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2131932394
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.471527127
Short name T732
Test name
Test status
Simulation time 32555008 ps
CPU time 0.62 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 193928 kb
Host smart-636c51d4-b7bf-4747-8315-c221c3f20b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471527127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.471527127
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.678554909
Short name T85
Test name
Test status
Simulation time 27763270 ps
CPU time 0.74 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:32 PM PDT 24
Peak memory 196240 kb
Host smart-c2fd3c17-5070-4dfe-ae8b-1656d2b048d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678554909 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.678554909
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3881065124
Short name T735
Test name
Test status
Simulation time 337762877 ps
CPU time 1.46 seconds
Started Mar 14 01:11:33 PM PDT 24
Finished Mar 14 01:11:35 PM PDT 24
Peak memory 198264 kb
Host smart-3df5a1ce-6dc8-42b4-bceb-771ba14b4f47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881065124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3881065124
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3378906548
Short name T47
Test name
Test status
Simulation time 189939203 ps
CPU time 0.87 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 197060 kb
Host smart-c156b8ae-a1cf-474b-bd33-921e409e464b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378906548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3378906548
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1435765448
Short name T734
Test name
Test status
Simulation time 42397563 ps
CPU time 1.04 seconds
Started Mar 14 01:11:34 PM PDT 24
Finished Mar 14 01:11:35 PM PDT 24
Peak memory 198072 kb
Host smart-45e41738-d794-4973-8d4d-9379e29e3633
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435765448 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1435765448
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2423322583
Short name T786
Test name
Test status
Simulation time 49142578 ps
CPU time 0.61 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 194768 kb
Host smart-05b2d198-ed61-43cc-98e1-08b4a12fe59a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423322583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2423322583
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1187132827
Short name T781
Test name
Test status
Simulation time 22765905 ps
CPU time 0.61 seconds
Started Mar 14 01:11:33 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 193800 kb
Host smart-41f57507-8e48-446d-a21c-624be86c4f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187132827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1187132827
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1002663
Short name T832
Test name
Test status
Simulation time 41345398 ps
CPU time 0.72 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 195276 kb
Host smart-2d28d54f-81e2-498b-b22b-1da7e7fda644
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002663 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.gpio_same_csr_outstanding.1002663
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3583957479
Short name T810
Test name
Test status
Simulation time 58622867 ps
CPU time 3.56 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:35 PM PDT 24
Peak memory 198208 kb
Host smart-cfd09bd0-dd38-44e6-a6b5-607cd80a9e37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583957479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3583957479
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3256484145
Short name T46
Test name
Test status
Simulation time 73429357 ps
CPU time 1.11 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:32 PM PDT 24
Peak memory 198188 kb
Host smart-fa6ace82-4523-42aa-bc82-c70093ffbcf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256484145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3256484145
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2790808442
Short name T766
Test name
Test status
Simulation time 19844204 ps
CPU time 0.93 seconds
Started Mar 14 01:11:32 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 198084 kb
Host smart-7633bc13-cbf8-49d0-9338-c496a4689d03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790808442 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2790808442
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3151839780
Short name T830
Test name
Test status
Simulation time 56667816 ps
CPU time 0.62 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 194808 kb
Host smart-72d38004-f154-4539-b71a-c45dc89ec60f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151839780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3151839780
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.328648826
Short name T782
Test name
Test status
Simulation time 14792657 ps
CPU time 0.62 seconds
Started Mar 14 01:11:32 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 193776 kb
Host smart-321f69de-0513-4d96-a0bb-27b073751eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328648826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.328648826
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2564217115
Short name T83
Test name
Test status
Simulation time 24275623 ps
CPU time 0.61 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 195036 kb
Host smart-0b05f2cf-f5a4-47dc-a1eb-301b9caf7399
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564217115 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2564217115
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.887150026
Short name T764
Test name
Test status
Simulation time 347612553 ps
CPU time 3.11 seconds
Started Mar 14 01:11:32 PM PDT 24
Finished Mar 14 01:11:35 PM PDT 24
Peak memory 198224 kb
Host smart-515e0e7d-28a0-4394-a7d3-707c91d34d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887150026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.887150026
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1882759052
Short name T822
Test name
Test status
Simulation time 93777246 ps
CPU time 0.96 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 197404 kb
Host smart-92325540-ecce-4bad-b7a9-37b4f4ac5b1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882759052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1882759052
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3846007935
Short name T722
Test name
Test status
Simulation time 101923055 ps
CPU time 1.68 seconds
Started Mar 14 01:11:33 PM PDT 24
Finished Mar 14 01:11:35 PM PDT 24
Peak memory 198292 kb
Host smart-0a992ce1-a400-454c-85f6-a1e51d25c053
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846007935 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3846007935
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.294250133
Short name T84
Test name
Test status
Simulation time 24212035 ps
CPU time 0.62 seconds
Started Mar 14 01:11:33 PM PDT 24
Finished Mar 14 01:11:34 PM PDT 24
Peak memory 194572 kb
Host smart-f32a750d-500e-4628-843f-15552d620f57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294250133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.294250133
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1115961625
Short name T744
Test name
Test status
Simulation time 54341367 ps
CPU time 0.62 seconds
Started Mar 14 01:11:33 PM PDT 24
Finished Mar 14 01:11:34 PM PDT 24
Peak memory 193880 kb
Host smart-bcac4e3e-5b68-46e6-b7f4-5b8c1a159b82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115961625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1115961625
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3008872059
Short name T836
Test name
Test status
Simulation time 17893299 ps
CPU time 0.7 seconds
Started Mar 14 01:11:33 PM PDT 24
Finished Mar 14 01:11:34 PM PDT 24
Peak memory 195472 kb
Host smart-397bf4f5-c83b-4e74-945f-168d195fd63e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008872059 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3008872059
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1709170587
Short name T838
Test name
Test status
Simulation time 29975174 ps
CPU time 1.52 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 198180 kb
Host smart-2eefc95e-46c7-4564-8ea3-e918ee8563dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709170587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1709170587
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1109759381
Short name T840
Test name
Test status
Simulation time 85095299 ps
CPU time 1.14 seconds
Started Mar 14 01:11:33 PM PDT 24
Finished Mar 14 01:11:34 PM PDT 24
Peak memory 198240 kb
Host smart-502f5c31-4bd5-47bf-a16a-f9287e92393e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109759381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1109759381
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3414385721
Short name T812
Test name
Test status
Simulation time 33977460 ps
CPU time 0.84 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 198100 kb
Host smart-69c5d1a3-0f13-441e-9d6f-457758cdcf24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414385721 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3414385721
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3911972567
Short name T721
Test name
Test status
Simulation time 15478526 ps
CPU time 0.64 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 194940 kb
Host smart-e4fdb4e7-6cbd-46d7-8329-da8fcc3ec1a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911972567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3911972567
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2778537203
Short name T834
Test name
Test status
Simulation time 31380778 ps
CPU time 0.63 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 193956 kb
Host smart-277318ce-3ae6-4e24-b46b-5a8b459b9c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778537203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2778537203
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3465938008
Short name T107
Test name
Test status
Simulation time 488245850 ps
CPU time 0.75 seconds
Started Mar 14 01:11:32 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 196268 kb
Host smart-0be61da4-d982-4e1b-b9c9-feb59eb8be0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465938008 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3465938008
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1411344568
Short name T738
Test name
Test status
Simulation time 48045923 ps
CPU time 1.32 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198272 kb
Host smart-09c10ea9-e11e-4df7-873d-88b701cf7505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411344568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1411344568
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.172350030
Short name T805
Test name
Test status
Simulation time 318369549 ps
CPU time 1.18 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198244 kb
Host smart-9942f452-3151-4083-a183-8fcd474ae113
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172350030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.172350030
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2994271224
Short name T800
Test name
Test status
Simulation time 35455856 ps
CPU time 0.99 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:56 PM PDT 24
Peak memory 198048 kb
Host smart-425b1922-6a7c-4ef6-b12c-feb7d55dc62f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994271224 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2994271224
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.934325661
Short name T839
Test name
Test status
Simulation time 13444757 ps
CPU time 0.62 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 193308 kb
Host smart-674aa661-6144-4f1c-ac71-0951598c38ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934325661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.934325661
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3794076611
Short name T723
Test name
Test status
Simulation time 18581616 ps
CPU time 0.56 seconds
Started Mar 14 01:11:46 PM PDT 24
Finished Mar 14 01:11:47 PM PDT 24
Peak memory 193804 kb
Host smart-a5b9571d-b447-40da-9b78-f6bb7e64b8b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794076611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3794076611
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.507480522
Short name T827
Test name
Test status
Simulation time 24076175 ps
CPU time 0.75 seconds
Started Mar 14 01:11:43 PM PDT 24
Finished Mar 14 01:11:44 PM PDT 24
Peak memory 194692 kb
Host smart-ad162593-7697-41b4-9fe9-659becc5afb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507480522 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.507480522
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.4139895523
Short name T825
Test name
Test status
Simulation time 181360566 ps
CPU time 1.93 seconds
Started Mar 14 01:11:51 PM PDT 24
Finished Mar 14 01:11:53 PM PDT 24
Peak memory 198280 kb
Host smart-faaa71be-a9b9-45d5-a5ee-af430f809339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139895523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.4139895523
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2001079411
Short name T50
Test name
Test status
Simulation time 80129549 ps
CPU time 1.16 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:57 PM PDT 24
Peak memory 198212 kb
Host smart-8b521a2f-2c49-4ca7-91b0-37d0df45015d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001079411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2001079411
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1482490749
Short name T776
Test name
Test status
Simulation time 27382341 ps
CPU time 0.8 seconds
Started Mar 14 01:11:45 PM PDT 24
Finished Mar 14 01:11:47 PM PDT 24
Peak memory 197676 kb
Host smart-e5af86fc-d9ff-4fc2-a6d3-63c4580285d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482490749 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1482490749
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2845836529
Short name T96
Test name
Test status
Simulation time 14229895 ps
CPU time 0.6 seconds
Started Mar 14 01:11:45 PM PDT 24
Finished Mar 14 01:11:46 PM PDT 24
Peak memory 194344 kb
Host smart-6d0f37ad-4ca6-4c34-9c6e-d134516b1955
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845836529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2845836529
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.642781447
Short name T774
Test name
Test status
Simulation time 14923271 ps
CPU time 0.59 seconds
Started Mar 14 01:11:40 PM PDT 24
Finished Mar 14 01:11:41 PM PDT 24
Peak memory 194476 kb
Host smart-0929fc20-7946-441b-9fe5-9e51bece2a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642781447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.642781447
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2308417157
Short name T831
Test name
Test status
Simulation time 33129071 ps
CPU time 0.72 seconds
Started Mar 14 01:11:47 PM PDT 24
Finished Mar 14 01:11:48 PM PDT 24
Peak memory 196812 kb
Host smart-2b9cec9c-84db-44b9-a611-169e76069ade
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308417157 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2308417157
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2445780694
Short name T747
Test name
Test status
Simulation time 586081142 ps
CPU time 1.51 seconds
Started Mar 14 01:11:51 PM PDT 24
Finished Mar 14 01:11:53 PM PDT 24
Peak memory 198256 kb
Host smart-df496a0e-69fb-4feb-86ea-73ac2e13539e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445780694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2445780694
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2178648840
Short name T51
Test name
Test status
Simulation time 120414967 ps
CPU time 1.52 seconds
Started Mar 14 01:11:43 PM PDT 24
Finished Mar 14 01:11:45 PM PDT 24
Peak memory 198128 kb
Host smart-a7ff5d9f-d0a8-4a2f-b649-315170b4bad1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178648840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2178648840
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.68001018
Short name T767
Test name
Test status
Simulation time 42138414 ps
CPU time 0.96 seconds
Started Mar 14 01:11:41 PM PDT 24
Finished Mar 14 01:11:42 PM PDT 24
Peak memory 198096 kb
Host smart-d713aaad-f7a7-40f5-9549-8d579bb033f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68001018 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.68001018
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2362025215
Short name T110
Test name
Test status
Simulation time 43168984 ps
CPU time 0.56 seconds
Started Mar 14 01:11:46 PM PDT 24
Finished Mar 14 01:11:47 PM PDT 24
Peak memory 195344 kb
Host smart-ad21e993-31d4-4634-93af-17b3935953b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362025215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2362025215
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.869524718
Short name T790
Test name
Test status
Simulation time 44800196 ps
CPU time 0.6 seconds
Started Mar 14 01:11:41 PM PDT 24
Finished Mar 14 01:11:42 PM PDT 24
Peak memory 193844 kb
Host smart-693e8128-62d1-4188-87b5-954b27718cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869524718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.869524718
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2055216453
Short name T89
Test name
Test status
Simulation time 45189118 ps
CPU time 0.64 seconds
Started Mar 14 01:11:40 PM PDT 24
Finished Mar 14 01:11:40 PM PDT 24
Peak memory 195676 kb
Host smart-e8b99a5e-2ed6-4eea-9f68-1f17aae593a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055216453 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2055216453
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.768733089
Short name T742
Test name
Test status
Simulation time 102745278 ps
CPU time 1.14 seconds
Started Mar 14 01:11:40 PM PDT 24
Finished Mar 14 01:11:41 PM PDT 24
Peak memory 198120 kb
Host smart-878c5002-c7a4-4ce8-95cb-1840b60db4f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768733089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.768733089
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1935373229
Short name T48
Test name
Test status
Simulation time 128953278 ps
CPU time 1.2 seconds
Started Mar 14 01:11:45 PM PDT 24
Finished Mar 14 01:11:46 PM PDT 24
Peak memory 198100 kb
Host smart-cea40388-4c9e-4308-92e2-3d4eecf4ba80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935373229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1935373229
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3437294235
Short name T777
Test name
Test status
Simulation time 30877361 ps
CPU time 0.79 seconds
Started Mar 14 01:11:47 PM PDT 24
Finished Mar 14 01:11:48 PM PDT 24
Peak memory 198068 kb
Host smart-ceb59120-5ec4-42d2-8ab2-4e40ef9c01b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437294235 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3437294235
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.552646766
Short name T109
Test name
Test status
Simulation time 45987863 ps
CPU time 0.57 seconds
Started Mar 14 01:11:47 PM PDT 24
Finished Mar 14 01:11:48 PM PDT 24
Peak memory 194708 kb
Host smart-a99dad5f-9a59-439f-9908-370ba08a02c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552646766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.552646766
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3977651220
Short name T730
Test name
Test status
Simulation time 14928949 ps
CPU time 0.6 seconds
Started Mar 14 01:11:49 PM PDT 24
Finished Mar 14 01:11:50 PM PDT 24
Peak memory 194484 kb
Host smart-b697ef82-57f8-4755-9acc-7d85b62557ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977651220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3977651220
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1441951214
Short name T817
Test name
Test status
Simulation time 66401443 ps
CPU time 0.65 seconds
Started Mar 14 01:11:40 PM PDT 24
Finished Mar 14 01:11:41 PM PDT 24
Peak memory 195692 kb
Host smart-60008dde-5adf-4e41-b911-8f315e332474
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441951214 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1441951214
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.321435112
Short name T814
Test name
Test status
Simulation time 41554072 ps
CPU time 1.98 seconds
Started Mar 14 01:11:47 PM PDT 24
Finished Mar 14 01:11:50 PM PDT 24
Peak memory 198252 kb
Host smart-3dc29506-210e-4103-8602-79b92ec77224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321435112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.321435112
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.193404212
Short name T54
Test name
Test status
Simulation time 158041207 ps
CPU time 0.88 seconds
Started Mar 14 01:11:48 PM PDT 24
Finished Mar 14 01:11:49 PM PDT 24
Peak memory 197336 kb
Host smart-857fe435-9019-4d04-8243-89920a570ebe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193404212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.193404212
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2346256042
Short name T97
Test name
Test status
Simulation time 28115073 ps
CPU time 0.86 seconds
Started Mar 14 01:11:24 PM PDT 24
Finished Mar 14 01:11:25 PM PDT 24
Peak memory 196144 kb
Host smart-7e068107-8e2c-48f0-8e4c-31883f7ac5fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346256042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2346256042
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1640187861
Short name T737
Test name
Test status
Simulation time 35914119 ps
CPU time 1.35 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 196968 kb
Host smart-1b57c508-905b-47eb-9999-aee07c6b5a75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640187861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1640187861
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1800797526
Short name T733
Test name
Test status
Simulation time 45524187 ps
CPU time 0.6 seconds
Started Mar 14 01:11:23 PM PDT 24
Finished Mar 14 01:11:23 PM PDT 24
Peak memory 194420 kb
Host smart-6e7686a2-cbac-4f2c-8d8e-2aeda44ab710
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800797526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1800797526
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4136831631
Short name T833
Test name
Test status
Simulation time 65606354 ps
CPU time 0.93 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 198048 kb
Host smart-477c7e5b-24f9-4e10-92d2-9707a649e7de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136831631 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.4136831631
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3945227425
Short name T780
Test name
Test status
Simulation time 37352382 ps
CPU time 0.6 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 194928 kb
Host smart-8183e09b-4828-427e-a359-566fadb7a73e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945227425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3945227425
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1567138295
Short name T727
Test name
Test status
Simulation time 15750503 ps
CPU time 0.61 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:26 PM PDT 24
Peak memory 194496 kb
Host smart-4cf5b370-cea3-4daa-b4f0-aa9247aa29fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567138295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1567138295
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.453084683
Short name T837
Test name
Test status
Simulation time 68169868 ps
CPU time 0.82 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 196460 kb
Host smart-4e6a3974-fb7e-4d4a-91ce-9a12546fb947
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453084683 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.453084683
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.274654572
Short name T752
Test name
Test status
Simulation time 132059428 ps
CPU time 1.5 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198228 kb
Host smart-65540720-9efa-4dee-a4ad-f7b1576209fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274654572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.274654572
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1434407152
Short name T824
Test name
Test status
Simulation time 18898076 ps
CPU time 0.64 seconds
Started Mar 14 01:11:49 PM PDT 24
Finished Mar 14 01:11:50 PM PDT 24
Peak memory 193884 kb
Host smart-9e04a6b8-ef7c-4bde-bfc9-dac34dd33d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434407152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1434407152
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1916160326
Short name T743
Test name
Test status
Simulation time 36230157 ps
CPU time 0.56 seconds
Started Mar 14 01:11:40 PM PDT 24
Finished Mar 14 01:11:40 PM PDT 24
Peak memory 194444 kb
Host smart-0dd4139c-fe63-4be1-9904-dd99e95002c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916160326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1916160326
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.256222561
Short name T826
Test name
Test status
Simulation time 96605299 ps
CPU time 0.58 seconds
Started Mar 14 01:11:50 PM PDT 24
Finished Mar 14 01:11:51 PM PDT 24
Peak memory 193832 kb
Host smart-fe76adcd-f134-499f-bdde-946bea6b6ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256222561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.256222561
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.757081083
Short name T750
Test name
Test status
Simulation time 15541427 ps
CPU time 0.58 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:56 PM PDT 24
Peak memory 193760 kb
Host smart-6d68bc9b-36b6-4e53-ab17-f4bdbd14beba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757081083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.757081083
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3601098581
Short name T785
Test name
Test status
Simulation time 56287811 ps
CPU time 0.6 seconds
Started Mar 14 01:11:43 PM PDT 24
Finished Mar 14 01:11:43 PM PDT 24
Peak memory 193732 kb
Host smart-28a557f1-9ede-44b1-81f2-98e43b070ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601098581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3601098581
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.819929103
Short name T818
Test name
Test status
Simulation time 48499124 ps
CPU time 0.6 seconds
Started Mar 14 01:11:51 PM PDT 24
Finished Mar 14 01:11:51 PM PDT 24
Peak memory 193844 kb
Host smart-6a68d0ea-8d30-4b37-bb6b-61da641413ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819929103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.819929103
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3100639287
Short name T813
Test name
Test status
Simulation time 13577439 ps
CPU time 0.61 seconds
Started Mar 14 01:11:43 PM PDT 24
Finished Mar 14 01:11:44 PM PDT 24
Peak memory 194372 kb
Host smart-3b31d94c-4a63-4d6a-bc32-06c442bf208e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100639287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3100639287
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.59795052
Short name T769
Test name
Test status
Simulation time 15714720 ps
CPU time 0.58 seconds
Started Mar 14 01:11:39 PM PDT 24
Finished Mar 14 01:11:40 PM PDT 24
Peak memory 193808 kb
Host smart-4cb34908-cfe3-4435-85e6-300d293234f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59795052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.59795052
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1173580409
Short name T719
Test name
Test status
Simulation time 33724573 ps
CPU time 0.63 seconds
Started Mar 14 01:11:39 PM PDT 24
Finished Mar 14 01:11:40 PM PDT 24
Peak memory 194556 kb
Host smart-8a8925f1-cf17-4fd5-8552-cb79310000d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173580409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1173580409
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.484065812
Short name T819
Test name
Test status
Simulation time 54870730 ps
CPU time 0.58 seconds
Started Mar 14 01:11:47 PM PDT 24
Finished Mar 14 01:11:48 PM PDT 24
Peak memory 193744 kb
Host smart-0d018c10-d7cf-4859-9bda-a65bfc8196db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484065812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.484065812
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2098135976
Short name T98
Test name
Test status
Simulation time 50904819 ps
CPU time 0.73 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:26 PM PDT 24
Peak memory 196040 kb
Host smart-181dec1e-4dd3-4129-8005-d2ddf8c720b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098135976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2098135976
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.694026283
Short name T90
Test name
Test status
Simulation time 219586281 ps
CPU time 2.5 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 198112 kb
Host smart-9faf763d-20a9-4e66-bed2-6e1fc9a83d7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694026283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.694026283
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3848057961
Short name T95
Test name
Test status
Simulation time 35644662 ps
CPU time 0.68 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 195704 kb
Host smart-514070ae-67a2-424f-9231-1064ec11c233
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848057961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3848057961
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2250740590
Short name T771
Test name
Test status
Simulation time 265848299 ps
CPU time 1.08 seconds
Started Mar 14 01:11:29 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198296 kb
Host smart-0d02db19-4c44-44c5-adcd-03887da1a454
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250740590 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2250740590
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2506520854
Short name T726
Test name
Test status
Simulation time 14746457 ps
CPU time 0.61 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 194452 kb
Host smart-f4dacc42-cb60-46e9-b25e-a57e0e3049da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506520854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2506520854
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1739990466
Short name T724
Test name
Test status
Simulation time 57136167 ps
CPU time 0.64 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:25 PM PDT 24
Peak memory 193864 kb
Host smart-0d40d92c-e321-4d03-bc3e-834fcf5bb7a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739990466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1739990466
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.142857348
Short name T104
Test name
Test status
Simulation time 74935894 ps
CPU time 0.68 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 195552 kb
Host smart-075e1d4a-5027-48da-b20b-ef058e0092b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142857348 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.142857348
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.822734382
Short name T788
Test name
Test status
Simulation time 27734925 ps
CPU time 1.4 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 198152 kb
Host smart-17d45f2c-6d14-4c40-8f6a-34076876802c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822734382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.822734382
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4271391816
Short name T841
Test name
Test status
Simulation time 300877791 ps
CPU time 1.11 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 198152 kb
Host smart-e9a7d1c8-a74a-4519-9905-e21b566d8130
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271391816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.4271391816
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1235818213
Short name T823
Test name
Test status
Simulation time 20294344 ps
CPU time 0.6 seconds
Started Mar 14 01:11:50 PM PDT 24
Finished Mar 14 01:11:51 PM PDT 24
Peak memory 193852 kb
Host smart-6c2b72e3-bca0-4534-9208-8f2562bfc534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235818213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1235818213
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1759498704
Short name T731
Test name
Test status
Simulation time 145612866 ps
CPU time 0.62 seconds
Started Mar 14 01:11:48 PM PDT 24
Finished Mar 14 01:11:49 PM PDT 24
Peak memory 194560 kb
Host smart-bcb573eb-118b-4b87-8d6a-b74e1af11201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759498704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1759498704
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3250066590
Short name T787
Test name
Test status
Simulation time 13461932 ps
CPU time 0.59 seconds
Started Mar 14 01:11:49 PM PDT 24
Finished Mar 14 01:11:49 PM PDT 24
Peak memory 193832 kb
Host smart-685cbf6e-354f-487e-a04c-c32721c1fa55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250066590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3250066590
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1291824176
Short name T768
Test name
Test status
Simulation time 35436120 ps
CPU time 0.63 seconds
Started Mar 14 01:11:49 PM PDT 24
Finished Mar 14 01:11:50 PM PDT 24
Peak memory 194580 kb
Host smart-81e559e0-80e6-48b2-85fc-b3db752eee78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291824176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1291824176
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.4185761363
Short name T758
Test name
Test status
Simulation time 46943230 ps
CPU time 0.6 seconds
Started Mar 14 01:11:50 PM PDT 24
Finished Mar 14 01:11:51 PM PDT 24
Peak memory 194496 kb
Host smart-924d12df-f085-4832-bf6f-ad94b5e2724b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185761363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.4185761363
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.872601070
Short name T783
Test name
Test status
Simulation time 42570389 ps
CPU time 0.6 seconds
Started Mar 14 01:11:38 PM PDT 24
Finished Mar 14 01:11:39 PM PDT 24
Peak memory 194468 kb
Host smart-1f0f0169-6784-4203-b468-9b253c1fc1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872601070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.872601070
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2775056685
Short name T770
Test name
Test status
Simulation time 21944050 ps
CPU time 0.59 seconds
Started Mar 14 01:11:40 PM PDT 24
Finished Mar 14 01:11:41 PM PDT 24
Peak memory 193812 kb
Host smart-2c38169b-f847-4411-8f5a-793520eb1703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775056685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2775056685
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4120295809
Short name T798
Test name
Test status
Simulation time 74256641 ps
CPU time 0.6 seconds
Started Mar 14 01:11:46 PM PDT 24
Finished Mar 14 01:11:48 PM PDT 24
Peak memory 193828 kb
Host smart-983e817b-d1ed-46f8-af28-a57f68c44ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120295809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4120295809
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2554212466
Short name T811
Test name
Test status
Simulation time 13597031 ps
CPU time 0.61 seconds
Started Mar 14 01:11:40 PM PDT 24
Finished Mar 14 01:11:40 PM PDT 24
Peak memory 193740 kb
Host smart-8500fd3f-e762-4521-ba84-2a997187417e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554212466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2554212466
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.4252684880
Short name T775
Test name
Test status
Simulation time 36086365 ps
CPU time 0.59 seconds
Started Mar 14 01:11:41 PM PDT 24
Finished Mar 14 01:11:42 PM PDT 24
Peak memory 194464 kb
Host smart-5b0023d6-9eb6-4cc1-9117-1720f7c39fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252684880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.4252684880
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.932366719
Short name T794
Test name
Test status
Simulation time 174079932 ps
CPU time 2.39 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 198124 kb
Host smart-cd62d978-e51a-4531-8fc1-8940490d360b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932366719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.932366719
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2930824245
Short name T756
Test name
Test status
Simulation time 34851160 ps
CPU time 0.62 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 194760 kb
Host smart-de578877-806b-4ac7-b1de-9020a5aa2b43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930824245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2930824245
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2616074547
Short name T779
Test name
Test status
Simulation time 167754909 ps
CPU time 0.87 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 197968 kb
Host smart-0846287d-33d6-44d4-9799-12c0fbe6ab6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616074547 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2616074547
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1331942805
Short name T91
Test name
Test status
Simulation time 31729584 ps
CPU time 0.57 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 193840 kb
Host smart-f858a2e7-f872-44ba-ba32-40c6e6cfc7d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331942805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1331942805
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2431639477
Short name T765
Test name
Test status
Simulation time 13253692 ps
CPU time 0.63 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 193880 kb
Host smart-27b3719f-a76b-4bd2-82cb-c3e0117dd175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431639477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2431639477
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2932612761
Short name T108
Test name
Test status
Simulation time 27490867 ps
CPU time 0.78 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 195860 kb
Host smart-8a58ea67-4740-4e25-a96b-6010c9a39c85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932612761 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2932612761
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2021199799
Short name T755
Test name
Test status
Simulation time 103221932 ps
CPU time 2.01 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 198096 kb
Host smart-0a6cb33f-f48b-4fd9-b351-fde41b675144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021199799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2021199799
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.544572559
Short name T52
Test name
Test status
Simulation time 396063093 ps
CPU time 1.48 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198208 kb
Host smart-6cf5368c-782f-4c50-9ffa-a3116adc7697
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544572559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.544572559
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.304461445
Short name T757
Test name
Test status
Simulation time 80979481 ps
CPU time 0.64 seconds
Started Mar 14 01:11:49 PM PDT 24
Finished Mar 14 01:11:50 PM PDT 24
Peak memory 194568 kb
Host smart-7bb3c878-2d77-4e8d-972c-b016fa68f929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304461445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.304461445
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2069402252
Short name T797
Test name
Test status
Simulation time 258761987 ps
CPU time 0.64 seconds
Started Mar 14 01:11:45 PM PDT 24
Finished Mar 14 01:11:47 PM PDT 24
Peak memory 194136 kb
Host smart-cc7348b9-bf97-44b0-be7a-c0b61022c1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069402252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2069402252
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3760236119
Short name T759
Test name
Test status
Simulation time 17396260 ps
CPU time 0.6 seconds
Started Mar 14 01:11:48 PM PDT 24
Finished Mar 14 01:11:49 PM PDT 24
Peak memory 193848 kb
Host smart-d7a1c93d-0fbf-41ea-a6d6-0a234f916187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760236119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3760236119
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3720124839
Short name T736
Test name
Test status
Simulation time 36231544 ps
CPU time 0.59 seconds
Started Mar 14 01:11:53 PM PDT 24
Finished Mar 14 01:11:55 PM PDT 24
Peak memory 193680 kb
Host smart-d0157e3c-acd9-413d-8edd-8ec4b292d6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720124839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3720124839
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.999113774
Short name T749
Test name
Test status
Simulation time 48569095 ps
CPU time 0.6 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:56 PM PDT 24
Peak memory 193776 kb
Host smart-14061b9e-c3e8-4da8-aef6-9122a4949e77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999113774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.999113774
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.5607817
Short name T728
Test name
Test status
Simulation time 16220180 ps
CPU time 0.62 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:56 PM PDT 24
Peak memory 193892 kb
Host smart-b5491174-a0a9-421d-82ad-3eebd801e172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5607817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.5607817
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1592781400
Short name T729
Test name
Test status
Simulation time 33348614 ps
CPU time 0.59 seconds
Started Mar 14 01:11:54 PM PDT 24
Finished Mar 14 01:11:55 PM PDT 24
Peak memory 193756 kb
Host smart-b4a33fd4-c1f5-47d3-89a1-f50276a7c71e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592781400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1592781400
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3337419904
Short name T772
Test name
Test status
Simulation time 47542100 ps
CPU time 0.63 seconds
Started Mar 14 01:11:54 PM PDT 24
Finished Mar 14 01:11:55 PM PDT 24
Peak memory 193836 kb
Host smart-4a53abb1-08ba-4852-89a2-90ed4bfeab44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337419904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3337419904
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3349637747
Short name T808
Test name
Test status
Simulation time 15554741 ps
CPU time 0.62 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:55 PM PDT 24
Peak memory 193852 kb
Host smart-ad940a1b-50da-4250-a0b0-62bd58ec7533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349637747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3349637747
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2947426702
Short name T828
Test name
Test status
Simulation time 44732086 ps
CPU time 0.72 seconds
Started Mar 14 01:11:52 PM PDT 24
Finished Mar 14 01:11:54 PM PDT 24
Peak memory 193820 kb
Host smart-0cc63eb1-12e7-4f17-abfc-7136797d106e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947426702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2947426702
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1537843638
Short name T751
Test name
Test status
Simulation time 20309339 ps
CPU time 0.75 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 198024 kb
Host smart-b59541fe-b7fc-480e-86f8-d2e31be412ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537843638 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1537843638
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1134354603
Short name T94
Test name
Test status
Simulation time 16347027 ps
CPU time 0.63 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:27 PM PDT 24
Peak memory 195164 kb
Host smart-23851dc9-3a38-44be-86a4-48aab09cfb7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134354603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1134354603
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3678950700
Short name T739
Test name
Test status
Simulation time 10902218 ps
CPU time 0.57 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 194456 kb
Host smart-0e0774e9-978b-4056-80cb-6c02598b159c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678950700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3678950700
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3703218123
Short name T103
Test name
Test status
Simulation time 162286786 ps
CPU time 0.89 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 196264 kb
Host smart-26f8de40-51a7-4ab5-a245-52805e591dcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703218123 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3703218123
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4149957999
Short name T761
Test name
Test status
Simulation time 141574245 ps
CPU time 2.18 seconds
Started Mar 14 01:11:32 PM PDT 24
Finished Mar 14 01:11:34 PM PDT 24
Peak memory 198236 kb
Host smart-baa35475-0000-44ed-b2a7-4210bd3832e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149957999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.4149957999
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3700666697
Short name T38
Test name
Test status
Simulation time 207232830 ps
CPU time 1.44 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:27 PM PDT 24
Peak memory 198192 kb
Host smart-a29d0983-c16d-4ae1-8fd0-41f7461205c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700666697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3700666697
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3936683741
Short name T820
Test name
Test status
Simulation time 36663496 ps
CPU time 0.78 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 197932 kb
Host smart-85f23435-f8a5-47ff-ac5a-8ae7a59a42c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936683741 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3936683741
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2138674964
Short name T88
Test name
Test status
Simulation time 14806988 ps
CPU time 0.62 seconds
Started Mar 14 01:11:25 PM PDT 24
Finished Mar 14 01:11:26 PM PDT 24
Peak memory 194944 kb
Host smart-ba0eeede-04e8-490e-823c-ac52caf7bc5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138674964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2138674964
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.54220348
Short name T807
Test name
Test status
Simulation time 13338719 ps
CPU time 0.59 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 193780 kb
Host smart-1f494b52-1ba2-45b2-8827-8d0087567d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54220348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.54220348
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.749583921
Short name T102
Test name
Test status
Simulation time 33183954 ps
CPU time 0.66 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:27 PM PDT 24
Peak memory 195004 kb
Host smart-f9a9cc34-2fe9-4513-8311-b87dd35c7f6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749583921 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.749583921
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2711698682
Short name T773
Test name
Test status
Simulation time 357174207 ps
CPU time 2.15 seconds
Started Mar 14 01:11:23 PM PDT 24
Finished Mar 14 01:11:26 PM PDT 24
Peak memory 198244 kb
Host smart-8af04ab8-91a7-45b6-a17c-8a72fd30a886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711698682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2711698682
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.59225900
Short name T778
Test name
Test status
Simulation time 349974321 ps
CPU time 1.45 seconds
Started Mar 14 01:11:26 PM PDT 24
Finished Mar 14 01:11:28 PM PDT 24
Peak memory 198220 kb
Host smart-77aac888-6fc2-4a56-ab44-a5a54a179845
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59225900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.gpio_tl_intg_err.59225900
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4028530823
Short name T762
Test name
Test status
Simulation time 54540774 ps
CPU time 0.9 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198108 kb
Host smart-1dc038f0-8570-4c82-aade-6c11a40a80f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028530823 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4028530823
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1130722609
Short name T93
Test name
Test status
Simulation time 14334006 ps
CPU time 0.61 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 194444 kb
Host smart-937d494f-99de-4281-afa5-38458f7ff92a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130722609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1130722609
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2065563217
Short name T803
Test name
Test status
Simulation time 12846983 ps
CPU time 0.6 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 193816 kb
Host smart-090ab6df-81dd-4b06-96c3-99702f95b92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065563217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2065563217
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3069792848
Short name T105
Test name
Test status
Simulation time 38623998 ps
CPU time 0.88 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 196608 kb
Host smart-22cb45c6-b7b4-4086-9a09-de5b74788dfb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069792848 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3069792848
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.723368653
Short name T720
Test name
Test status
Simulation time 133288992 ps
CPU time 2.31 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 198276 kb
Host smart-246c1013-9d0c-4a3c-8929-8e91e51c713a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723368653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.723368653
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3744310472
Short name T802
Test name
Test status
Simulation time 71661106 ps
CPU time 0.92 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 197380 kb
Host smart-4f61f887-fa90-4fe3-9eea-5b39844678d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744310472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3744310472
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1417870911
Short name T791
Test name
Test status
Simulation time 78216027 ps
CPU time 1.1 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198040 kb
Host smart-0378ff20-de8a-4454-928c-8f844f945199
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417870911 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1417870911
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.822724549
Short name T92
Test name
Test status
Simulation time 13977954 ps
CPU time 0.61 seconds
Started Mar 14 01:11:27 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 194924 kb
Host smart-e480dc60-7f3d-4388-a0d4-b9b79a183d71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822724549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.822724549
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3888947874
Short name T799
Test name
Test status
Simulation time 53787648 ps
CPU time 0.64 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:29 PM PDT 24
Peak memory 193824 kb
Host smart-60e0038c-70d0-4d01-b5f4-f3b87121b3bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888947874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3888947874
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1917377889
Short name T795
Test name
Test status
Simulation time 39718324 ps
CPU time 0.85 seconds
Started Mar 14 01:11:29 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 196444 kb
Host smart-ef58d473-83ff-4629-9563-97e93f42813e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917377889 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1917377889
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1314473889
Short name T784
Test name
Test status
Simulation time 23663754 ps
CPU time 1.41 seconds
Started Mar 14 01:11:28 PM PDT 24
Finished Mar 14 01:11:30 PM PDT 24
Peak memory 198272 kb
Host smart-437fc006-84e7-4912-bce2-b13aff673785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314473889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1314473889
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3043464515
Short name T740
Test name
Test status
Simulation time 33626625 ps
CPU time 0.75 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 197060 kb
Host smart-0de33e43-cd8e-45d5-9e6a-f4a047e950a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043464515 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3043464515
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2329073252
Short name T745
Test name
Test status
Simulation time 108009114 ps
CPU time 0.64 seconds
Started Mar 14 01:11:29 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 195796 kb
Host smart-2f0d02a5-00aa-48eb-a036-1a2241d1f8aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329073252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2329073252
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2718106677
Short name T725
Test name
Test status
Simulation time 22655106 ps
CPU time 0.6 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:32 PM PDT 24
Peak memory 193828 kb
Host smart-9c0a2959-d002-4dbc-aa0b-e2640984a9b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718106677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2718106677
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2202136547
Short name T796
Test name
Test status
Simulation time 16305248 ps
CPU time 0.74 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:31 PM PDT 24
Peak memory 194560 kb
Host smart-b4101321-644a-471d-ad42-067839f60317
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202136547 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2202136547
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.301688273
Short name T748
Test name
Test status
Simulation time 105258496 ps
CPU time 2.26 seconds
Started Mar 14 01:11:30 PM PDT 24
Finished Mar 14 01:11:32 PM PDT 24
Peak memory 198048 kb
Host smart-388dce5b-2ada-4e25-a2d2-94598d5a11f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301688273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.301688273
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2205492085
Short name T789
Test name
Test status
Simulation time 234075134 ps
CPU time 1.17 seconds
Started Mar 14 01:11:31 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 198204 kb
Host smart-09ef7e8b-d720-42d0-9084-d5ebeba1b1c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205492085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2205492085
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3280205589
Short name T643
Test name
Test status
Simulation time 13436378 ps
CPU time 0.64 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:43 PM PDT 24
Peak memory 194992 kb
Host smart-5f59c500-4e1a-432c-a2d9-cce3f657fe60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280205589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3280205589
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3994532292
Short name T226
Test name
Test status
Simulation time 136555736 ps
CPU time 0.6 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 194868 kb
Host smart-3e8512fc-1710-4476-8acd-fbb1dfb73378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994532292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3994532292
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.505110185
Short name T326
Test name
Test status
Simulation time 7007924535 ps
CPU time 18.08 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:23:01 PM PDT 24
Peak memory 198444 kb
Host smart-ddfa694f-a200-4dcd-8bb7-0ea7d7db3960
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505110185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.505110185
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2303772528
Short name T596
Test name
Test status
Simulation time 58199848 ps
CPU time 0.62 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 195484 kb
Host smart-cef50d93-3032-4fcd-8428-5a03f8b3895e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303772528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2303772528
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.4086457667
Short name T603
Test name
Test status
Simulation time 1156651959 ps
CPU time 1.4 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 198308 kb
Host smart-433397ee-f1b2-4938-9e44-27fc4c8714cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086457667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.4086457667
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.810451396
Short name T609
Test name
Test status
Simulation time 27364980 ps
CPU time 1.25 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 197104 kb
Host smart-1f07a8b9-c375-4b96-b218-4b2c6793002d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810451396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.810451396
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2572655164
Short name T460
Test name
Test status
Simulation time 79481979 ps
CPU time 2.4 seconds
Started Mar 14 01:22:44 PM PDT 24
Finished Mar 14 01:22:47 PM PDT 24
Peak memory 197476 kb
Host smart-96937f4b-e7f1-46e4-9e6f-141835852c5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572655164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2572655164
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2702383856
Short name T294
Test name
Test status
Simulation time 36451491 ps
CPU time 1.22 seconds
Started Mar 14 01:22:40 PM PDT 24
Finished Mar 14 01:22:42 PM PDT 24
Peak memory 196056 kb
Host smart-f6c28d7c-571c-41f1-81f2-03940e7ea44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702383856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2702383856
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2917121833
Short name T375
Test name
Test status
Simulation time 112237631 ps
CPU time 1.23 seconds
Started Mar 14 01:22:44 PM PDT 24
Finished Mar 14 01:22:46 PM PDT 24
Peak memory 197404 kb
Host smart-6acd2e8d-72c4-439b-a281-89399c390c0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917121833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2917121833
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.23669572
Short name T203
Test name
Test status
Simulation time 199980335 ps
CPU time 2.36 seconds
Started Mar 14 01:22:44 PM PDT 24
Finished Mar 14 01:22:47 PM PDT 24
Peak memory 198356 kb
Host smart-126e8135-5744-4bfd-865d-433b82a677a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23669572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rando
m_long_reg_writes_reg_reads.23669572
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.189109415
Short name T413
Test name
Test status
Simulation time 123693918 ps
CPU time 1.52 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:43 PM PDT 24
Peak memory 198284 kb
Host smart-30071992-b4d0-4613-b088-a4c6f1d27c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189109415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.189109415
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_stress_all.76044411
Short name T605
Test name
Test status
Simulation time 5736658250 ps
CPU time 118.17 seconds
Started Mar 14 01:22:40 PM PDT 24
Finished Mar 14 01:24:39 PM PDT 24
Peak memory 198492 kb
Host smart-8bf27ad3-adc2-4d24-adc6-6a81acc75d1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76044411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpi
o_stress_all.76044411
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.899730618
Short name T35
Test name
Test status
Simulation time 33746594347 ps
CPU time 438.68 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:30:01 PM PDT 24
Peak memory 198544 kb
Host smart-8ce5ac31-e444-4aca-93ea-a8eb87626c5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=899730618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.899730618
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2642391074
Short name T427
Test name
Test status
Simulation time 13485241 ps
CPU time 0.57 seconds
Started Mar 14 01:22:37 PM PDT 24
Finished Mar 14 01:22:37 PM PDT 24
Peak memory 194880 kb
Host smart-686bae5a-3fe7-420e-ac33-e953ee9a51a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642391074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2642391074
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3067096137
Short name T284
Test name
Test status
Simulation time 63917908 ps
CPU time 0.91 seconds
Started Mar 14 01:22:38 PM PDT 24
Finished Mar 14 01:22:40 PM PDT 24
Peak memory 196120 kb
Host smart-da77da62-09f1-4559-89e3-17a8b007e9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067096137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3067096137
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2722242424
Short name T503
Test name
Test status
Simulation time 510906494 ps
CPU time 17.41 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:23:00 PM PDT 24
Peak memory 195876 kb
Host smart-6163c1d8-bb0e-42cf-9347-fff6930859e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722242424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2722242424
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2771670746
Short name T466
Test name
Test status
Simulation time 85363663 ps
CPU time 0.83 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:22:45 PM PDT 24
Peak memory 196764 kb
Host smart-53defac8-5d69-4b4c-94a6-c4bb13639374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771670746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2771670746
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.4213107788
Short name T26
Test name
Test status
Simulation time 61986015 ps
CPU time 0.75 seconds
Started Mar 14 01:22:47 PM PDT 24
Finished Mar 14 01:22:49 PM PDT 24
Peak memory 195752 kb
Host smart-aff060cf-8333-410a-9340-180688edf614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213107788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.4213107788
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3133133072
Short name T364
Test name
Test status
Simulation time 88819103 ps
CPU time 0.95 seconds
Started Mar 14 01:22:39 PM PDT 24
Finished Mar 14 01:22:40 PM PDT 24
Peak memory 197396 kb
Host smart-4ea60d35-c394-4146-bb8e-f6eab2a08690
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133133072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3133133072
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3496425996
Short name T236
Test name
Test status
Simulation time 50841889 ps
CPU time 1.19 seconds
Started Mar 14 01:22:41 PM PDT 24
Finished Mar 14 01:22:43 PM PDT 24
Peak memory 195844 kb
Host smart-bb0d5d06-24e4-4ba2-b612-aaa0e804a1b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496425996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3496425996
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4250826601
Short name T304
Test name
Test status
Simulation time 31916962 ps
CPU time 0.87 seconds
Started Mar 14 01:22:44 PM PDT 24
Finished Mar 14 01:22:45 PM PDT 24
Peak memory 196800 kb
Host smart-b0e7bf01-2ceb-48f0-ab6a-79e3f4b534a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250826601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4250826601
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1238053350
Short name T234
Test name
Test status
Simulation time 55134214 ps
CPU time 1.01 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 196356 kb
Host smart-ebfad017-6356-464d-9b8d-b27ed6206fcb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238053350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1238053350
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.4126984705
Short name T519
Test name
Test status
Simulation time 1440245046 ps
CPU time 4.19 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:47 PM PDT 24
Peak memory 198164 kb
Host smart-7765607e-a00f-4b76-a943-01b2a68240cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126984705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.4126984705
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3221948289
Short name T43
Test name
Test status
Simulation time 83351797 ps
CPU time 0.94 seconds
Started Mar 14 01:22:40 PM PDT 24
Finished Mar 14 01:22:42 PM PDT 24
Peak memory 214824 kb
Host smart-f8ad13d9-5136-4921-858c-5ca0b781bf11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221948289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3221948289
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.589048967
Short name T167
Test name
Test status
Simulation time 35235835 ps
CPU time 1.18 seconds
Started Mar 14 01:22:44 PM PDT 24
Finished Mar 14 01:22:46 PM PDT 24
Peak memory 196772 kb
Host smart-a80e4bb6-2dfb-4c61-bf30-192d00b8f336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589048967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.589048967
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1806107757
Short name T312
Test name
Test status
Simulation time 174578024 ps
CPU time 1.16 seconds
Started Mar 14 01:22:41 PM PDT 24
Finished Mar 14 01:22:43 PM PDT 24
Peak memory 196092 kb
Host smart-a9ca6b45-4912-465e-9325-ffbd001a80e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806107757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1806107757
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3748908660
Short name T535
Test name
Test status
Simulation time 24970070526 ps
CPU time 151.87 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:25:15 PM PDT 24
Peak memory 198388 kb
Host smart-e16a71b4-670c-420d-8cf3-940fcf8ee165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748908660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3748908660
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.2324853409
Short name T71
Test name
Test status
Simulation time 73674370483 ps
CPU time 457.37 seconds
Started Mar 14 01:22:39 PM PDT 24
Finished Mar 14 01:30:17 PM PDT 24
Peak memory 198384 kb
Host smart-9b2c184e-6ac5-49df-a847-2511d1c81ca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2324853409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.2324853409
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.503491295
Short name T402
Test name
Test status
Simulation time 33487618 ps
CPU time 0.58 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 194044 kb
Host smart-5d4e1020-aee9-4bc3-bb56-2970a3968413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503491295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.503491295
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1454950334
Short name T170
Test name
Test status
Simulation time 17719739 ps
CPU time 0.69 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 194316 kb
Host smart-81a84d5d-7ae9-460c-99d1-b591c1c15055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454950334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1454950334
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2313923281
Short name T231
Test name
Test status
Simulation time 4315482470 ps
CPU time 19.24 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 197144 kb
Host smart-c2abf3f7-868d-402b-b1a6-0f3f0bac1522
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313923281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2313923281
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2612830556
Short name T212
Test name
Test status
Simulation time 38496188 ps
CPU time 0.64 seconds
Started Mar 14 01:23:17 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 194580 kb
Host smart-e3e555b9-f77f-4fac-9acf-916aa5fd3d2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612830556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2612830556
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3878478895
Short name T613
Test name
Test status
Simulation time 25788310 ps
CPU time 0.76 seconds
Started Mar 14 01:23:17 PM PDT 24
Finished Mar 14 01:23:18 PM PDT 24
Peak memory 195624 kb
Host smart-632de7f3-1376-433b-a32a-23fe5cf6a783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878478895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3878478895
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2272302976
Short name T207
Test name
Test status
Simulation time 123807496 ps
CPU time 2.83 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:18 PM PDT 24
Peak memory 198372 kb
Host smart-1f990436-98da-4981-ae29-aa43110b9edd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272302976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2272302976
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.267471947
Short name T227
Test name
Test status
Simulation time 188679238 ps
CPU time 1.62 seconds
Started Mar 14 01:23:23 PM PDT 24
Finished Mar 14 01:23:25 PM PDT 24
Peak memory 196436 kb
Host smart-e28ca297-508b-41b9-b029-3f079cd8333f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267471947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
267471947
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1780604594
Short name T547
Test name
Test status
Simulation time 126859090 ps
CPU time 0.92 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:16 PM PDT 24
Peak memory 196232 kb
Host smart-d244e2f4-db54-4733-9ac9-a52edcb40148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780604594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1780604594
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3550863943
Short name T661
Test name
Test status
Simulation time 33775698 ps
CPU time 0.82 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 195780 kb
Host smart-33eaf9d3-0da2-4f2f-b230-01180e2a98e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550863943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3550863943
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3926264297
Short name T344
Test name
Test status
Simulation time 167210232 ps
CPU time 2.17 seconds
Started Mar 14 01:23:20 PM PDT 24
Finished Mar 14 01:23:22 PM PDT 24
Peak memory 198288 kb
Host smart-5797a1cc-8e47-4ddf-95ca-0d4ed376b5cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926264297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3926264297
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1919776925
Short name T579
Test name
Test status
Simulation time 65036862 ps
CPU time 1.06 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 195956 kb
Host smart-c0c292e7-7a27-4297-a0fa-a6f8110699ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919776925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1919776925
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3770832573
Short name T181
Test name
Test status
Simulation time 76390178 ps
CPU time 1.45 seconds
Started Mar 14 01:23:17 PM PDT 24
Finished Mar 14 01:23:19 PM PDT 24
Peak memory 196984 kb
Host smart-9e69c0e6-be0c-4812-869f-00d831329e32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770832573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3770832573
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.822719120
Short name T5
Test name
Test status
Simulation time 37586855247 ps
CPU time 201.97 seconds
Started Mar 14 01:23:22 PM PDT 24
Finished Mar 14 01:26:45 PM PDT 24
Peak memory 198460 kb
Host smart-cfa9ac0d-616d-4ff2-a733-23b868dee477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822719120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.822719120
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1879666471
Short name T411
Test name
Test status
Simulation time 161988741030 ps
CPU time 816.98 seconds
Started Mar 14 01:23:13 PM PDT 24
Finished Mar 14 01:36:50 PM PDT 24
Peak memory 198492 kb
Host smart-e112d9ff-d7a1-4163-aa18-81fdd8fc9751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1879666471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1879666471
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.4162604508
Short name T562
Test name
Test status
Simulation time 14716871 ps
CPU time 0.59 seconds
Started Mar 14 01:23:19 PM PDT 24
Finished Mar 14 01:23:20 PM PDT 24
Peak memory 194164 kb
Host smart-f248eb02-0063-4306-ac81-2c4d6ce23a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162604508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.4162604508
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3428642366
Short name T322
Test name
Test status
Simulation time 140328740 ps
CPU time 0.93 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:16 PM PDT 24
Peak memory 195760 kb
Host smart-a6661181-4d10-4cfd-86fe-bf3c7b7293cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428642366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3428642366
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2905312816
Short name T459
Test name
Test status
Simulation time 358647290 ps
CPU time 19.13 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 195868 kb
Host smart-a6730c2d-c6e4-45e3-901b-fc7d6059025b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905312816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2905312816
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.54774323
Short name T525
Test name
Test status
Simulation time 52527019 ps
CPU time 0.76 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 196116 kb
Host smart-eca03fb2-30f9-4f23-b74b-c0ff0a8b5f26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54774323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.54774323
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3636729338
Short name T58
Test name
Test status
Simulation time 513794964 ps
CPU time 1.47 seconds
Started Mar 14 01:23:19 PM PDT 24
Finished Mar 14 01:23:22 PM PDT 24
Peak memory 196144 kb
Host smart-7060b83b-e0d2-4dda-be82-a9e11ee16ea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636729338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3636729338
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3011870031
Short name T270
Test name
Test status
Simulation time 63573020 ps
CPU time 2.65 seconds
Started Mar 14 01:23:19 PM PDT 24
Finished Mar 14 01:23:23 PM PDT 24
Peak memory 198436 kb
Host smart-59303a3c-64e1-4b46-aa8b-cebda813a6d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011870031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3011870031
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2239402346
Short name T123
Test name
Test status
Simulation time 369901749 ps
CPU time 2.92 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:19 PM PDT 24
Peak memory 198384 kb
Host smart-6cbb508f-6a8f-4ad7-a135-3e2a21237bf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239402346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2239402346
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2433886009
Short name T305
Test name
Test status
Simulation time 39544286 ps
CPU time 1.04 seconds
Started Mar 14 01:23:20 PM PDT 24
Finished Mar 14 01:23:21 PM PDT 24
Peak memory 196280 kb
Host smart-bd86db01-85c0-47c2-a8db-38e0b9a72f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433886009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2433886009
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3875948980
Short name T624
Test name
Test status
Simulation time 328768882 ps
CPU time 1.36 seconds
Started Mar 14 01:23:17 PM PDT 24
Finished Mar 14 01:23:19 PM PDT 24
Peak memory 195972 kb
Host smart-cebda3a5-b869-4ebd-983d-6db79cbdc8a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875948980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3875948980
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1148107495
Short name T697
Test name
Test status
Simulation time 5087314562 ps
CPU time 4.24 seconds
Started Mar 14 01:23:21 PM PDT 24
Finished Mar 14 01:23:25 PM PDT 24
Peak memory 198440 kb
Host smart-b8a06bf2-5588-4b16-aac7-2b793a758f3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148107495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1148107495
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.848903350
Short name T623
Test name
Test status
Simulation time 79839851 ps
CPU time 1.47 seconds
Started Mar 14 01:23:19 PM PDT 24
Finished Mar 14 01:23:21 PM PDT 24
Peak memory 197060 kb
Host smart-e27e6036-4a84-41c8-9e55-94457e244206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848903350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.848903350
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1309037608
Short name T672
Test name
Test status
Simulation time 27420915 ps
CPU time 0.84 seconds
Started Mar 14 01:23:19 PM PDT 24
Finished Mar 14 01:23:20 PM PDT 24
Peak memory 195468 kb
Host smart-0fd174d1-944b-49b4-ae5b-dd59da74a045
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309037608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1309037608
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.491450581
Short name T157
Test name
Test status
Simulation time 21156994057 ps
CPU time 67.94 seconds
Started Mar 14 01:23:19 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 198452 kb
Host smart-541fe848-211d-49f4-a76c-043f834d4767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491450581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.491450581
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.602543720
Short name T626
Test name
Test status
Simulation time 93599899 ps
CPU time 0.9 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 197516 kb
Host smart-3a7ed61d-edf9-484b-ac44-2a3cbaf3dd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602543720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.602543720
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2109404614
Short name T130
Test name
Test status
Simulation time 2038171313 ps
CPU time 9.33 seconds
Started Mar 14 01:23:29 PM PDT 24
Finished Mar 14 01:23:38 PM PDT 24
Peak memory 195836 kb
Host smart-245adab6-60c7-4c2f-a572-8d896989d900
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109404614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2109404614
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3563130068
Short name T633
Test name
Test status
Simulation time 56186027 ps
CPU time 0.79 seconds
Started Mar 14 01:23:27 PM PDT 24
Finished Mar 14 01:23:28 PM PDT 24
Peak memory 195168 kb
Host smart-3112289c-51d9-444d-aa20-55ad58f79114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563130068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3563130068
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1895407471
Short name T141
Test name
Test status
Simulation time 28396037 ps
CPU time 0.98 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 197040 kb
Host smart-cdb86410-912f-4c92-82e0-7b8b66082721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895407471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1895407471
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.863564772
Short name T256
Test name
Test status
Simulation time 122856277 ps
CPU time 2.56 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 198464 kb
Host smart-99f9596f-3df4-4c8c-a196-ccb10c5f5e2f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863564772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.863564772
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1197986448
Short name T247
Test name
Test status
Simulation time 179196808 ps
CPU time 2.03 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 196320 kb
Host smart-30989968-5db2-436c-b0d2-a310ef160477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197986448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1197986448
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.470833833
Short name T276
Test name
Test status
Simulation time 23292008 ps
CPU time 0.62 seconds
Started Mar 14 01:23:28 PM PDT 24
Finished Mar 14 01:23:29 PM PDT 24
Peak memory 194340 kb
Host smart-cd66d4b4-b275-46f1-8f86-e514092ab668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470833833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.470833833
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2819751707
Short name T636
Test name
Test status
Simulation time 80539517 ps
CPU time 1 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 196056 kb
Host smart-4dd59b5b-160a-49eb-879f-d7ed0a4ae8fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819751707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2819751707
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_smoke.2401326606
Short name T599
Test name
Test status
Simulation time 73937536 ps
CPU time 1.32 seconds
Started Mar 14 01:23:17 PM PDT 24
Finished Mar 14 01:23:18 PM PDT 24
Peak memory 196988 kb
Host smart-81337c15-c06d-4f97-892a-98f051265fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401326606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2401326606
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1590907599
Short name T32
Test name
Test status
Simulation time 41022870 ps
CPU time 0.96 seconds
Started Mar 14 01:23:27 PM PDT 24
Finished Mar 14 01:23:28 PM PDT 24
Peak memory 196116 kb
Host smart-b80552f1-8c91-49a5-a749-b4c21a28f291
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590907599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1590907599
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3576437950
Short name T315
Test name
Test status
Simulation time 11143324155 ps
CPU time 163.65 seconds
Started Mar 14 01:23:28 PM PDT 24
Finished Mar 14 01:26:12 PM PDT 24
Peak memory 198468 kb
Host smart-a9f0a4b0-a0ad-46e3-b806-17d60f84c2d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576437950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3576437950
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1741658810
Short name T610
Test name
Test status
Simulation time 12006020 ps
CPU time 0.57 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 194252 kb
Host smart-b1ddc847-25eb-4903-95c5-ccbc608416a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741658810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1741658810
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2644184374
Short name T531
Test name
Test status
Simulation time 177073287 ps
CPU time 0.81 seconds
Started Mar 14 01:23:29 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 195528 kb
Host smart-b9ecdab5-eff4-4358-9c4a-7ce28f26bcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644184374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2644184374
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.670661729
Short name T665
Test name
Test status
Simulation time 473331840 ps
CPU time 23.43 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:55 PM PDT 24
Peak memory 195860 kb
Host smart-6bf92581-7bef-4fde-aa09-189091a23fc1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670661729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.670661729
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2591771849
Short name T705
Test name
Test status
Simulation time 348443818 ps
CPU time 1 seconds
Started Mar 14 01:23:27 PM PDT 24
Finished Mar 14 01:23:29 PM PDT 24
Peak memory 198160 kb
Host smart-ef8bc2a4-bc2f-4647-8d54-4d5cfad4c07c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591771849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2591771849
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1065013721
Short name T472
Test name
Test status
Simulation time 81574005 ps
CPU time 1.26 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 197060 kb
Host smart-a7870918-768d-4e3b-8614-f7b3d40d4c49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065013721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1065013721
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3077289537
Short name T182
Test name
Test status
Simulation time 267463407 ps
CPU time 3.01 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:35 PM PDT 24
Peak memory 198372 kb
Host smart-074eb16b-464a-4b9e-aa6b-03aa072d3e16
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077289537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3077289537
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3335749248
Short name T217
Test name
Test status
Simulation time 436935344 ps
CPU time 2.34 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:23:35 PM PDT 24
Peak memory 197512 kb
Host smart-d0beab7e-4a7e-4466-be2d-4a0668a6ddcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335749248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3335749248
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3833364095
Short name T249
Test name
Test status
Simulation time 43174400 ps
CPU time 1.02 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 196288 kb
Host smart-4383ef86-b538-4a51-94f3-217ae14e7c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833364095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3833364095
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3365364037
Short name T428
Test name
Test status
Simulation time 65867190 ps
CPU time 1.31 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 197264 kb
Host smart-54d27df5-108d-4f0f-9bd1-da9c7d2505ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365364037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3365364037
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1796342606
Short name T381
Test name
Test status
Simulation time 86124580 ps
CPU time 4.22 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 198280 kb
Host smart-5231ae0a-77c5-4bc3-bf26-3c99fb98e56b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796342606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1796342606
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2382264685
Short name T166
Test name
Test status
Simulation time 138981365 ps
CPU time 1.33 seconds
Started Mar 14 01:23:28 PM PDT 24
Finished Mar 14 01:23:30 PM PDT 24
Peak memory 196948 kb
Host smart-a2676346-9d96-4503-b125-eacb9ac33f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382264685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2382264685
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1409096080
Short name T439
Test name
Test status
Simulation time 105666533 ps
CPU time 1.23 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 196172 kb
Host smart-81a37798-cd73-4f43-9c7b-0e3e70aa450c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409096080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1409096080
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1603719911
Short name T8
Test name
Test status
Simulation time 5045595136 ps
CPU time 63.28 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:24:34 PM PDT 24
Peak memory 198408 kb
Host smart-585e6d39-b501-4825-98d7-4d4a499ac1fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603719911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1603719911
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1375289627
Short name T667
Test name
Test status
Simulation time 156641962345 ps
CPU time 711.45 seconds
Started Mar 14 01:23:29 PM PDT 24
Finished Mar 14 01:35:20 PM PDT 24
Peak memory 198508 kb
Host smart-f59189a5-c316-4e74-a713-12eb712bd46c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1375289627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1375289627
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2704379353
Short name T153
Test name
Test status
Simulation time 66135951 ps
CPU time 0.56 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 194764 kb
Host smart-f1e27d17-4e7a-477b-a726-b2d8140cf169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704379353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2704379353
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3414686628
Short name T612
Test name
Test status
Simulation time 75959212 ps
CPU time 0.98 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 195700 kb
Host smart-92f65d2f-30af-470d-9d04-1c7125a637db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414686628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3414686628
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2790171543
Short name T474
Test name
Test status
Simulation time 145888547 ps
CPU time 7.6 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:38 PM PDT 24
Peak memory 198316 kb
Host smart-a3312a99-2fb0-4e67-853a-bda9adfa01dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790171543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2790171543
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3714002552
Short name T491
Test name
Test status
Simulation time 162728977 ps
CPU time 1.01 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 198104 kb
Host smart-25cdd078-e20a-472c-8085-907b5423d9dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714002552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3714002552
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1981697789
Short name T162
Test name
Test status
Simulation time 299948601 ps
CPU time 1.19 seconds
Started Mar 14 01:23:29 PM PDT 24
Finished Mar 14 01:23:30 PM PDT 24
Peak memory 196392 kb
Host smart-f27bb50e-2a41-4e72-a8fb-0297e5e4209a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981697789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1981697789
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2869710172
Short name T176
Test name
Test status
Simulation time 150368397 ps
CPU time 1.78 seconds
Started Mar 14 01:23:29 PM PDT 24
Finished Mar 14 01:23:30 PM PDT 24
Peak memory 197128 kb
Host smart-c530ec06-6fcd-4841-bc4f-0e168807c15c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869710172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2869710172
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3771156152
Short name T361
Test name
Test status
Simulation time 224263477 ps
CPU time 1.53 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 196132 kb
Host smart-119703ef-ca53-47bd-a7ab-a03cd849a571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771156152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3771156152
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.837009254
Short name T286
Test name
Test status
Simulation time 18494485 ps
CPU time 0.73 seconds
Started Mar 14 01:23:35 PM PDT 24
Finished Mar 14 01:23:36 PM PDT 24
Peak memory 196360 kb
Host smart-f97a4190-c751-4523-bad7-6b390cf7ab75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837009254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.837009254
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1635204905
Short name T210
Test name
Test status
Simulation time 33693084 ps
CPU time 1.18 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 198308 kb
Host smart-ab27b171-089b-40f7-a822-c367328843e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635204905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1635204905
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1215243548
Short name T4
Test name
Test status
Simulation time 1922718974 ps
CPU time 6.44 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:36 PM PDT 24
Peak memory 198256 kb
Host smart-fce8820e-3646-4390-bd4c-46c44fb61453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215243548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1215243548
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1349904719
Short name T601
Test name
Test status
Simulation time 114085921 ps
CPU time 1.36 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 197252 kb
Host smart-26d5747e-2b2b-475a-ba27-89a03abb1216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349904719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1349904719
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1505927900
Short name T132
Test name
Test status
Simulation time 52953004 ps
CPU time 1.14 seconds
Started Mar 14 01:23:29 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 196176 kb
Host smart-fc357bdb-4b38-42da-9efb-5952312cf7d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505927900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1505927900
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.265955748
Short name T10
Test name
Test status
Simulation time 64123836957 ps
CPU time 114.78 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:25:26 PM PDT 24
Peak memory 198372 kb
Host smart-78a4b97d-d470-4ae9-8979-c6aa9917210a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265955748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.265955748
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2547647197
Short name T151
Test name
Test status
Simulation time 19060682 ps
CPU time 0.55 seconds
Started Mar 14 01:23:28 PM PDT 24
Finished Mar 14 01:23:28 PM PDT 24
Peak memory 194160 kb
Host smart-615c1d39-eaea-4c54-b53e-6e0075275dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547647197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2547647197
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.981646249
Short name T475
Test name
Test status
Simulation time 105901272 ps
CPU time 0.76 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 196264 kb
Host smart-6ce7b3ff-e258-407c-b9ff-ab54d07ba0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981646249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.981646249
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2065733154
Short name T550
Test name
Test status
Simulation time 4924998992 ps
CPU time 9.11 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:41 PM PDT 24
Peak memory 197288 kb
Host smart-226ec037-0e3c-4008-8b6d-fd6328dd3a20
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065733154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2065733154
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2291063491
Short name T218
Test name
Test status
Simulation time 91189182 ps
CPU time 1.03 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 196712 kb
Host smart-a2b98b16-c367-4fc8-a05a-30264179f492
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291063491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2291063491
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2341735194
Short name T279
Test name
Test status
Simulation time 70938509 ps
CPU time 1.21 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 196532 kb
Host smart-b7fc34f4-2d3c-4754-a614-9b36e8117e3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341735194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2341735194
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1217084181
Short name T277
Test name
Test status
Simulation time 173415667 ps
CPU time 1.74 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:23:35 PM PDT 24
Peak memory 197296 kb
Host smart-955e589e-13d7-4f6b-a9ff-615fc131c14c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217084181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1217084181
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1554104587
Short name T336
Test name
Test status
Simulation time 163595286 ps
CPU time 1.28 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 196412 kb
Host smart-0663e8b6-1056-482b-af98-21c93ea2609a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554104587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1554104587
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.4002943207
Short name T178
Test name
Test status
Simulation time 50652800 ps
CPU time 0.81 seconds
Started Mar 14 01:23:28 PM PDT 24
Finished Mar 14 01:23:29 PM PDT 24
Peak memory 195756 kb
Host smart-59ec7ed5-d470-4a56-afab-4313f01fbe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002943207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.4002943207
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1031148665
Short name T164
Test name
Test status
Simulation time 90976561 ps
CPU time 0.74 seconds
Started Mar 14 01:23:29 PM PDT 24
Finished Mar 14 01:23:30 PM PDT 24
Peak memory 195608 kb
Host smart-2e6429c0-8667-4c58-ae63-1bc8fcc046be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031148665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1031148665
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.4099641892
Short name T482
Test name
Test status
Simulation time 5001398308 ps
CPU time 4.46 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:35 PM PDT 24
Peak memory 198396 kb
Host smart-712e18a6-9c58-416a-9bb9-c88dfb1ccad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099641892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.4099641892
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1444497408
Short name T140
Test name
Test status
Simulation time 304353756 ps
CPU time 1.25 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 196588 kb
Host smart-e1a6ea1a-f695-4b25-8168-0cbc7006b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444497408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1444497408
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1286496857
Short name T707
Test name
Test status
Simulation time 75255639 ps
CPU time 1.36 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 197432 kb
Host smart-17b39f93-d5e3-4c05-b76e-11e272aef523
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286496857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1286496857
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.830769708
Short name T529
Test name
Test status
Simulation time 6005838946 ps
CPU time 158.51 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:26:10 PM PDT 24
Peak memory 198504 kb
Host smart-d692a160-4613-4748-a7de-b864f89c7f26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830769708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.830769708
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.941009755
Short name T704
Test name
Test status
Simulation time 38526921496 ps
CPU time 466.04 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:31:18 PM PDT 24
Peak memory 198548 kb
Host smart-7d4fda00-4227-42f0-b1a0-2f8ae53bc8c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=941009755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.941009755
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1665491028
Short name T355
Test name
Test status
Simulation time 37465395 ps
CPU time 0.57 seconds
Started Mar 14 01:23:36 PM PDT 24
Finished Mar 14 01:23:36 PM PDT 24
Peak memory 194336 kb
Host smart-bb826a3a-1b98-48df-86be-c261188c6eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665491028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1665491028
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3642608127
Short name T233
Test name
Test status
Simulation time 68311810 ps
CPU time 0.81 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 195600 kb
Host smart-05c9e72e-f40c-4849-9de4-ccca891478d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642608127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3642608127
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4167526969
Short name T175
Test name
Test status
Simulation time 285429677 ps
CPU time 8.45 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:41 PM PDT 24
Peak memory 195812 kb
Host smart-0c9eb7de-16ba-4075-883d-4cf7beb760bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167526969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.4167526969
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2422631309
Short name T543
Test name
Test status
Simulation time 71827408 ps
CPU time 0.82 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 196192 kb
Host smart-80ebce79-f87e-4135-97a6-4cf485a4ea4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422631309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2422631309
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3844779514
Short name T607
Test name
Test status
Simulation time 21470739 ps
CPU time 0.7 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 195136 kb
Host smart-40e8cbc0-a9c0-4250-abe1-e375f76ea9fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844779514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3844779514
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3717048482
Short name T671
Test name
Test status
Simulation time 356462763 ps
CPU time 2.67 seconds
Started Mar 14 01:23:28 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 198472 kb
Host smart-83139dd4-9772-4319-9bee-41eafe5dee11
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717048482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3717048482
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2242171403
Short name T302
Test name
Test status
Simulation time 68082993 ps
CPU time 1.61 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 196844 kb
Host smart-eb646719-5a30-4605-861c-d1f8d77e783c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242171403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2242171403
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1825763822
Short name T314
Test name
Test status
Simulation time 160068163 ps
CPU time 1.29 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 198448 kb
Host smart-017e5020-c42a-44c6-b1aa-6b3e75a7f42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825763822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1825763822
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2752636027
Short name T423
Test name
Test status
Simulation time 53341684 ps
CPU time 0.8 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 195764 kb
Host smart-f8d80d6d-a68b-46a5-9ee2-72d568f3d8fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752636027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2752636027
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.4236116643
Short name T391
Test name
Test status
Simulation time 2377320198 ps
CPU time 6.44 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:36 PM PDT 24
Peak memory 198396 kb
Host smart-afb87daf-04e8-42b6-82cd-9fbf5aeba745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236116643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.4236116643
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1518974336
Short name T208
Test name
Test status
Simulation time 289530498 ps
CPU time 1.33 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 195820 kb
Host smart-5678fc35-0eb1-460f-95bc-cd4b34ad72a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518974336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1518974336
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.74179703
Short name T121
Test name
Test status
Simulation time 57748062 ps
CPU time 1.21 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 196728 kb
Host smart-ab066d86-e80b-4396-ba73-0f577da6fccd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74179703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.74179703
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1356152484
Short name T385
Test name
Test status
Simulation time 8581671860 ps
CPU time 96.29 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:25:09 PM PDT 24
Peak memory 198368 kb
Host smart-bb564738-9924-4ae6-9dae-ba5df43252e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356152484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1356152484
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3450210369
Short name T515
Test name
Test status
Simulation time 60803340 ps
CPU time 0.56 seconds
Started Mar 14 01:23:36 PM PDT 24
Finished Mar 14 01:23:36 PM PDT 24
Peak memory 194852 kb
Host smart-b027f050-142f-4d44-a836-9f652eddaf87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450210369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3450210369
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.261393307
Short name T370
Test name
Test status
Simulation time 52791884 ps
CPU time 0.74 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 196112 kb
Host smart-a80f61e5-869d-4165-9eb4-cd5560fd87e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261393307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.261393307
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2686416369
Short name T476
Test name
Test status
Simulation time 292873748 ps
CPU time 16.06 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 197356 kb
Host smart-b62e5be6-743e-467e-a271-25d4018e1a02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686416369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2686416369
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2459419849
Short name T274
Test name
Test status
Simulation time 55720781 ps
CPU time 0.85 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 196164 kb
Host smart-2ab1335b-d7a7-4fac-bbf3-9f94c20ef432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459419849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2459419849
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1286042701
Short name T683
Test name
Test status
Simulation time 121257512 ps
CPU time 1.04 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 196328 kb
Host smart-084e50c7-d0d4-4a7d-82cd-9309ea1bb0ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286042701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1286042701
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3257785713
Short name T463
Test name
Test status
Simulation time 636973572 ps
CPU time 3.82 seconds
Started Mar 14 01:23:38 PM PDT 24
Finished Mar 14 01:23:42 PM PDT 24
Peak memory 198460 kb
Host smart-ea6f624d-2c25-4fa4-98a5-4005e7f510bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257785713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3257785713
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.676750059
Short name T325
Test name
Test status
Simulation time 27141379 ps
CPU time 0.97 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 195940 kb
Host smart-d1471f81-f167-4a55-a7ad-30ff6750ab0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676750059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
676750059
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3076545777
Short name T150
Test name
Test status
Simulation time 109684986 ps
CPU time 0.84 seconds
Started Mar 14 01:23:36 PM PDT 24
Finished Mar 14 01:23:37 PM PDT 24
Peak memory 196704 kb
Host smart-fd44022b-c3fb-4cbc-8568-3224cb9eb510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076545777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3076545777
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.936824162
Short name T458
Test name
Test status
Simulation time 15615004 ps
CPU time 0.66 seconds
Started Mar 14 01:23:36 PM PDT 24
Finished Mar 14 01:23:37 PM PDT 24
Peak memory 195232 kb
Host smart-73ecda3b-a1ef-4321-aca6-eea7717caa3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936824162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.936824162
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1067671145
Short name T318
Test name
Test status
Simulation time 212203626 ps
CPU time 4.91 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:35 PM PDT 24
Peak memory 198296 kb
Host smart-de475a66-2f94-40c0-bedb-3d89be45077c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067671145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1067671145
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3127588660
Short name T137
Test name
Test status
Simulation time 181768584 ps
CPU time 1.04 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 195864 kb
Host smart-3b3d1e65-ee6e-483a-b174-b6ef35cd5630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127588660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3127588660
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2804602579
Short name T479
Test name
Test status
Simulation time 133044867 ps
CPU time 1.21 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 197188 kb
Host smart-4e62f71f-ec43-4ce9-a85b-6abaaa2b6d24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804602579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2804602579
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3402188521
Short name T524
Test name
Test status
Simulation time 31100404995 ps
CPU time 108.38 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:25:20 PM PDT 24
Peak memory 198368 kb
Host smart-c34046f8-d620-454f-9403-c7f4d2b2c85f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402188521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3402188521
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3761450664
Short name T36
Test name
Test status
Simulation time 46340142040 ps
CPU time 1108.34 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:42:01 PM PDT 24
Peak memory 198544 kb
Host smart-5831385a-caaa-43bc-9ecf-d21d1f660b72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3761450664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3761450664
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1252855304
Short name T398
Test name
Test status
Simulation time 44818560 ps
CPU time 0.58 seconds
Started Mar 14 01:23:34 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 194960 kb
Host smart-c15a8ffe-c420-40c7-a888-f6414eec10dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252855304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1252855304
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2997376056
Short name T568
Test name
Test status
Simulation time 112759261 ps
CPU time 0.89 seconds
Started Mar 14 01:23:34 PM PDT 24
Finished Mar 14 01:23:35 PM PDT 24
Peak memory 196160 kb
Host smart-0e851917-c68d-49bf-b8a1-603a00875ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997376056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2997376056
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.628000846
Short name T511
Test name
Test status
Simulation time 1861252392 ps
CPU time 14.78 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 196540 kb
Host smart-c9c6531b-cef9-489b-a29a-e61dd1e1afc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628000846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.628000846
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2565164393
Short name T651
Test name
Test status
Simulation time 82993223 ps
CPU time 0.98 seconds
Started Mar 14 01:23:39 PM PDT 24
Finished Mar 14 01:23:40 PM PDT 24
Peak memory 197296 kb
Host smart-3f5b7485-12e2-4185-9300-836334f89599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565164393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2565164393
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2127780208
Short name T470
Test name
Test status
Simulation time 414033334 ps
CPU time 1 seconds
Started Mar 14 01:23:35 PM PDT 24
Finished Mar 14 01:23:36 PM PDT 24
Peak memory 196092 kb
Host smart-12b3c668-4773-4420-9e5a-f7b0d80ff8ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127780208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2127780208
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4032592000
Short name T502
Test name
Test status
Simulation time 92025821 ps
CPU time 1.34 seconds
Started Mar 14 01:23:32 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 196944 kb
Host smart-3c9299b8-2ceb-4ecf-bbad-16c387332623
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032592000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4032592000
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1092953237
Short name T297
Test name
Test status
Simulation time 53655176 ps
CPU time 0.74 seconds
Started Mar 14 01:23:30 PM PDT 24
Finished Mar 14 01:23:31 PM PDT 24
Peak memory 194616 kb
Host smart-18b2374f-1dbd-4ff5-87c9-1a2f9510e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092953237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1092953237
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2354922829
Short name T430
Test name
Test status
Simulation time 39340900 ps
CPU time 1.03 seconds
Started Mar 14 01:23:31 PM PDT 24
Finished Mar 14 01:23:32 PM PDT 24
Peak memory 196136 kb
Host smart-9d97a8b5-57c4-4442-9f12-6604915835f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354922829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2354922829
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2837781826
Short name T713
Test name
Test status
Simulation time 118450933 ps
CPU time 1.15 seconds
Started Mar 14 01:23:37 PM PDT 24
Finished Mar 14 01:23:38 PM PDT 24
Peak memory 198372 kb
Host smart-48f4dcbe-2766-4f3a-b44d-762e91316f52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837781826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2837781826
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.756483678
Short name T190
Test name
Test status
Simulation time 86227165 ps
CPU time 0.81 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 196196 kb
Host smart-02d87ca7-1706-4cc9-896f-3356c57e71a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756483678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.756483678
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2190697692
Short name T674
Test name
Test status
Simulation time 378888746 ps
CPU time 1.46 seconds
Started Mar 14 01:23:36 PM PDT 24
Finished Mar 14 01:23:38 PM PDT 24
Peak memory 197228 kb
Host smart-9800881b-0fa1-47da-a82a-34a11f29bfad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190697692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2190697692
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3095172898
Short name T124
Test name
Test status
Simulation time 12226062690 ps
CPU time 73.18 seconds
Started Mar 14 01:23:37 PM PDT 24
Finished Mar 14 01:24:50 PM PDT 24
Peak memory 198364 kb
Host smart-d4a1993d-5f18-432f-89f0-c4260ee0d49d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095172898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3095172898
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1533093073
Short name T383
Test name
Test status
Simulation time 39935797 ps
CPU time 0.57 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 194328 kb
Host smart-d71407f8-0c42-4bdb-9651-d2be202770a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533093073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1533093073
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1275573090
Short name T301
Test name
Test status
Simulation time 16767220 ps
CPU time 0.64 seconds
Started Mar 14 01:23:38 PM PDT 24
Finished Mar 14 01:23:39 PM PDT 24
Peak memory 194372 kb
Host smart-3ff86306-049a-4cb9-bed5-002e8021feeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275573090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1275573090
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1727578439
Short name T662
Test name
Test status
Simulation time 3740750597 ps
CPU time 20.73 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:24:06 PM PDT 24
Peak memory 197692 kb
Host smart-67445e1a-7ff0-4696-97ee-797fc271218e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727578439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1727578439
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3795111742
Short name T244
Test name
Test status
Simulation time 144250192 ps
CPU time 0.72 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:44 PM PDT 24
Peak memory 194956 kb
Host smart-99247ee4-49bd-422f-96f6-58eefc577675
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795111742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3795111742
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2818092166
Short name T486
Test name
Test status
Simulation time 83403566 ps
CPU time 1.55 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 197020 kb
Host smart-e10301e7-1db8-43b9-bfaf-d2ca92ed6088
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818092166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2818092166
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2558211435
Short name T185
Test name
Test status
Simulation time 50354176 ps
CPU time 1.41 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:45 PM PDT 24
Peak memory 197096 kb
Host smart-b352fcc3-e5d5-42ed-82e6-3e3f60f0901b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558211435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2558211435
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1593902780
Short name T221
Test name
Test status
Simulation time 119910786 ps
CPU time 1.73 seconds
Started Mar 14 01:23:42 PM PDT 24
Finished Mar 14 01:23:44 PM PDT 24
Peak memory 196208 kb
Host smart-8f5e5aec-9c89-4bd9-841e-b49c6bcd53f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593902780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1593902780
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1184572332
Short name T648
Test name
Test status
Simulation time 44329443 ps
CPU time 0.72 seconds
Started Mar 14 01:23:33 PM PDT 24
Finished Mar 14 01:23:34 PM PDT 24
Peak memory 194620 kb
Host smart-f6718b97-e7cf-43f3-ad12-53e95eba1247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184572332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1184572332
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2452370292
Short name T591
Test name
Test status
Simulation time 126040302 ps
CPU time 0.94 seconds
Started Mar 14 01:23:38 PM PDT 24
Finished Mar 14 01:23:39 PM PDT 24
Peak memory 196396 kb
Host smart-597273ac-ba4b-49b3-b22f-43c33c075220
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452370292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2452370292
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.4198505922
Short name T536
Test name
Test status
Simulation time 186668639 ps
CPU time 2.37 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 198396 kb
Host smart-fafcb642-d689-41f0-ba16-b2334b36e840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198505922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.4198505922
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.763733870
Short name T191
Test name
Test status
Simulation time 290184805 ps
CPU time 1.43 seconds
Started Mar 14 01:23:34 PM PDT 24
Finished Mar 14 01:23:35 PM PDT 24
Peak memory 197476 kb
Host smart-a9670b63-c715-4346-80d1-64f3b527d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763733870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.763733870
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.636852961
Short name T400
Test name
Test status
Simulation time 112294032 ps
CPU time 1.01 seconds
Started Mar 14 01:23:34 PM PDT 24
Finished Mar 14 01:23:35 PM PDT 24
Peak memory 195988 kb
Host smart-d94b0a19-5f27-474a-8469-68bd836b5f0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636852961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.636852961
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1814951653
Short name T9
Test name
Test status
Simulation time 7427666843 ps
CPU time 40.23 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:24:26 PM PDT 24
Peak memory 198308 kb
Host smart-6766afef-40b4-4020-b4a0-77ed51ac6a1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814951653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1814951653
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3432802506
Short name T510
Test name
Test status
Simulation time 15076522 ps
CPU time 0.58 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:22:43 PM PDT 24
Peak memory 194992 kb
Host smart-bed9e00b-5971-4695-807a-393d4ee20f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432802506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3432802506
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2955273683
Short name T405
Test name
Test status
Simulation time 43865270 ps
CPU time 0.86 seconds
Started Mar 14 01:22:39 PM PDT 24
Finished Mar 14 01:22:40 PM PDT 24
Peak memory 195704 kb
Host smart-c24dd4cd-6315-4591-b7e0-856913e92cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955273683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2955273683
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3335185966
Short name T412
Test name
Test status
Simulation time 464898209 ps
CPU time 24.99 seconds
Started Mar 14 01:22:40 PM PDT 24
Finished Mar 14 01:23:06 PM PDT 24
Peak memory 197088 kb
Host smart-2a3153c6-c55a-4d9f-a8eb-8fa2a1ed4b90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335185966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3335185966
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1074994537
Short name T30
Test name
Test status
Simulation time 59782826 ps
CPU time 0.82 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 196244 kb
Host smart-f6333a38-5ad0-48e3-a364-18306836ccc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074994537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1074994537
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3459132138
Short name T117
Test name
Test status
Simulation time 271938236 ps
CPU time 1.2 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 196508 kb
Host smart-28348bbd-7f05-44f4-8352-5adf14262ae1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459132138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3459132138
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2673746241
Short name T356
Test name
Test status
Simulation time 90301021 ps
CPU time 3.74 seconds
Started Mar 14 01:22:41 PM PDT 24
Finished Mar 14 01:22:45 PM PDT 24
Peak memory 198488 kb
Host smart-84c6ff8c-deda-495f-9f13-b5fb53b0734f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673746241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2673746241
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2296722350
Short name T23
Test name
Test status
Simulation time 129580380 ps
CPU time 2.51 seconds
Started Mar 14 01:22:36 PM PDT 24
Finished Mar 14 01:22:39 PM PDT 24
Peak memory 197384 kb
Host smart-8b5a27ee-b4f8-45cb-aa3e-addd7b27cd14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296722350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2296722350
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3034724759
Short name T215
Test name
Test status
Simulation time 96398140 ps
CPU time 1.16 seconds
Started Mar 14 01:22:39 PM PDT 24
Finished Mar 14 01:22:41 PM PDT 24
Peak memory 196436 kb
Host smart-8e7b1300-673c-4f46-910a-5a00f304d883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034724759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3034724759
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1266282000
Short name T310
Test name
Test status
Simulation time 69205064 ps
CPU time 1.35 seconds
Started Mar 14 01:22:41 PM PDT 24
Finished Mar 14 01:22:43 PM PDT 24
Peak memory 196144 kb
Host smart-461947db-48ac-4e52-a7c9-e903fb76839f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266282000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1266282000
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1972328776
Short name T436
Test name
Test status
Simulation time 68145257 ps
CPU time 3.15 seconds
Started Mar 14 01:22:41 PM PDT 24
Finished Mar 14 01:22:45 PM PDT 24
Peak memory 198204 kb
Host smart-abf9e77c-7d6b-4d1f-8056-54dfb9c33580
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972328776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1972328776
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3760216110
Short name T57
Test name
Test status
Simulation time 59743059 ps
CPU time 0.9 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:22:45 PM PDT 24
Peak memory 213668 kb
Host smart-cb01db12-5dc2-4bb5-bea3-9d8dafd0c41d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760216110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3760216110
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.159573133
Short name T484
Test name
Test status
Simulation time 53648511 ps
CPU time 1.06 seconds
Started Mar 14 01:22:39 PM PDT 24
Finished Mar 14 01:22:41 PM PDT 24
Peak memory 196756 kb
Host smart-227ee87b-ea6b-40e1-91df-905379bfae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159573133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.159573133
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2293432162
Short name T262
Test name
Test status
Simulation time 132638433 ps
CPU time 0.85 seconds
Started Mar 14 01:22:39 PM PDT 24
Finished Mar 14 01:22:40 PM PDT 24
Peak memory 196352 kb
Host smart-62003320-0e4f-4959-8ece-32dcc1b23cef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293432162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2293432162
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2956369708
Short name T186
Test name
Test status
Simulation time 30216326865 ps
CPU time 205.17 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:26:08 PM PDT 24
Peak memory 198424 kb
Host smart-29c684c2-585e-4adf-af93-3463badc8fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956369708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2956369708
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2822953111
Short name T485
Test name
Test status
Simulation time 35118430 ps
CPU time 0.55 seconds
Started Mar 14 01:23:40 PM PDT 24
Finished Mar 14 01:23:41 PM PDT 24
Peak memory 194860 kb
Host smart-7cbc61b6-9bb2-4bb2-983e-b55d415a4c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822953111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2822953111
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.615897875
Short name T652
Test name
Test status
Simulation time 20935727 ps
CPU time 0.73 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:45 PM PDT 24
Peak memory 194344 kb
Host smart-f0e1dc1c-fb1a-4ccb-93ae-0355ed3fdce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615897875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.615897875
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.830670398
Short name T299
Test name
Test status
Simulation time 1761537750 ps
CPU time 25.21 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:24:11 PM PDT 24
Peak memory 197052 kb
Host smart-c7ef3d5f-dcdc-4136-a4be-241d312a164f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830670398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.830670398
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.321280012
Short name T82
Test name
Test status
Simulation time 114887539 ps
CPU time 0.95 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:45 PM PDT 24
Peak memory 197044 kb
Host smart-634bfed8-7d10-4deb-aa76-2715c2ed3f85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321280012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.321280012
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4081388750
Short name T631
Test name
Test status
Simulation time 82670381 ps
CPU time 0.71 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 195200 kb
Host smart-f5d95b17-eb72-44c7-8b1e-fedd5b28016a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081388750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4081388750
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3933831958
Short name T498
Test name
Test status
Simulation time 247461760 ps
CPU time 2.64 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 198500 kb
Host smart-79479ae8-c56c-4621-8a79-d439e6663192
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933831958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3933831958
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1136457723
Short name T642
Test name
Test status
Simulation time 420944464 ps
CPU time 2.6 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 197288 kb
Host smart-a44c9d83-81a6-4027-901b-b11625f11de6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136457723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1136457723
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3922849278
Short name T554
Test name
Test status
Simulation time 66481480 ps
CPU time 1.2 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 196448 kb
Host smart-0d75ddfd-5809-4af3-9b35-c2ac18fbf364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922849278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3922849278
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3818249764
Short name T544
Test name
Test status
Simulation time 150682044 ps
CPU time 0.98 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 196976 kb
Host smart-a0809044-276e-42d6-8376-eab3e40fb042
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818249764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3818249764
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1046566679
Short name T483
Test name
Test status
Simulation time 262690573 ps
CPU time 4 seconds
Started Mar 14 01:23:42 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 198096 kb
Host smart-f04b5d9e-7dfe-44cc-9fda-8395a4456d91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046566679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1046566679
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3559752781
Short name T444
Test name
Test status
Simulation time 41883274 ps
CPU time 1.23 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:44 PM PDT 24
Peak memory 197032 kb
Host smart-b47c7bfa-27f1-43b6-b621-3736296297b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559752781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3559752781
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1645537097
Short name T216
Test name
Test status
Simulation time 132356956 ps
CPU time 1.31 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 197184 kb
Host smart-b8d29820-bd56-436f-84f5-c7ea89b79886
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645537097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1645537097
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3427366648
Short name T676
Test name
Test status
Simulation time 24119069527 ps
CPU time 89.45 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:25:14 PM PDT 24
Peak memory 198356 kb
Host smart-8f93db23-b2dd-44b0-9f0e-94f9440fdcb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427366648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3427366648
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.333681772
Short name T619
Test name
Test status
Simulation time 11143828 ps
CPU time 0.57 seconds
Started Mar 14 01:23:50 PM PDT 24
Finished Mar 14 01:23:51 PM PDT 24
Peak memory 194788 kb
Host smart-3a9aa569-1512-4b4c-863a-8d89fe96f5df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333681772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.333681772
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2706843001
Short name T542
Test name
Test status
Simulation time 199802931 ps
CPU time 1.02 seconds
Started Mar 14 01:23:50 PM PDT 24
Finished Mar 14 01:23:51 PM PDT 24
Peak memory 195964 kb
Host smart-972db1d8-35b7-4fb4-9301-8b75802916ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706843001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2706843001
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2952487402
Short name T319
Test name
Test status
Simulation time 190917890 ps
CPU time 9.86 seconds
Started Mar 14 01:23:47 PM PDT 24
Finished Mar 14 01:23:57 PM PDT 24
Peak memory 198328 kb
Host smart-261689cb-1423-4feb-b204-cd890639d9af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952487402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2952487402
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1886116129
Short name T559
Test name
Test status
Simulation time 93920558 ps
CPU time 0.88 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:45 PM PDT 24
Peak memory 196840 kb
Host smart-7f16071c-2055-4fa7-a505-adddab0c4d69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886116129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1886116129
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.892047579
Short name T453
Test name
Test status
Simulation time 128658274 ps
CPU time 1.21 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 196080 kb
Host smart-d0917403-fed0-430d-98ea-a5026c8db30f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892047579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.892047579
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1510520002
Short name T239
Test name
Test status
Simulation time 44914712 ps
CPU time 1.84 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 198376 kb
Host smart-5602b15d-7a86-4227-9307-492b179492c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510520002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1510520002
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3837018652
Short name T527
Test name
Test status
Simulation time 286137851 ps
CPU time 3.28 seconds
Started Mar 14 01:23:40 PM PDT 24
Finished Mar 14 01:23:43 PM PDT 24
Peak memory 196852 kb
Host smart-6c8e75c0-dc85-4dcf-93f5-a11ce9e4b637
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837018652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3837018652
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2578299524
Short name T457
Test name
Test status
Simulation time 112956690 ps
CPU time 0.97 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:45 PM PDT 24
Peak memory 197540 kb
Host smart-6a272863-1ff3-4e87-9091-ba18d3263dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578299524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2578299524
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.4079226813
Short name T512
Test name
Test status
Simulation time 96126907 ps
CPU time 0.8 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 195804 kb
Host smart-f41b2125-5bc5-459f-9401-fbcf94a60fb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079226813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.4079226813
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2480165545
Short name T580
Test name
Test status
Simulation time 866843607 ps
CPU time 5.05 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 198268 kb
Host smart-20953b06-5ae6-4f25-8f7a-1c630dcbdcaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480165545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2480165545
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1417962787
Short name T220
Test name
Test status
Simulation time 378379957 ps
CPU time 1.44 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 197152 kb
Host smart-7b0e8b50-8c5f-43fa-ad19-c5bd6782a2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417962787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1417962787
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1669538342
Short name T206
Test name
Test status
Simulation time 170191332 ps
CPU time 1.37 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 197160 kb
Host smart-d19ec38f-255f-4c55-9ffe-88f3663f8dc9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669538342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1669538342
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1261090503
Short name T261
Test name
Test status
Simulation time 38130403418 ps
CPU time 163.08 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:26:27 PM PDT 24
Peak memory 198432 kb
Host smart-3fd62d85-e9e7-42c9-b894-660040bef5ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261090503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1261090503
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2062084614
Short name T73
Test name
Test status
Simulation time 96254619015 ps
CPU time 1158.98 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:43:02 PM PDT 24
Peak memory 198540 kb
Host smart-cd1a3068-4263-42e6-882e-980f78137f87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2062084614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2062084614
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3269934297
Short name T446
Test name
Test status
Simulation time 15236784 ps
CPU time 0.59 seconds
Started Mar 14 01:23:49 PM PDT 24
Finished Mar 14 01:23:50 PM PDT 24
Peak memory 194132 kb
Host smart-74a8c750-1afd-4d6d-87d4-7fd10c1a85b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269934297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3269934297
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.90567531
Short name T534
Test name
Test status
Simulation time 29682012 ps
CPU time 0.81 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 195580 kb
Host smart-d2f1ed8c-2497-4ff3-97da-0d8c260376a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90567531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.90567531
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2232034081
Short name T267
Test name
Test status
Simulation time 1882109322 ps
CPU time 20.9 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:24:05 PM PDT 24
Peak memory 195872 kb
Host smart-90c12a8e-6bd4-4094-b374-2d3501d2a752
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232034081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2232034081
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.378338827
Short name T59
Test name
Test status
Simulation time 89090535 ps
CPU time 0.88 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 196220 kb
Host smart-e006104c-6830-4672-8754-606de21e880e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378338827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.378338827
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1228105216
Short name T514
Test name
Test status
Simulation time 46674683 ps
CPU time 0.97 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 197620 kb
Host smart-97956e15-695a-4a25-b119-cca11c99cca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228105216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1228105216
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3067531019
Short name T196
Test name
Test status
Simulation time 97692072 ps
CPU time 3.71 seconds
Started Mar 14 01:23:51 PM PDT 24
Finished Mar 14 01:23:55 PM PDT 24
Peak memory 196656 kb
Host smart-0c42a4d1-c751-49d6-80c5-0064e38d16bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067531019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3067531019
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.4259438539
Short name T530
Test name
Test status
Simulation time 125273854 ps
CPU time 1.95 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 196912 kb
Host smart-bc01fdba-8d19-46d4-8740-5db21105d1a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259438539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.4259438539
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3951059323
Short name T306
Test name
Test status
Simulation time 286051772 ps
CPU time 1.2 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 197428 kb
Host smart-ef991890-4f14-42b7-a229-bed74408f86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951059323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3951059323
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3418676335
Short name T501
Test name
Test status
Simulation time 21661262 ps
CPU time 0.74 seconds
Started Mar 14 01:23:42 PM PDT 24
Finished Mar 14 01:23:42 PM PDT 24
Peak memory 194672 kb
Host smart-54754092-11f0-4c98-937a-3d33fcb9bd34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418676335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3418676335
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1533362873
Short name T338
Test name
Test status
Simulation time 732058649 ps
CPU time 2.96 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 198360 kb
Host smart-df747d2d-c8e0-43a2-89b4-532f522d4a46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533362873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1533362873
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3501522472
Short name T513
Test name
Test status
Simulation time 110963390 ps
CPU time 0.73 seconds
Started Mar 14 01:23:40 PM PDT 24
Finished Mar 14 01:23:41 PM PDT 24
Peak memory 194452 kb
Host smart-6a1a7202-0470-46ae-92d0-c6b824b7283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501522472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3501522472
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2971502775
Short name T526
Test name
Test status
Simulation time 448904063 ps
CPU time 1.39 seconds
Started Mar 14 01:23:42 PM PDT 24
Finished Mar 14 01:23:44 PM PDT 24
Peak memory 197096 kb
Host smart-a7b808bb-a478-45f3-97b7-0de6ac053a3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971502775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2971502775
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2209197295
Short name T189
Test name
Test status
Simulation time 9206666092 ps
CPU time 125.68 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:25:52 PM PDT 24
Peak memory 198436 kb
Host smart-c787f9a8-adfd-4fae-9fa9-ca4a923d8858
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209197295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2209197295
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3335105077
Short name T455
Test name
Test status
Simulation time 62728613 ps
CPU time 0.55 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 194860 kb
Host smart-421228f2-85fa-4f2f-a854-dafb5dea0271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335105077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3335105077
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.15944535
Short name T19
Test name
Test status
Simulation time 63679362 ps
CPU time 0.75 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 194280 kb
Host smart-b562ca53-976e-422d-b83a-e8ad2d93603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15944535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.15944535
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2013241882
Short name T451
Test name
Test status
Simulation time 4604578367 ps
CPU time 22.41 seconds
Started Mar 14 01:23:50 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 196940 kb
Host smart-ceb326c1-6af2-4109-9b10-ef9262f1873f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013241882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2013241882
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2216945323
Short name T242
Test name
Test status
Simulation time 52643969 ps
CPU time 0.82 seconds
Started Mar 14 01:23:48 PM PDT 24
Finished Mar 14 01:23:49 PM PDT 24
Peak memory 196852 kb
Host smart-4e320a81-50be-4331-b969-9220a6ffc246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216945323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2216945323
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3094542729
Short name T629
Test name
Test status
Simulation time 83033767 ps
CPU time 1.45 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 197268 kb
Host smart-8d9312e3-a8bb-4c3a-8956-758a5ac14ba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094542729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3094542729
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3369004689
Short name T630
Test name
Test status
Simulation time 89004716 ps
CPU time 3.71 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:23:49 PM PDT 24
Peak memory 198292 kb
Host smart-c6335a48-998a-4c13-bbc9-1f96261e3eaf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369004689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3369004689
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2427581225
Short name T570
Test name
Test status
Simulation time 218848824 ps
CPU time 2.11 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 197224 kb
Host smart-34bb87f6-5c84-4529-9576-14476611da60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427581225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2427581225
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3802263295
Short name T115
Test name
Test status
Simulation time 17075623 ps
CPU time 0.7 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:23:58 PM PDT 24
Peak memory 194588 kb
Host smart-359c877b-aa36-4026-af12-23afd030b512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802263295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3802263295
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1889951327
Short name T283
Test name
Test status
Simulation time 58754545 ps
CPU time 1.18 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:45 PM PDT 24
Peak memory 197276 kb
Host smart-549a7e3f-3a40-4ad2-9175-40a243d6f7b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889951327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1889951327
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.670206281
Short name T248
Test name
Test status
Simulation time 176152120 ps
CPU time 3.77 seconds
Started Mar 14 01:23:51 PM PDT 24
Finished Mar 14 01:23:55 PM PDT 24
Peak memory 198260 kb
Host smart-7e4ee31b-20f0-4dd0-8871-3d826664438b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670206281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.670206281
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3693856018
Short name T280
Test name
Test status
Simulation time 224525028 ps
CPU time 1.28 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 195856 kb
Host smart-4e6b11a6-5d08-41ff-b338-a613ca80dc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693856018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3693856018
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.372590234
Short name T61
Test name
Test status
Simulation time 145150926 ps
CPU time 0.89 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:23:57 PM PDT 24
Peak memory 195424 kb
Host smart-fc84e238-f789-44e3-be0a-a8c97f333c03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372590234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.372590234
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2486024856
Short name T359
Test name
Test status
Simulation time 17656291165 ps
CPU time 193.6 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:26:59 PM PDT 24
Peak memory 198372 kb
Host smart-2a904c07-0fa2-4a73-b9c4-e911d37fca16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486024856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2486024856
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1677621977
Short name T193
Test name
Test status
Simulation time 14412150 ps
CPU time 0.6 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 194092 kb
Host smart-652932e4-edbd-45b0-8559-6e4c3321378c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677621977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1677621977
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3432265966
Short name T202
Test name
Test status
Simulation time 58701656 ps
CPU time 0.66 seconds
Started Mar 14 01:23:48 PM PDT 24
Finished Mar 14 01:23:48 PM PDT 24
Peak memory 194932 kb
Host smart-e40a9d25-af9c-4f9b-a5f5-2285efcc9377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432265966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3432265966
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.955959004
Short name T656
Test name
Test status
Simulation time 1409642806 ps
CPU time 8.66 seconds
Started Mar 14 01:23:47 PM PDT 24
Finished Mar 14 01:23:56 PM PDT 24
Peak memory 198280 kb
Host smart-17d5be5f-24c4-45a7-946b-9eedc2bbdf0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955959004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.955959004
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.568681371
Short name T134
Test name
Test status
Simulation time 243873612 ps
CPU time 0.88 seconds
Started Mar 14 01:23:46 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 196132 kb
Host smart-00814347-3eff-4045-a358-f391f3481645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568681371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.568681371
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1398151706
Short name T321
Test name
Test status
Simulation time 420114310 ps
CPU time 1.44 seconds
Started Mar 14 01:23:42 PM PDT 24
Finished Mar 14 01:23:43 PM PDT 24
Peak memory 197292 kb
Host smart-a44c7e7c-8102-4281-b5fc-d1d96592fd69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398151706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1398151706
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3188458632
Short name T334
Test name
Test status
Simulation time 84628701 ps
CPU time 3.55 seconds
Started Mar 14 01:23:47 PM PDT 24
Finished Mar 14 01:23:51 PM PDT 24
Peak memory 198444 kb
Host smart-77dd2a14-f87c-47ae-a064-bc0c41a20c54
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188458632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3188458632
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1141873812
Short name T581
Test name
Test status
Simulation time 73872353 ps
CPU time 2.54 seconds
Started Mar 14 01:23:47 PM PDT 24
Finished Mar 14 01:23:50 PM PDT 24
Peak memory 198332 kb
Host smart-7f4589d2-5cca-4d87-81cc-e0b93d7217ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141873812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1141873812
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1051057253
Short name T120
Test name
Test status
Simulation time 277528380 ps
CPU time 1.3 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:45 PM PDT 24
Peak memory 196156 kb
Host smart-80bbd732-c6a1-4cba-910f-42187e7b420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051057253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1051057253
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1985450749
Short name T523
Test name
Test status
Simulation time 443707220 ps
CPU time 1.3 seconds
Started Mar 14 01:23:48 PM PDT 24
Finished Mar 14 01:23:49 PM PDT 24
Peak memory 196852 kb
Host smart-a22a118e-0dc9-4f20-8db1-842ff27b129d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985450749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1985450749
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1330991571
Short name T699
Test name
Test status
Simulation time 405881808 ps
CPU time 3.45 seconds
Started Mar 14 01:23:47 PM PDT 24
Finished Mar 14 01:23:51 PM PDT 24
Peak memory 198268 kb
Host smart-ba2b8d72-2fd5-439c-afff-bea86178fc4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330991571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1330991571
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1671160896
Short name T552
Test name
Test status
Simulation time 90918258 ps
CPU time 1.15 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 196012 kb
Host smart-1e876992-4519-43a1-95d3-ec40e4c2d7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671160896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1671160896
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.994875112
Short name T245
Test name
Test status
Simulation time 79553577 ps
CPU time 1.09 seconds
Started Mar 14 01:23:48 PM PDT 24
Finished Mar 14 01:23:49 PM PDT 24
Peak memory 196100 kb
Host smart-595db9e7-be8a-4656-9486-ae174fbd4071
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994875112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.994875112
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4264528642
Short name T627
Test name
Test status
Simulation time 13811959369 ps
CPU time 87.18 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:25:10 PM PDT 24
Peak memory 198376 kb
Host smart-6c303682-f5b4-42b2-a5df-f048407c47d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264528642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4264528642
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1641234717
Short name T70
Test name
Test status
Simulation time 239788130119 ps
CPU time 1076.22 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:41:40 PM PDT 24
Peak memory 198520 kb
Host smart-aa27f0a6-c625-4b86-a5a2-5294af4868e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1641234717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1641234717
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.102147527
Short name T688
Test name
Test status
Simulation time 39830683 ps
CPU time 0.59 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 194144 kb
Host smart-ef36fc14-feed-4d54-9d1b-32c607981816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102147527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.102147527
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.4088887671
Short name T416
Test name
Test status
Simulation time 156088072 ps
CPU time 1.01 seconds
Started Mar 14 01:23:47 PM PDT 24
Finished Mar 14 01:23:49 PM PDT 24
Peak memory 196884 kb
Host smart-aff7b8ec-3830-4f23-93fe-33941982fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088887671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.4088887671
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3760039013
Short name T468
Test name
Test status
Simulation time 1386799024 ps
CPU time 20.05 seconds
Started Mar 14 01:23:49 PM PDT 24
Finished Mar 14 01:24:09 PM PDT 24
Peak memory 198300 kb
Host smart-ad00250e-1a77-4727-8057-6f27918b5fae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760039013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3760039013
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.565772912
Short name T560
Test name
Test status
Simulation time 98939717 ps
CPU time 0.93 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 196976 kb
Host smart-75d13469-57af-430d-851b-e4b8e3b67472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565772912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.565772912
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2527337368
Short name T138
Test name
Test status
Simulation time 86344301 ps
CPU time 1.22 seconds
Started Mar 14 01:23:45 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 196496 kb
Host smart-dc24fc4f-aa3a-4900-b70a-7fa7d1b9b4aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527337368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2527337368
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2084759471
Short name T418
Test name
Test status
Simulation time 95632895 ps
CPU time 3.8 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:49 PM PDT 24
Peak memory 198348 kb
Host smart-93d8f0f3-9104-4979-bfa3-1497eddfa64a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084759471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2084759471
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3763148561
Short name T701
Test name
Test status
Simulation time 371716332 ps
CPU time 3.4 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:47 PM PDT 24
Peak memory 198424 kb
Host smart-3ef60c22-24bb-44b4-afa1-9de3dc4a0d30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763148561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3763148561
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.4153258429
Short name T670
Test name
Test status
Simulation time 61078661 ps
CPU time 1.27 seconds
Started Mar 14 01:23:44 PM PDT 24
Finished Mar 14 01:23:46 PM PDT 24
Peak memory 196932 kb
Host smart-89c3cbe6-bb5e-4e04-9d92-7277525022cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153258429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.4153258429
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2026253117
Short name T365
Test name
Test status
Simulation time 34090231 ps
CPU time 1.32 seconds
Started Mar 14 01:23:42 PM PDT 24
Finished Mar 14 01:23:44 PM PDT 24
Peak memory 198444 kb
Host smart-e7efca7b-b725-4039-b688-bb8b21e8c9d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026253117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2026253117
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3940517386
Short name T574
Test name
Test status
Simulation time 579607697 ps
CPU time 3.03 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:02 PM PDT 24
Peak memory 198300 kb
Host smart-2f815e4c-05a0-4ad8-a29c-000c36d116a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940517386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3940517386
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4123006050
Short name T316
Test name
Test status
Simulation time 82854680 ps
CPU time 0.89 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:44 PM PDT 24
Peak memory 196672 kb
Host smart-69bb81e1-b88f-4824-86fc-9a35fbab3f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123006050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4123006050
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3743974291
Short name T389
Test name
Test status
Simulation time 52049396 ps
CPU time 1.08 seconds
Started Mar 14 01:23:43 PM PDT 24
Finished Mar 14 01:23:44 PM PDT 24
Peak memory 196568 kb
Host smart-bbddfe22-5a59-4477-b9ca-99402d3b2d92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743974291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3743974291
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2407139888
Short name T204
Test name
Test status
Simulation time 7142479685 ps
CPU time 100.24 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:25:38 PM PDT 24
Peak memory 198456 kb
Host smart-115822a0-8fae-40b4-a290-82a5f025066c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407139888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2407139888
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.4080990652
Short name T80
Test name
Test status
Simulation time 26249779 ps
CPU time 0.64 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:23:57 PM PDT 24
Peak memory 194336 kb
Host smart-bfc56d5d-5fb2-48e4-becb-997a76730846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080990652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.4080990652
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.424952229
Short name T232
Test name
Test status
Simulation time 35841906 ps
CPU time 0.82 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:23:57 PM PDT 24
Peak memory 195492 kb
Host smart-b54f4468-2a9e-4b01-846d-2a116b84cd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424952229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.424952229
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2573874739
Short name T177
Test name
Test status
Simulation time 1015989542 ps
CPU time 15.89 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 198320 kb
Host smart-fd4309cc-e963-47ca-a4a5-c5eca6915fde
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573874739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2573874739
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2841277261
Short name T378
Test name
Test status
Simulation time 310460611 ps
CPU time 1 seconds
Started Mar 14 01:24:00 PM PDT 24
Finished Mar 14 01:24:02 PM PDT 24
Peak memory 198140 kb
Host smart-ecf84be5-e1c9-4c1c-9b63-3bdb135c4b68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841277261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2841277261
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2170237293
Short name T27
Test name
Test status
Simulation time 47557085 ps
CPU time 1.42 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:02 PM PDT 24
Peak memory 197324 kb
Host smart-3dfa913f-01d2-4dd5-94b2-16ca453fb18a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170237293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2170237293
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1585612689
Short name T200
Test name
Test status
Simulation time 780915204 ps
CPU time 2.54 seconds
Started Mar 14 01:23:54 PM PDT 24
Finished Mar 14 01:23:56 PM PDT 24
Peak memory 198452 kb
Host smart-583e69fe-cf7e-4ddc-b6cd-1eabfc5528c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585612689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1585612689
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.4252103657
Short name T135
Test name
Test status
Simulation time 138743714 ps
CPU time 3.09 seconds
Started Mar 14 01:24:02 PM PDT 24
Finished Mar 14 01:24:06 PM PDT 24
Peak memory 197604 kb
Host smart-c8b49b6d-f5b8-4097-8db1-a7799086247d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252103657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.4252103657
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1478586758
Short name T222
Test name
Test status
Simulation time 66578889 ps
CPU time 1.34 seconds
Started Mar 14 01:23:54 PM PDT 24
Finished Mar 14 01:23:56 PM PDT 24
Peak memory 196928 kb
Host smart-66351392-d590-4b46-aa6b-3e2bafba1ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478586758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1478586758
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2680275102
Short name T358
Test name
Test status
Simulation time 137106202 ps
CPU time 0.89 seconds
Started Mar 14 01:23:55 PM PDT 24
Finished Mar 14 01:23:56 PM PDT 24
Peak memory 196848 kb
Host smart-8980a69c-87e2-44ed-b71b-68f84359d5a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680275102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2680275102
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3739398983
Short name T634
Test name
Test status
Simulation time 251149554 ps
CPU time 3.02 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:04 PM PDT 24
Peak memory 198220 kb
Host smart-9faa2de3-ddc8-43be-99b2-bea2f2347889
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739398983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3739398983
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3229175247
Short name T373
Test name
Test status
Simulation time 53271190 ps
CPU time 1.41 seconds
Started Mar 14 01:24:00 PM PDT 24
Finished Mar 14 01:24:03 PM PDT 24
Peak memory 195896 kb
Host smart-05d3bc0f-58d7-463c-9096-c805d5b1178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229175247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3229175247
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1719618535
Short name T380
Test name
Test status
Simulation time 130782991 ps
CPU time 0.98 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:23:58 PM PDT 24
Peak memory 196448 kb
Host smart-b44eea15-4726-4442-a647-574c8d193ca3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719618535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1719618535
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1093048998
Short name T645
Test name
Test status
Simulation time 94860414645 ps
CPU time 54.05 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:53 PM PDT 24
Peak memory 198428 kb
Host smart-59ad991d-f5fc-4431-a197-8676e59f0326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093048998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1093048998
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3036126386
Short name T397
Test name
Test status
Simulation time 46414464332 ps
CPU time 1190.95 seconds
Started Mar 14 01:24:02 PM PDT 24
Finished Mar 14 01:43:53 PM PDT 24
Peak memory 198472 kb
Host smart-3835e5ea-8e8f-4f63-8e36-85b58e4c1911
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3036126386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3036126386
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2292217589
Short name T478
Test name
Test status
Simulation time 38328295 ps
CPU time 0.65 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:23:59 PM PDT 24
Peak memory 194176 kb
Host smart-56b572de-e326-4b5b-a0ba-21948ffbbe14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292217589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2292217589
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2147860768
Short name T680
Test name
Test status
Simulation time 69288866 ps
CPU time 0.84 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:23:59 PM PDT 24
Peak memory 196440 kb
Host smart-b25c2482-6bc7-4a86-83d5-0e24d525ef09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147860768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2147860768
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.315852317
Short name T257
Test name
Test status
Simulation time 997807322 ps
CPU time 25.98 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:26 PM PDT 24
Peak memory 195832 kb
Host smart-cdefc842-2a1e-44a5-8a2d-6a7cebce4349
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315852317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.315852317
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.97019183
Short name T379
Test name
Test status
Simulation time 226573035 ps
CPU time 0.95 seconds
Started Mar 14 01:23:53 PM PDT 24
Finished Mar 14 01:23:54 PM PDT 24
Peak memory 198204 kb
Host smart-61cfebab-7e85-4c25-8bf0-047005c73739
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97019183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.97019183
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.615999830
Short name T452
Test name
Test status
Simulation time 94973313 ps
CPU time 1.03 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 196792 kb
Host smart-0c7ee317-ba66-43f8-abf6-3e8573e86205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615999830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.615999830
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2532671093
Short name T595
Test name
Test status
Simulation time 174694048 ps
CPU time 2.03 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:23:59 PM PDT 24
Peak memory 198456 kb
Host smart-4ad7bda2-c03c-41ed-8776-68ff213fe6c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532671093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2532671093
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2601303162
Short name T289
Test name
Test status
Simulation time 322695285 ps
CPU time 1.95 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:23:58 PM PDT 24
Peak memory 196500 kb
Host smart-81c72a25-3af6-4b5e-a859-3c34893bb196
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601303162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2601303162
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3485898436
Short name T116
Test name
Test status
Simulation time 42072092 ps
CPU time 0.72 seconds
Started Mar 14 01:23:52 PM PDT 24
Finished Mar 14 01:23:53 PM PDT 24
Peak memory 195624 kb
Host smart-1685277a-05df-49fb-855c-1a0445d0b984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485898436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3485898436
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.919285256
Short name T146
Test name
Test status
Simulation time 135552985 ps
CPU time 0.91 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 196888 kb
Host smart-ad0ee594-5957-4bce-9e07-d1f2d3f3839d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919285256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.919285256
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3445809542
Short name T64
Test name
Test status
Simulation time 1312927740 ps
CPU time 3.72 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 198324 kb
Host smart-e1cbdd7b-0792-4bd5-b0bb-7a49d7f867e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445809542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3445809542
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2616489301
Short name T538
Test name
Test status
Simulation time 191868689 ps
CPU time 1.03 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:01 PM PDT 24
Peak memory 195992 kb
Host smart-15432eb4-220e-4cb7-b89e-b428af54e666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616489301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2616489301
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4196547476
Short name T646
Test name
Test status
Simulation time 269115788 ps
CPU time 1.17 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:23:59 PM PDT 24
Peak memory 195956 kb
Host smart-da49cd85-72fa-4494-a6db-523cc96ec81b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196547476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4196547476
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1615747460
Short name T122
Test name
Test status
Simulation time 28944992071 ps
CPU time 87.18 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 198444 kb
Host smart-ad011e80-293a-43c9-afbf-7aac2773be6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615747460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1615747460
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2672621188
Short name T255
Test name
Test status
Simulation time 23102633 ps
CPU time 0.57 seconds
Started Mar 14 01:24:02 PM PDT 24
Finished Mar 14 01:24:03 PM PDT 24
Peak memory 194128 kb
Host smart-6d2955df-f617-43c3-8aa0-96c40027ee29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672621188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2672621188
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.565689715
Short name T156
Test name
Test status
Simulation time 35926764 ps
CPU time 0.68 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 195000 kb
Host smart-cddd6eee-1458-41cd-bf13-d52a3bd6e72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565689715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.565689715
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.48968387
Short name T298
Test name
Test status
Simulation time 793722065 ps
CPU time 26.4 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:24:23 PM PDT 24
Peak memory 195744 kb
Host smart-40dcc004-5f6b-4d40-ab8b-751831455839
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48968387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stress
.48968387
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3812502739
Short name T330
Test name
Test status
Simulation time 97284051 ps
CPU time 0.7 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:23:59 PM PDT 24
Peak memory 194780 kb
Host smart-ec5d0cb0-77f3-4285-9e4b-9f31be23f64d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812502739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3812502739
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.675482528
Short name T540
Test name
Test status
Simulation time 41788005 ps
CPU time 1.17 seconds
Started Mar 14 01:24:00 PM PDT 24
Finished Mar 14 01:24:02 PM PDT 24
Peak memory 196412 kb
Host smart-fc794df4-476a-4d2b-a5be-7263effe61aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675482528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.675482528
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.297210221
Short name T565
Test name
Test status
Simulation time 178297043 ps
CPU time 3.86 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:03 PM PDT 24
Peak memory 196660 kb
Host smart-fd7e17d4-3252-4093-9d5b-888965bbf314
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297210221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.297210221
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1036870211
Short name T192
Test name
Test status
Simulation time 656599476 ps
CPU time 3.19 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 196148 kb
Host smart-14fa4ee1-5109-4de1-9314-69dcc1fb098b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036870211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1036870211
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3786591784
Short name T461
Test name
Test status
Simulation time 46267582 ps
CPU time 0.89 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 196156 kb
Host smart-39642678-1093-4c09-aa26-f222bd3402ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786591784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3786591784
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2468198982
Short name T410
Test name
Test status
Simulation time 41026824 ps
CPU time 0.91 seconds
Started Mar 14 01:23:55 PM PDT 24
Finished Mar 14 01:23:56 PM PDT 24
Peak memory 196348 kb
Host smart-fa529922-b7b2-40bd-ae35-20466ab463fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468198982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2468198982
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1078759870
Short name T454
Test name
Test status
Simulation time 68489973 ps
CPU time 1.49 seconds
Started Mar 14 01:24:02 PM PDT 24
Finished Mar 14 01:24:04 PM PDT 24
Peak memory 198300 kb
Host smart-49b1c238-56f2-43ca-b979-2382b8b6007d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078759870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1078759870
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1935565634
Short name T362
Test name
Test status
Simulation time 28699243 ps
CPU time 1.06 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:23:58 PM PDT 24
Peak memory 195864 kb
Host smart-4f20dc8e-129e-4bd7-88b3-f5ffc1d5c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935565634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1935565634
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3606496618
Short name T505
Test name
Test status
Simulation time 72288789 ps
CPU time 1.11 seconds
Started Mar 14 01:23:54 PM PDT 24
Finished Mar 14 01:23:55 PM PDT 24
Peak memory 196800 kb
Host smart-4f19468d-eb7b-4ebd-8ce5-44aed1dab346
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606496618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3606496618
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2317095952
Short name T340
Test name
Test status
Simulation time 8242074765 ps
CPU time 53.65 seconds
Started Mar 14 01:23:54 PM PDT 24
Finished Mar 14 01:24:48 PM PDT 24
Peak memory 198416 kb
Host smart-1a902590-5fcb-4f64-bcc5-63ecfa26b8d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317095952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2317095952
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.225541629
Short name T287
Test name
Test status
Simulation time 212171819367 ps
CPU time 2073.2 seconds
Started Mar 14 01:23:57 PM PDT 24
Finished Mar 14 01:58:31 PM PDT 24
Peak memory 198528 kb
Host smart-d13227c4-93e4-4cb8-8e68-af9f27d1be0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=225541629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.225541629
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2695924159
Short name T161
Test name
Test status
Simulation time 55082956 ps
CPU time 0.64 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 195180 kb
Host smart-2015a38c-8598-42aa-ba2e-584b359a54f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695924159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2695924159
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4269408548
Short name T471
Test name
Test status
Simulation time 54205879 ps
CPU time 0.61 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:23:57 PM PDT 24
Peak memory 194192 kb
Host smart-706cb745-310d-494d-973d-91a1d891c8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269408548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4269408548
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.445260661
Short name T494
Test name
Test status
Simulation time 496334545 ps
CPU time 4.21 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:04 PM PDT 24
Peak memory 196288 kb
Host smart-1541befb-caaa-45cf-8c23-b2ef8bb284c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445260661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.445260661
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.133904543
Short name T65
Test name
Test status
Simulation time 67739157 ps
CPU time 1.06 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:02 PM PDT 24
Peak memory 197504 kb
Host smart-bf9b5270-cc40-4797-ac76-a10d19fb4b33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133904543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.133904543
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.62682145
Short name T598
Test name
Test status
Simulation time 59843869 ps
CPU time 1.43 seconds
Started Mar 14 01:23:55 PM PDT 24
Finished Mar 14 01:23:57 PM PDT 24
Peak memory 197384 kb
Host smart-d9f2c1f7-35b7-4b04-a6f3-ac42a51480c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62682145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.62682145
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.606535799
Short name T555
Test name
Test status
Simulation time 179685626 ps
CPU time 2.04 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:23:58 PM PDT 24
Peak memory 196696 kb
Host smart-9319df20-bd53-454d-b321-3426d64244d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606535799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.606535799
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2569795750
Short name T118
Test name
Test status
Simulation time 51685054 ps
CPU time 1.39 seconds
Started Mar 14 01:23:55 PM PDT 24
Finished Mar 14 01:23:57 PM PDT 24
Peak memory 196088 kb
Host smart-c95b3fc4-8740-4138-a088-e324cea712fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569795750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2569795750
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4208626915
Short name T114
Test name
Test status
Simulation time 215356900 ps
CPU time 1.24 seconds
Started Mar 14 01:23:55 PM PDT 24
Finished Mar 14 01:23:57 PM PDT 24
Peak memory 197332 kb
Host smart-7fc178d1-3acb-49e0-a331-8525ddbb584a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208626915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4208626915
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.450612093
Short name T589
Test name
Test status
Simulation time 46549196 ps
CPU time 1.03 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:01 PM PDT 24
Peak memory 196100 kb
Host smart-c21a4a7d-c6f3-4fca-9859-9e7696aa8130
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450612093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.450612093
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.844872382
Short name T495
Test name
Test status
Simulation time 356165313 ps
CPU time 1.75 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:01 PM PDT 24
Peak memory 198196 kb
Host smart-3cd97fa7-b6b6-4c21-a44b-36fecca571a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844872382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.844872382
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.4017874047
Short name T419
Test name
Test status
Simulation time 285180105 ps
CPU time 1.35 seconds
Started Mar 14 01:23:55 PM PDT 24
Finished Mar 14 01:23:56 PM PDT 24
Peak memory 197016 kb
Host smart-ee1b2f39-1030-4121-aa0e-22f24dde52f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017874047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.4017874047
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2980446594
Short name T159
Test name
Test status
Simulation time 35457142 ps
CPU time 0.97 seconds
Started Mar 14 01:24:01 PM PDT 24
Finished Mar 14 01:24:02 PM PDT 24
Peak memory 195472 kb
Host smart-d6fa8e34-dc18-4417-ba92-ce4bdff7038e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980446594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2980446594
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1184713975
Short name T448
Test name
Test status
Simulation time 18523368521 ps
CPU time 40.85 seconds
Started Mar 14 01:23:55 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 198428 kb
Host smart-3aaf10d8-844c-430f-8287-c46f5069adfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184713975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1184713975
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.3019183797
Short name T349
Test name
Test status
Simulation time 16195638754 ps
CPU time 489.31 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:32:09 PM PDT 24
Peak memory 198516 kb
Host smart-e8cca510-b72c-49a4-85f4-5145bca79bc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3019183797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.3019183797
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3115955786
Short name T296
Test name
Test status
Simulation time 41004061 ps
CPU time 0.61 seconds
Started Mar 14 01:22:44 PM PDT 24
Finished Mar 14 01:22:45 PM PDT 24
Peak memory 194860 kb
Host smart-374a17e0-3e35-44bc-9d9e-54db267ae912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115955786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3115955786
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.551424869
Short name T209
Test name
Test status
Simulation time 35592496 ps
CPU time 0.69 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:43 PM PDT 24
Peak memory 194408 kb
Host smart-08715c63-1973-4d17-b896-becd353e91b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551424869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.551424869
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2340565215
Short name T345
Test name
Test status
Simulation time 2334713468 ps
CPU time 18.16 seconds
Started Mar 14 01:22:44 PM PDT 24
Finished Mar 14 01:23:02 PM PDT 24
Peak memory 197100 kb
Host smart-eb8e879c-94ca-4a15-b54a-b1e7047d2323
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340565215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2340565215
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3653175436
Short name T682
Test name
Test status
Simulation time 824609522 ps
CPU time 0.82 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 196928 kb
Host smart-c5cbca08-cbdd-46ee-9a5f-81cc4f5f2ac7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653175436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3653175436
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1535717604
Short name T668
Test name
Test status
Simulation time 26385698 ps
CPU time 0.78 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 195764 kb
Host smart-5231bcff-9515-40d9-b142-67da09c15edb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535717604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1535717604
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2613091767
Short name T324
Test name
Test status
Simulation time 88869331 ps
CPU time 3.7 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:47 PM PDT 24
Peak memory 198476 kb
Host smart-9ae41aa1-4011-49a8-91dd-45cea25ec8fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613091767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2613091767
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1417346033
Short name T465
Test name
Test status
Simulation time 920932104 ps
CPU time 2.86 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:46 PM PDT 24
Peak memory 197520 kb
Host smart-604693e8-d26c-4701-bd76-84d364e1ec0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417346033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1417346033
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2872695717
Short name T467
Test name
Test status
Simulation time 59096504 ps
CPU time 1.26 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:22:45 PM PDT 24
Peak memory 196192 kb
Host smart-13971337-2ca3-4725-9d7a-b6d599e6bc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872695717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2872695717
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.851519062
Short name T313
Test name
Test status
Simulation time 266494901 ps
CPU time 1.42 seconds
Started Mar 14 01:22:43 PM PDT 24
Finished Mar 14 01:22:45 PM PDT 24
Peak memory 198360 kb
Host smart-13b41faa-f9a1-4eca-a6fd-2298f3fd1fc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851519062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.851519062
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.243736011
Short name T6
Test name
Test status
Simulation time 654400021 ps
CPU time 4.28 seconds
Started Mar 14 01:22:40 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 198252 kb
Host smart-566fd8a8-6b84-46d9-9d95-4b77531b95b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243736011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.243736011
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.4102096355
Short name T56
Test name
Test status
Simulation time 67358486 ps
CPU time 0.79 seconds
Started Mar 14 01:22:41 PM PDT 24
Finished Mar 14 01:22:42 PM PDT 24
Peak memory 213576 kb
Host smart-cb5eb9aa-c119-4f4e-aa3e-5774446e935c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102096355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.4102096355
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1632249842
Short name T17
Test name
Test status
Simulation time 91159660 ps
CPU time 1.17 seconds
Started Mar 14 01:22:42 PM PDT 24
Finished Mar 14 01:22:44 PM PDT 24
Peak memory 195924 kb
Host smart-e260e8de-19f5-4d8d-a243-cd3aeadbe71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632249842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1632249842
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1191478394
Short name T640
Test name
Test status
Simulation time 128454946 ps
CPU time 1.2 seconds
Started Mar 14 01:22:41 PM PDT 24
Finished Mar 14 01:22:43 PM PDT 24
Peak memory 196768 kb
Host smart-22703191-3f71-4d38-aeee-3ea2bd57cc3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191478394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1191478394
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3384720633
Short name T360
Test name
Test status
Simulation time 36141230147 ps
CPU time 135.84 seconds
Started Mar 14 01:22:44 PM PDT 24
Finished Mar 14 01:25:00 PM PDT 24
Peak memory 198448 kb
Host smart-7cffbba2-7528-4858-95af-ffc8b4df5108
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384720633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3384720633
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3435061053
Short name T374
Test name
Test status
Simulation time 11234386 ps
CPU time 0.58 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 194028 kb
Host smart-cb84b990-c35b-4ce1-babd-769eb57022cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435061053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3435061053
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3662440147
Short name T480
Test name
Test status
Simulation time 408890249 ps
CPU time 0.98 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:00 PM PDT 24
Peak memory 196232 kb
Host smart-d13b645d-ff1e-4499-93f8-79d51aa69067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662440147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3662440147
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.690993576
Short name T621
Test name
Test status
Simulation time 1060734797 ps
CPU time 10.46 seconds
Started Mar 14 01:24:03 PM PDT 24
Finished Mar 14 01:24:14 PM PDT 24
Peak memory 197480 kb
Host smart-693d3b41-5652-48c4-a519-3b9524c94c0b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690993576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.690993576
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1996047278
Short name T660
Test name
Test status
Simulation time 61458379 ps
CPU time 0.95 seconds
Started Mar 14 01:24:02 PM PDT 24
Finished Mar 14 01:24:03 PM PDT 24
Peak memory 196940 kb
Host smart-04a9257d-1d88-4584-bdfb-6924d2eec0cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996047278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1996047278
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.788756190
Short name T575
Test name
Test status
Simulation time 179030103 ps
CPU time 1.38 seconds
Started Mar 14 01:24:00 PM PDT 24
Finished Mar 14 01:24:02 PM PDT 24
Peak memory 198264 kb
Host smart-77d35eaa-94a6-4052-9a5c-4f9b06381199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788756190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.788756190
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4107905532
Short name T174
Test name
Test status
Simulation time 33715756 ps
CPU time 1.28 seconds
Started Mar 14 01:23:54 PM PDT 24
Finished Mar 14 01:23:56 PM PDT 24
Peak memory 196856 kb
Host smart-5ea38de8-6d1a-452a-a9a3-5aa2b094220c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107905532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4107905532
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3407256790
Short name T155
Test name
Test status
Simulation time 60945197 ps
CPU time 1.95 seconds
Started Mar 14 01:24:01 PM PDT 24
Finished Mar 14 01:24:03 PM PDT 24
Peak memory 197636 kb
Host smart-eac078c6-b1d4-4f20-b3bf-1b2ea2d876d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407256790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3407256790
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.298398970
Short name T399
Test name
Test status
Simulation time 168321122 ps
CPU time 1.27 seconds
Started Mar 14 01:23:55 PM PDT 24
Finished Mar 14 01:23:57 PM PDT 24
Peak memory 197460 kb
Host smart-9937e4e7-e892-4fe7-bdf1-db2d2f7c666d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298398970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.298398970
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2101126878
Short name T173
Test name
Test status
Simulation time 121274355 ps
CPU time 0.73 seconds
Started Mar 14 01:24:02 PM PDT 24
Finished Mar 14 01:24:03 PM PDT 24
Peak memory 195676 kb
Host smart-5918de17-c968-41b4-bd0a-de0c6f759eae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101126878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2101126878
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1466530717
Short name T127
Test name
Test status
Simulation time 608634499 ps
CPU time 2.76 seconds
Started Mar 14 01:24:03 PM PDT 24
Finished Mar 14 01:24:06 PM PDT 24
Peak memory 197968 kb
Host smart-01d8337b-cd45-44d1-9971-80f989ffab5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466530717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1466530717
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3805278316
Short name T268
Test name
Test status
Simulation time 48726511 ps
CPU time 1.37 seconds
Started Mar 14 01:23:58 PM PDT 24
Finished Mar 14 01:24:01 PM PDT 24
Peak memory 196996 kb
Host smart-01e9bc37-43f0-4b1a-83de-0025f63e2914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805278316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3805278316
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3613536413
Short name T11
Test name
Test status
Simulation time 173379314 ps
CPU time 1.33 seconds
Started Mar 14 01:23:59 PM PDT 24
Finished Mar 14 01:24:01 PM PDT 24
Peak memory 196948 kb
Host smart-8f9675b0-720b-4a26-a1a4-e87e6288ca91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613536413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3613536413
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3827881270
Short name T7
Test name
Test status
Simulation time 12488003925 ps
CPU time 34.68 seconds
Started Mar 14 01:23:56 PM PDT 24
Finished Mar 14 01:24:31 PM PDT 24
Peak memory 198412 kb
Host smart-450203bc-550c-4949-84d0-cb63e0978a86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827881270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3827881270
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3512579187
Short name T522
Test name
Test status
Simulation time 154586633372 ps
CPU time 996.12 seconds
Started Mar 14 01:24:03 PM PDT 24
Finished Mar 14 01:40:40 PM PDT 24
Peak memory 198500 kb
Host smart-1d05af0b-6795-4f19-8e38-214357b6d8fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3512579187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3512579187
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2540498636
Short name T264
Test name
Test status
Simulation time 11423029 ps
CPU time 0.57 seconds
Started Mar 14 01:24:07 PM PDT 24
Finished Mar 14 01:24:08 PM PDT 24
Peak memory 194132 kb
Host smart-908b2d17-acc0-4d6e-ab00-dc27bb61e563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540498636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2540498636
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2830011456
Short name T641
Test name
Test status
Simulation time 34566062 ps
CPU time 0.73 seconds
Started Mar 14 01:24:08 PM PDT 24
Finished Mar 14 01:24:09 PM PDT 24
Peak memory 195032 kb
Host smart-4728d68f-12ed-48ab-a331-5798711b1afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830011456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2830011456
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1424651226
Short name T266
Test name
Test status
Simulation time 206929335 ps
CPU time 10.16 seconds
Started Mar 14 01:24:07 PM PDT 24
Finished Mar 14 01:24:18 PM PDT 24
Peak memory 197032 kb
Host smart-7027fe83-6cee-457c-94b2-270e73dbcea7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424651226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1424651226
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.185487694
Short name T125
Test name
Test status
Simulation time 75464113 ps
CPU time 1.09 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:11 PM PDT 24
Peak memory 196984 kb
Host smart-15a3d52e-2c66-447b-97e2-4c1b602f8dbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185487694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.185487694
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3235723590
Short name T148
Test name
Test status
Simulation time 48707789 ps
CPU time 1.25 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:11 PM PDT 24
Peak memory 197368 kb
Host smart-59a3f035-24a4-4a45-9a32-df9a7cddf290
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235723590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3235723590
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1265339172
Short name T393
Test name
Test status
Simulation time 150432322 ps
CPU time 3.08 seconds
Started Mar 14 01:24:08 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 198472 kb
Host smart-8fecd2a0-d4f1-4f51-9a28-2b0f9041a9c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265339172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1265339172
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.4103761579
Short name T553
Test name
Test status
Simulation time 362990040 ps
CPU time 3.28 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 197456 kb
Host smart-b9f06f08-5226-42cc-a66e-d27ed1b2edd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103761579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.4103761579
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.97585335
Short name T403
Test name
Test status
Simulation time 275670860 ps
CPU time 1.28 seconds
Started Mar 14 01:24:07 PM PDT 24
Finished Mar 14 01:24:09 PM PDT 24
Peak memory 197232 kb
Host smart-ceea4eb0-7794-4666-9c10-37afd28480c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97585335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.97585335
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3568615911
Short name T390
Test name
Test status
Simulation time 55885423 ps
CPU time 1.17 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:11 PM PDT 24
Peak memory 197092 kb
Host smart-ebe59a43-d0e0-474d-a0eb-39d513653552
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568615911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3568615911
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.4184475629
Short name T372
Test name
Test status
Simulation time 356512356 ps
CPU time 4.34 seconds
Started Mar 14 01:24:09 PM PDT 24
Finished Mar 14 01:24:14 PM PDT 24
Peak memory 198384 kb
Host smart-3ac547fe-0d52-49a7-9b0e-1f49ab78753f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184475629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.4184475629
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3858867031
Short name T260
Test name
Test status
Simulation time 101619349 ps
CPU time 0.99 seconds
Started Mar 14 01:24:06 PM PDT 24
Finished Mar 14 01:24:08 PM PDT 24
Peak memory 195860 kb
Host smart-69f6e440-7240-49b4-93e0-52e8c55db19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858867031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3858867031
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3821043844
Short name T352
Test name
Test status
Simulation time 189582119 ps
CPU time 1.43 seconds
Started Mar 14 01:24:07 PM PDT 24
Finished Mar 14 01:24:09 PM PDT 24
Peak memory 197156 kb
Host smart-de30b149-893d-4dc7-9bc1-f27ad8b772b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821043844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3821043844
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2973852981
Short name T3
Test name
Test status
Simulation time 90666599220 ps
CPU time 59.52 seconds
Started Mar 14 01:24:09 PM PDT 24
Finished Mar 14 01:25:09 PM PDT 24
Peak memory 198456 kb
Host smart-a4d897ad-0d88-43f9-9d79-4b49b5dedb51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973852981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2973852981
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.4138069954
Short name T561
Test name
Test status
Simulation time 89771037087 ps
CPU time 894.12 seconds
Started Mar 14 01:24:15 PM PDT 24
Finished Mar 14 01:39:10 PM PDT 24
Peak memory 198432 kb
Host smart-e7a465df-8b8e-4fe6-b21e-df5ea5fbf5db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4138069954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.4138069954
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.379946769
Short name T171
Test name
Test status
Simulation time 46034163 ps
CPU time 0.58 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 194764 kb
Host smart-4543f270-9b88-4371-a98f-1f25666646e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379946769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.379946769
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3572855807
Short name T377
Test name
Test status
Simulation time 117554904 ps
CPU time 0.83 seconds
Started Mar 14 01:24:09 PM PDT 24
Finished Mar 14 01:24:10 PM PDT 24
Peak memory 196220 kb
Host smart-1fbda18c-3f17-42f3-a3fa-2e03bce4eb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572855807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3572855807
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2071606768
Short name T333
Test name
Test status
Simulation time 1454782014 ps
CPU time 12.9 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:23 PM PDT 24
Peak memory 196836 kb
Host smart-21839486-3ba9-4057-a227-7a6a41b9da26
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071606768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2071606768
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.335235682
Short name T384
Test name
Test status
Simulation time 89774027 ps
CPU time 0.69 seconds
Started Mar 14 01:24:09 PM PDT 24
Finished Mar 14 01:24:10 PM PDT 24
Peak memory 195588 kb
Host smart-3098389f-94d1-4b90-b8f0-6714dd48237c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335235682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.335235682
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1163408000
Short name T590
Test name
Test status
Simulation time 69407835 ps
CPU time 1.16 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 196848 kb
Host smart-26cae7e3-d5e9-40af-af8f-8183c045325e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163408000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1163408000
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.4181224701
Short name T252
Test name
Test status
Simulation time 258435006 ps
CPU time 3.29 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 198280 kb
Host smart-8ff7a045-64e2-4b57-ae25-dbe6de617bee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181224701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.4181224701
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3741387539
Short name T112
Test name
Test status
Simulation time 182625419 ps
CPU time 1.47 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:13 PM PDT 24
Peak memory 196512 kb
Host smart-e6211fed-8ddd-4a90-baaf-313770ab0226
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741387539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3741387539
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.13936482
Short name T435
Test name
Test status
Simulation time 35865309 ps
CPU time 1.34 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:24:13 PM PDT 24
Peak memory 198252 kb
Host smart-ec3b7b21-95e3-44ec-856e-f1ca3f4fb8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13936482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.13936482
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1889129527
Short name T230
Test name
Test status
Simulation time 55100880 ps
CPU time 1.3 seconds
Started Mar 14 01:24:09 PM PDT 24
Finished Mar 14 01:24:11 PM PDT 24
Peak memory 197412 kb
Host smart-1ac5dc48-cdc6-47dc-b1d1-6d1234e7186a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889129527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1889129527
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.908661733
Short name T654
Test name
Test status
Simulation time 160213015 ps
CPU time 1.69 seconds
Started Mar 14 01:24:07 PM PDT 24
Finished Mar 14 01:24:09 PM PDT 24
Peak memory 198352 kb
Host smart-97db94ce-6620-4513-88c3-990a59751ad4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908661733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.908661733
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.435017312
Short name T500
Test name
Test status
Simulation time 216844107 ps
CPU time 1.11 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:24:13 PM PDT 24
Peak memory 196448 kb
Host smart-73afa979-cfa9-4d59-b992-d214e6b77ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435017312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.435017312
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1115048137
Short name T343
Test name
Test status
Simulation time 68505094 ps
CPU time 1.38 seconds
Started Mar 14 01:24:13 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 197104 kb
Host smart-2a22f564-5a3e-4967-8418-4f36a6b0943c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115048137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1115048137
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.683018631
Short name T710
Test name
Test status
Simulation time 7433921726 ps
CPU time 64.16 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:25:17 PM PDT 24
Peak memory 198356 kb
Host smart-6e6ab3ba-25ef-4dc0-bb66-c58a5efddefb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683018631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.683018631
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3938507349
Short name T307
Test name
Test status
Simulation time 14937688 ps
CPU time 0.58 seconds
Started Mar 14 01:24:17 PM PDT 24
Finished Mar 14 01:24:18 PM PDT 24
Peak memory 194300 kb
Host smart-320901d5-07cf-40b2-b04e-a35ce4d98245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938507349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3938507349
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.734494673
Short name T143
Test name
Test status
Simulation time 25452422 ps
CPU time 0.83 seconds
Started Mar 14 01:24:08 PM PDT 24
Finished Mar 14 01:24:09 PM PDT 24
Peak memory 196336 kb
Host smart-1343dde1-8774-4229-9425-4d5fe3988ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734494673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.734494673
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1687769813
Short name T445
Test name
Test status
Simulation time 2029713218 ps
CPU time 14.77 seconds
Started Mar 14 01:24:16 PM PDT 24
Finished Mar 14 01:24:31 PM PDT 24
Peak memory 196848 kb
Host smart-3b42f994-9ee2-4feb-b75c-fbc221bf1456
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687769813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1687769813
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.476195234
Short name T353
Test name
Test status
Simulation time 300716618 ps
CPU time 1.01 seconds
Started Mar 14 01:24:17 PM PDT 24
Finished Mar 14 01:24:18 PM PDT 24
Peak memory 198228 kb
Host smart-a307476a-d996-46a1-8c62-8858131634bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476195234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.476195234
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.4209688012
Short name T541
Test name
Test status
Simulation time 131428528 ps
CPU time 1.21 seconds
Started Mar 14 01:24:09 PM PDT 24
Finished Mar 14 01:24:10 PM PDT 24
Peak memory 196440 kb
Host smart-2803e55f-cbb1-40a2-a3f4-e7f4e780dd7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209688012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.4209688012
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1338952973
Short name T408
Test name
Test status
Simulation time 80048327 ps
CPU time 1.7 seconds
Started Mar 14 01:24:09 PM PDT 24
Finished Mar 14 01:24:11 PM PDT 24
Peak memory 196944 kb
Host smart-9ec57fa1-5f39-42a4-8d0e-7022846e3790
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338952973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1338952973
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3298181995
Short name T462
Test name
Test status
Simulation time 108946159 ps
CPU time 3.26 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:13 PM PDT 24
Peak memory 196044 kb
Host smart-fa1afa1f-be87-4ae7-9e68-93a09f3ea88b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298181995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3298181995
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.342634951
Short name T564
Test name
Test status
Simulation time 162711395 ps
CPU time 0.69 seconds
Started Mar 14 01:24:15 PM PDT 24
Finished Mar 14 01:24:16 PM PDT 24
Peak memory 195260 kb
Host smart-a4bb5532-2ee6-4f30-8959-cf18d59a5fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342634951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.342634951
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1424146623
Short name T709
Test name
Test status
Simulation time 20843826 ps
CPU time 0.71 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 195260 kb
Host smart-ee259e04-f6ca-49e3-ad3c-36ca0de9f176
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424146623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1424146623
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3879369518
Short name T518
Test name
Test status
Simulation time 47710657 ps
CPU time 1.73 seconds
Started Mar 14 01:24:17 PM PDT 24
Finished Mar 14 01:24:19 PM PDT 24
Peak memory 198284 kb
Host smart-e4474a66-7e4f-436d-8360-a055ad6e7bbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879369518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3879369518
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1724774974
Short name T335
Test name
Test status
Simulation time 69025167 ps
CPU time 0.77 seconds
Started Mar 14 01:24:13 PM PDT 24
Finished Mar 14 01:24:14 PM PDT 24
Peak memory 195472 kb
Host smart-3d49c8d0-bff7-481a-9327-9f3c7bd48604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724774974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1724774974
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.4187435882
Short name T549
Test name
Test status
Simulation time 595209825 ps
CPU time 1.15 seconds
Started Mar 14 01:24:13 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 195856 kb
Host smart-662a73b9-849a-4281-b126-18d29eed23ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187435882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.4187435882
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3910364586
Short name T442
Test name
Test status
Simulation time 5719400910 ps
CPU time 155.82 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:26:46 PM PDT 24
Peak memory 198444 kb
Host smart-07b52bee-fada-4726-926f-c6e51fcfdbbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910364586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3910364586
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.188405965
Short name T684
Test name
Test status
Simulation time 13823170 ps
CPU time 0.59 seconds
Started Mar 14 01:24:13 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 195896 kb
Host smart-e6b94e18-8215-4c14-8cc8-a545708278c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188405965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.188405965
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1714995800
Short name T24
Test name
Test status
Simulation time 53132150 ps
CPU time 0.65 seconds
Started Mar 14 01:24:14 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 194116 kb
Host smart-a38bf456-4272-4a7d-9150-8650beb31109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714995800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1714995800
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1114231859
Short name T395
Test name
Test status
Simulation time 16084358786 ps
CPU time 26.76 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:39 PM PDT 24
Peak memory 196904 kb
Host smart-03c87167-13c5-4977-8cc3-008bb4d8c751
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114231859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1114231859
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1528114016
Short name T714
Test name
Test status
Simulation time 49446272 ps
CPU time 0.77 seconds
Started Mar 14 01:24:15 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 196760 kb
Host smart-98a81c2d-3f8c-4eb4-9178-99d533f4c560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528114016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1528114016
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.187556441
Short name T434
Test name
Test status
Simulation time 150764332 ps
CPU time 1.46 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 198392 kb
Host smart-e995fc58-f554-42d0-afe6-04fe6083a9df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187556441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.187556441
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2363882273
Short name T569
Test name
Test status
Simulation time 313885764 ps
CPU time 3.32 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:13 PM PDT 24
Peak memory 198488 kb
Host smart-b992d9b0-9870-4355-8639-251cd167e34d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363882273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2363882273
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2116995617
Short name T201
Test name
Test status
Simulation time 248852917 ps
CPU time 3.81 seconds
Started Mar 14 01:24:13 PM PDT 24
Finished Mar 14 01:24:18 PM PDT 24
Peak memory 198368 kb
Host smart-df27629d-1f4b-41b2-9b26-4f699c06b7ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116995617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2116995617
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.270233351
Short name T213
Test name
Test status
Simulation time 104368673 ps
CPU time 1.16 seconds
Started Mar 14 01:24:13 PM PDT 24
Finished Mar 14 01:24:15 PM PDT 24
Peak memory 196036 kb
Host smart-980ce8cb-bada-4edc-a99f-49c1e706343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270233351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.270233351
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.482951250
Short name T342
Test name
Test status
Simulation time 29383300 ps
CPU time 1.08 seconds
Started Mar 14 01:24:14 PM PDT 24
Finished Mar 14 01:24:16 PM PDT 24
Peak memory 196864 kb
Host smart-0d5c66db-3cb9-4888-ae83-043e9b2f7bf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482951250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.482951250
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.134529603
Short name T716
Test name
Test status
Simulation time 1093682869 ps
CPU time 4.79 seconds
Started Mar 14 01:24:13 PM PDT 24
Finished Mar 14 01:24:18 PM PDT 24
Peak memory 198376 kb
Host smart-6f5e36c0-b106-44d6-ae10-b9c74ed5215e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134529603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.134529603
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2282497412
Short name T653
Test name
Test status
Simulation time 61016847 ps
CPU time 1.21 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:24:13 PM PDT 24
Peak memory 196884 kb
Host smart-86eef3f5-6823-4240-aa6c-190fefbf95a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282497412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2282497412
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2399847133
Short name T293
Test name
Test status
Simulation time 28325794 ps
CPU time 0.99 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:11 PM PDT 24
Peak memory 196704 kb
Host smart-aa1e54a2-110b-4b88-923e-198ff548ad01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399847133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2399847133
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3188976671
Short name T473
Test name
Test status
Simulation time 2766090210 ps
CPU time 39.95 seconds
Started Mar 14 01:24:13 PM PDT 24
Finished Mar 14 01:24:53 PM PDT 24
Peak memory 198456 kb
Host smart-b80c4a29-04fd-488e-ab6b-8f9a3b114b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188976671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3188976671
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2537525248
Short name T426
Test name
Test status
Simulation time 100898779827 ps
CPU time 706.05 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:35:56 PM PDT 24
Peak memory 198564 kb
Host smart-8147661d-a735-4b99-8e7a-1e7df912dd56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2537525248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2537525248
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3997971347
Short name T638
Test name
Test status
Simulation time 82882942 ps
CPU time 0.61 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:24:13 PM PDT 24
Peak memory 194140 kb
Host smart-4ef8015c-c786-4151-8052-15667f7790fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997971347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3997971347
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2145289413
Short name T188
Test name
Test status
Simulation time 63549143 ps
CPU time 0.86 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 195656 kb
Host smart-bcbfa808-f4d9-4045-a633-c61c1a6eec8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145289413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2145289413
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1205452167
Short name T700
Test name
Test status
Simulation time 1606890192 ps
CPU time 28.05 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:39 PM PDT 24
Peak memory 195900 kb
Host smart-0404bd4f-0b89-4fb1-aa4d-7387c21f5f11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205452167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1205452167
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1017233384
Short name T673
Test name
Test status
Simulation time 118282939 ps
CPU time 0.76 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:10 PM PDT 24
Peak memory 196808 kb
Host smart-4341105b-a0cd-4a5f-8455-56f72174f37d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017233384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1017233384
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3774289724
Short name T282
Test name
Test status
Simulation time 183139266 ps
CPU time 1.38 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:24:13 PM PDT 24
Peak memory 198440 kb
Host smart-bbd5a50e-590c-41e9-80d7-6e4cde2e39ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774289724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3774289724
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1257409827
Short name T537
Test name
Test status
Simulation time 116499675 ps
CPU time 1.52 seconds
Started Mar 14 01:24:17 PM PDT 24
Finished Mar 14 01:24:18 PM PDT 24
Peak memory 198356 kb
Host smart-860f8ce8-bfd4-4302-850e-a9f9861a8662
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257409827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1257409827
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2317420594
Short name T440
Test name
Test status
Simulation time 100445271 ps
CPU time 1.2 seconds
Started Mar 14 01:24:15 PM PDT 24
Finished Mar 14 01:24:17 PM PDT 24
Peak memory 197552 kb
Host smart-2d097a47-c9d2-4e18-bc4b-3b17db9112d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317420594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2317420594
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.806457616
Short name T44
Test name
Test status
Simulation time 21674590 ps
CPU time 0.64 seconds
Started Mar 14 01:24:15 PM PDT 24
Finished Mar 14 01:24:16 PM PDT 24
Peak memory 195292 kb
Host smart-8334e4b3-1861-4b49-844a-9dfcd4c3f14d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806457616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.806457616
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1526228623
Short name T706
Test name
Test status
Simulation time 132114826 ps
CPU time 2.15 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:14 PM PDT 24
Peak memory 198076 kb
Host smart-1bd9ac4c-5e20-41a2-b1c9-54a0e3c030cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526228623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1526228623
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.998898606
Short name T417
Test name
Test status
Simulation time 93589965 ps
CPU time 1.39 seconds
Started Mar 14 01:24:10 PM PDT 24
Finished Mar 14 01:24:11 PM PDT 24
Peak memory 196620 kb
Host smart-83ba1a71-5bf7-4f88-9914-9a7706411825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998898606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.998898606
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2674694682
Short name T576
Test name
Test status
Simulation time 79933989 ps
CPU time 1.2 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 196232 kb
Host smart-e847537a-54c6-466e-b799-037c08a8a00b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674694682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2674694682
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3890003996
Short name T528
Test name
Test status
Simulation time 29230377580 ps
CPU time 191.03 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:27:23 PM PDT 24
Peak memory 198324 kb
Host smart-27c5615b-16f9-449b-af57-734a4acf6bf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890003996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3890003996
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1410309896
Short name T387
Test name
Test status
Simulation time 49995704 ps
CPU time 0.57 seconds
Started Mar 14 01:24:08 PM PDT 24
Finished Mar 14 01:24:09 PM PDT 24
Peak memory 194076 kb
Host smart-bf7231b3-ccac-4f3f-8292-9cf71bea4ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410309896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1410309896
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1377053266
Short name T477
Test name
Test status
Simulation time 202074468 ps
CPU time 0.98 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 196036 kb
Host smart-5ce4e08b-28ec-477a-93a9-b7fc227fc68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377053266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1377053266
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1764569010
Short name T420
Test name
Test status
Simulation time 207965258 ps
CPU time 6.51 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 01:24:17 PM PDT 24
Peak memory 198328 kb
Host smart-7faaa237-b7e6-4e18-97b7-61ed79fb658d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764569010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1764569010
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2414052395
Short name T357
Test name
Test status
Simulation time 218877028 ps
CPU time 1.25 seconds
Started Mar 14 01:24:17 PM PDT 24
Finished Mar 14 01:24:19 PM PDT 24
Peak memory 196132 kb
Host smart-1ca6f906-8e6e-454b-9341-b69e900144a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414052395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2414052395
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.240690186
Short name T386
Test name
Test status
Simulation time 350447695 ps
CPU time 3.06 seconds
Started Mar 14 01:24:17 PM PDT 24
Finished Mar 14 01:24:21 PM PDT 24
Peak memory 198404 kb
Host smart-ecbb44ed-ef4b-4ace-9d5c-86546b8b7777
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240690186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.240690186
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1680946498
Short name T371
Test name
Test status
Simulation time 24480858 ps
CPU time 0.91 seconds
Started Mar 14 01:24:12 PM PDT 24
Finished Mar 14 01:24:13 PM PDT 24
Peak memory 194732 kb
Host smart-b7f02b87-ca05-46da-9ad1-f56268906f0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680946498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1680946498
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4054510497
Short name T449
Test name
Test status
Simulation time 66685583 ps
CPU time 0.7 seconds
Started Mar 14 01:24:09 PM PDT 24
Finished Mar 14 01:24:10 PM PDT 24
Peak memory 195364 kb
Host smart-7b273839-1b38-4dcb-80fb-7a203923d45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054510497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4054510497
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2295461816
Short name T409
Test name
Test status
Simulation time 29009485 ps
CPU time 0.76 seconds
Started Mar 14 01:24:08 PM PDT 24
Finished Mar 14 01:24:09 PM PDT 24
Peak memory 195596 kb
Host smart-98f19771-263f-4750-8b93-2d71c6b454c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295461816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2295461816
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3348795967
Short name T715
Test name
Test status
Simulation time 793286872 ps
CPU time 2.93 seconds
Started Mar 14 01:24:09 PM PDT 24
Finished Mar 14 01:24:12 PM PDT 24
Peak memory 198308 kb
Host smart-74d408ae-774f-442d-8670-9e69249f2c2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348795967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3348795967
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1536730441
Short name T464
Test name
Test status
Simulation time 359324725 ps
CPU time 1.44 seconds
Started Mar 14 01:24:08 PM PDT 24
Finished Mar 14 01:24:09 PM PDT 24
Peak memory 195900 kb
Host smart-5fec523f-6d63-4068-8414-24d1b9e72f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536730441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1536730441
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.317611065
Short name T606
Test name
Test status
Simulation time 63976385 ps
CPU time 1.28 seconds
Started Mar 14 01:24:13 PM PDT 24
Finished Mar 14 01:24:14 PM PDT 24
Peak memory 197136 kb
Host smart-b005a4b1-d832-4de3-a5d0-f417976ee466
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317611065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.317611065
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3498363212
Short name T628
Test name
Test status
Simulation time 34550943639 ps
CPU time 104.8 seconds
Started Mar 14 01:24:17 PM PDT 24
Finished Mar 14 01:26:02 PM PDT 24
Peak memory 198432 kb
Host smart-ae6d7a55-84c7-453d-9e7e-db3a90a8027a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498363212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3498363212
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2719769948
Short name T696
Test name
Test status
Simulation time 330908156654 ps
CPU time 2264.43 seconds
Started Mar 14 01:24:11 PM PDT 24
Finished Mar 14 02:01:56 PM PDT 24
Peak memory 198424 kb
Host smart-34491660-e48c-41fb-936e-fa2010e98372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2719769948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2719769948
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.801346424
Short name T582
Test name
Test status
Simulation time 13506434 ps
CPU time 0.58 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 194140 kb
Host smart-8348179b-6354-4ea4-bc91-e957e9735d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801346424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.801346424
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.200585205
Short name T198
Test name
Test status
Simulation time 15108400 ps
CPU time 0.68 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:23 PM PDT 24
Peak memory 195108 kb
Host smart-1e16e331-9c45-4e28-a909-d803be4d1c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200585205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.200585205
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2915078916
Short name T517
Test name
Test status
Simulation time 3015561401 ps
CPU time 27.08 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:54 PM PDT 24
Peak memory 196944 kb
Host smart-f32c2f26-a853-4f18-a96c-23f82a11904d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915078916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2915078916
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.238578272
Short name T678
Test name
Test status
Simulation time 112985167 ps
CPU time 0.96 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 197380 kb
Host smart-76696474-4997-4a94-b864-947284503388
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238578272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.238578272
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.562875753
Short name T275
Test name
Test status
Simulation time 123120784 ps
CPU time 0.98 seconds
Started Mar 14 01:24:20 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 196260 kb
Host smart-b967abc8-72a4-44a5-bf35-15e29ffd6224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562875753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.562875753
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1368431271
Short name T415
Test name
Test status
Simulation time 67667384 ps
CPU time 2.86 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:24:24 PM PDT 24
Peak memory 198360 kb
Host smart-bbdba3d0-b980-4c49-ba7b-f5823fd9b8ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368431271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1368431271
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1934713869
Short name T604
Test name
Test status
Simulation time 772449741 ps
CPU time 3.52 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:26 PM PDT 24
Peak memory 198372 kb
Host smart-fc5f551e-8060-49ea-a160-309b16191cb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934713869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1934713869
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3400190085
Short name T285
Test name
Test status
Simulation time 35926382 ps
CPU time 0.89 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 196308 kb
Host smart-097992c3-2fab-44b6-986d-e4e0b4644fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400190085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3400190085
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3614282669
Short name T347
Test name
Test status
Simulation time 53773544 ps
CPU time 1.26 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 197328 kb
Host smart-21d66b04-ff6a-4df7-bb3c-e9340f7acee9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614282669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3614282669
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.22732583
Short name T407
Test name
Test status
Simulation time 343264944 ps
CPU time 3.43 seconds
Started Mar 14 01:24:25 PM PDT 24
Finished Mar 14 01:24:29 PM PDT 24
Peak memory 198316 kb
Host smart-7e03d024-bc2a-46a0-af1a-ad5a9c77ae2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22732583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand
om_long_reg_writes_reg_reads.22732583
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.934234790
Short name T278
Test name
Test status
Simulation time 37694535 ps
CPU time 1.07 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:24 PM PDT 24
Peak memory 196152 kb
Host smart-0b9cbba3-0c84-4c4e-af36-fecaac858f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934234790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.934234790
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1637865185
Short name T679
Test name
Test status
Simulation time 38260106 ps
CPU time 1.05 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 196020 kb
Host smart-4c5dcb43-8f3b-4b3a-8aa5-a46a22b9f8f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637865185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1637865185
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1790863010
Short name T197
Test name
Test status
Simulation time 30433304792 ps
CPU time 61.43 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:25:23 PM PDT 24
Peak memory 198400 kb
Host smart-296bfd09-9713-4118-9a09-b507bd47ef81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790863010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1790863010
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3815588547
Short name T195
Test name
Test status
Simulation time 132391992 ps
CPU time 0.57 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 194964 kb
Host smart-2b06cfe1-8f9b-446c-a081-1d9f8de31671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815588547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3815588547
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3579977751
Short name T78
Test name
Test status
Simulation time 16386812 ps
CPU time 0.62 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 194884 kb
Host smart-97e7a4c0-9874-4481-a002-cd394980d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579977751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3579977751
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2642480811
Short name T532
Test name
Test status
Simulation time 1413264362 ps
CPU time 18.64 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:41 PM PDT 24
Peak memory 198308 kb
Host smart-7535c724-a923-45ab-be2b-ec964be04cc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642480811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2642480811
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3464322752
Short name T425
Test name
Test status
Simulation time 192668892 ps
CPU time 0.88 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:23 PM PDT 24
Peak memory 196364 kb
Host smart-f275c18d-f388-4741-a892-0d174cf0a6dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464322752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3464322752
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2545364887
Short name T618
Test name
Test status
Simulation time 92627273 ps
CPU time 1.2 seconds
Started Mar 14 01:24:20 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 196436 kb
Host smart-14c53cf6-72e4-4a76-9a6a-90ae04bee268
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545364887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2545364887
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.625406287
Short name T184
Test name
Test status
Simulation time 76254465 ps
CPU time 2.96 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:25 PM PDT 24
Peak memory 196852 kb
Host smart-51551881-eefa-46bd-a1e9-bb6ff1d899d1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625406287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.625406287
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3675373062
Short name T664
Test name
Test status
Simulation time 526406489 ps
CPU time 2.06 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:24:23 PM PDT 24
Peak memory 196400 kb
Host smart-6582dc6b-ecb4-4488-909a-83e94d627f7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675373062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3675373062
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1248304346
Short name T180
Test name
Test status
Simulation time 36685691 ps
CPU time 0.81 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 197620 kb
Host smart-62b27e4d-94cf-4bcb-8972-8e9371914486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248304346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1248304346
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1293616745
Short name T509
Test name
Test status
Simulation time 40244038 ps
CPU time 0.7 seconds
Started Mar 14 01:24:24 PM PDT 24
Finished Mar 14 01:24:25 PM PDT 24
Peak memory 195300 kb
Host smart-0e5c8b1a-4d17-4de4-8f86-107b207ed56a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293616745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1293616745
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.196769121
Short name T686
Test name
Test status
Simulation time 1630282064 ps
CPU time 2.11 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 198320 kb
Host smart-213f0a40-f34a-4efb-bc6f-5aef380ec1d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196769121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.196769121
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.51429817
Short name T149
Test name
Test status
Simulation time 486009914 ps
CPU time 1.37 seconds
Started Mar 14 01:24:25 PM PDT 24
Finished Mar 14 01:24:26 PM PDT 24
Peak memory 196572 kb
Host smart-439a5073-9f5a-4eba-9fb5-0f75a17e3b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51429817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.51429817
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1196971263
Short name T147
Test name
Test status
Simulation time 499670117 ps
CPU time 1.5 seconds
Started Mar 14 01:24:24 PM PDT 24
Finished Mar 14 01:24:26 PM PDT 24
Peak memory 197088 kb
Host smart-90182c25-d9d0-411b-a7a6-eb01912ce8a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196971263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1196971263
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3659012275
Short name T490
Test name
Test status
Simulation time 50507515627 ps
CPU time 147.89 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:26:51 PM PDT 24
Peak memory 198492 kb
Host smart-82f2d927-fdc4-454d-b5ee-1b09b7d5c8db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659012275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3659012275
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2464862071
Short name T556
Test name
Test status
Simulation time 72880532 ps
CPU time 0.58 seconds
Started Mar 14 01:24:20 PM PDT 24
Finished Mar 14 01:24:21 PM PDT 24
Peak memory 194116 kb
Host smart-cb519f30-fbc0-497d-9193-f2f9bf72ced9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464862071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2464862071
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.625753490
Short name T611
Test name
Test status
Simulation time 28756107 ps
CPU time 0.81 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 195424 kb
Host smart-a8e04397-4ad8-47a6-96bf-5007a2c45596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625753490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.625753490
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.758730992
Short name T587
Test name
Test status
Simulation time 232421752 ps
CPU time 11.69 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:41 PM PDT 24
Peak memory 198256 kb
Host smart-b17f593f-1474-45e8-be39-3196001b2f6c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758730992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.758730992
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2129395388
Short name T350
Test name
Test status
Simulation time 137588990 ps
CPU time 1 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 198060 kb
Host smart-bad2b0bb-ff17-446b-b19c-6890a4298d8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129395388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2129395388
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1274166844
Short name T545
Test name
Test status
Simulation time 53052006 ps
CPU time 0.98 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:24 PM PDT 24
Peak memory 196836 kb
Host smart-e3c695ea-289a-42b3-9ce2-d62b8d3dc03e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274166844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1274166844
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1605448918
Short name T75
Test name
Test status
Simulation time 285701080 ps
CPU time 3 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:32 PM PDT 24
Peak memory 196824 kb
Host smart-fdbd4edc-4323-402f-918b-07cd498d8386
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605448918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1605448918
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.125990467
Short name T79
Test name
Test status
Simulation time 117406195 ps
CPU time 1.47 seconds
Started Mar 14 01:24:20 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 196996 kb
Host smart-c8493bb1-ffaf-4c25-9636-7afd3fa66e48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125990467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
125990467
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.365572558
Short name T689
Test name
Test status
Simulation time 44642950 ps
CPU time 1.12 seconds
Started Mar 14 01:24:20 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 196116 kb
Host smart-d182a213-2980-4dc5-aff5-207420629a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365572558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.365572558
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3255332015
Short name T13
Test name
Test status
Simulation time 26630472 ps
CPU time 0.79 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 195696 kb
Host smart-ca8ecc98-ef51-4842-9016-4a0d4cb135df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255332015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3255332015
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2443217074
Short name T271
Test name
Test status
Simulation time 1163586149 ps
CPU time 5.47 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:32 PM PDT 24
Peak memory 198316 kb
Host smart-9c85525d-06ff-4d8f-81a1-898376bb9d19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443217074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2443217074
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2933195259
Short name T259
Test name
Test status
Simulation time 35572221 ps
CPU time 1.01 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:23 PM PDT 24
Peak memory 196684 kb
Host smart-50769435-a54f-483c-a0d8-05e6b1d5129f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933195259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2933195259
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.4151612838
Short name T366
Test name
Test status
Simulation time 247526212 ps
CPU time 1.04 seconds
Started Mar 14 01:24:19 PM PDT 24
Finished Mar 14 01:24:20 PM PDT 24
Peak memory 196596 kb
Host smart-007f0719-bf17-407c-9354-6526e1c86bc6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151612838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.4151612838
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.818251711
Short name T219
Test name
Test status
Simulation time 14349605275 ps
CPU time 210.74 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:27:51 PM PDT 24
Peak memory 198444 kb
Host smart-34957c27-7314-4d2e-a58d-360e082be2b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818251711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.818251711
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.562571067
Short name T447
Test name
Test status
Simulation time 27629466 ps
CPU time 0.57 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:22:57 PM PDT 24
Peak memory 194092 kb
Host smart-0b2ba698-4008-4ea1-a7dd-4fc7050b95f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562571067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.562571067
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3351527584
Short name T563
Test name
Test status
Simulation time 200889824 ps
CPU time 0.93 seconds
Started Mar 14 01:22:58 PM PDT 24
Finished Mar 14 01:22:59 PM PDT 24
Peak memory 196468 kb
Host smart-bbf60003-debe-4f17-994d-be1141378441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351527584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3351527584
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3863391460
Short name T687
Test name
Test status
Simulation time 522826951 ps
CPU time 13.49 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:23:10 PM PDT 24
Peak memory 195828 kb
Host smart-565072c6-6136-458e-a8a7-8ef396ba7a5f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863391460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3863391460
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4015250800
Short name T341
Test name
Test status
Simulation time 389067127 ps
CPU time 1.09 seconds
Started Mar 14 01:22:58 PM PDT 24
Finished Mar 14 01:22:59 PM PDT 24
Peak memory 197000 kb
Host smart-b59c8132-7818-4b60-9d55-886ddce25a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015250800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4015250800
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.701409656
Short name T489
Test name
Test status
Simulation time 98862136 ps
CPU time 0.73 seconds
Started Mar 14 01:22:59 PM PDT 24
Finished Mar 14 01:23:01 PM PDT 24
Peak memory 194660 kb
Host smart-28716e7c-09ed-4b05-83b1-d09c04b497ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701409656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.701409656
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3244934782
Short name T588
Test name
Test status
Simulation time 1757700520 ps
CPU time 3.72 seconds
Started Mar 14 01:22:58 PM PDT 24
Finished Mar 14 01:23:02 PM PDT 24
Peak memory 198476 kb
Host smart-923e9c89-c733-4aea-8eca-bca0667c3089
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244934782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3244934782
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.780501043
Short name T40
Test name
Test status
Simulation time 102546803 ps
CPU time 1.32 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:22:58 PM PDT 24
Peak memory 197852 kb
Host smart-ed5b4404-debf-4b1c-9090-9ce791e7821f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780501043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.780501043
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2510713557
Short name T583
Test name
Test status
Simulation time 52853337 ps
CPU time 1.27 seconds
Started Mar 14 01:22:59 PM PDT 24
Finished Mar 14 01:23:01 PM PDT 24
Peak memory 197232 kb
Host smart-0d15471c-69e3-4180-9480-927cb1b5c630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510713557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2510713557
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2451217963
Short name T507
Test name
Test status
Simulation time 186508403 ps
CPU time 1.13 seconds
Started Mar 14 01:23:01 PM PDT 24
Finished Mar 14 01:23:03 PM PDT 24
Peak memory 197168 kb
Host smart-897a4837-cb3c-46f9-a54b-43d985aa78bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451217963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2451217963
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.22934168
Short name T205
Test name
Test status
Simulation time 97311847 ps
CPU time 4.22 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:23:01 PM PDT 24
Peak memory 198312 kb
Host smart-35a8bc77-e452-47bd-8a50-51a2827a4293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22934168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rando
m_long_reg_writes_reg_reads.22934168
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1337216028
Short name T42
Test name
Test status
Simulation time 305461615 ps
CPU time 0.93 seconds
Started Mar 14 01:22:54 PM PDT 24
Finished Mar 14 01:22:55 PM PDT 24
Peak memory 214712 kb
Host smart-3f3598ab-0ee9-4a1e-8d6f-d1c4496e1e56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337216028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1337216028
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1435749448
Short name T441
Test name
Test status
Simulation time 64361344 ps
CPU time 1.11 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:22:58 PM PDT 24
Peak memory 195760 kb
Host smart-0504eef5-f856-4885-a719-803954b1e6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435749448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1435749448
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.338613259
Short name T187
Test name
Test status
Simulation time 28751542 ps
CPU time 0.83 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:22:57 PM PDT 24
Peak memory 196100 kb
Host smart-2d68da59-e2ff-48f5-95f7-e88935bc67c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338613259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.338613259
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.673753674
Short name T659
Test name
Test status
Simulation time 29078169356 ps
CPU time 139.16 seconds
Started Mar 14 01:22:57 PM PDT 24
Finished Mar 14 01:25:17 PM PDT 24
Peak memory 198372 kb
Host smart-ab86aafe-5733-4a5b-8423-d80fad1354ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673753674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.673753674
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1004645012
Short name T635
Test name
Test status
Simulation time 21708403 ps
CPU time 0.57 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:31 PM PDT 24
Peak memory 194832 kb
Host smart-e3ccbf67-2494-4935-94c8-1ff54e719464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004645012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1004645012
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1485233192
Short name T401
Test name
Test status
Simulation time 58625964 ps
CPU time 0.66 seconds
Started Mar 14 01:24:20 PM PDT 24
Finished Mar 14 01:24:20 PM PDT 24
Peak memory 194604 kb
Host smart-a8cb939c-c902-4cbe-9368-648be2bb66b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485233192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1485233192
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.314150571
Short name T650
Test name
Test status
Simulation time 828739799 ps
CPU time 13.05 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:41 PM PDT 24
Peak memory 196548 kb
Host smart-8ae56410-6749-4d1c-b6ab-ba1d2796fa26
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314150571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.314150571
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3503674571
Short name T74
Test name
Test status
Simulation time 66773524 ps
CPU time 0.96 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 197388 kb
Host smart-5e77caac-d940-4683-ab5c-ba9ba93f0ac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503674571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3503674571
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.124633003
Short name T584
Test name
Test status
Simulation time 37689552 ps
CPU time 1.21 seconds
Started Mar 14 01:24:20 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 197172 kb
Host smart-a943a676-ed5c-4443-84ae-29279ab079f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124633003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.124633003
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.575754689
Short name T250
Test name
Test status
Simulation time 235904947 ps
CPU time 2.05 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 198376 kb
Host smart-6765f6c6-fbf8-4884-9bb8-dc3391a6181c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575754689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.575754689
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3508474811
Short name T488
Test name
Test status
Simulation time 154035130 ps
CPU time 1.17 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 196072 kb
Host smart-f2cff901-f8d8-4489-b6ec-741201c0ebf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508474811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3508474811
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2322096290
Short name T295
Test name
Test status
Simulation time 36950648 ps
CPU time 1.29 seconds
Started Mar 14 01:24:29 PM PDT 24
Finished Mar 14 01:24:31 PM PDT 24
Peak memory 196868 kb
Host smart-6775b397-900a-4d6b-a3e5-fbd217bf951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322096290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2322096290
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4067695862
Short name T66
Test name
Test status
Simulation time 31951054 ps
CPU time 0.84 seconds
Started Mar 14 01:24:20 PM PDT 24
Finished Mar 14 01:24:21 PM PDT 24
Peak memory 195864 kb
Host smart-f73766e3-af83-4f56-b16d-2af03026a1d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067695862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4067695862
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.4094098563
Short name T329
Test name
Test status
Simulation time 751094913 ps
CPU time 3.46 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:32 PM PDT 24
Peak memory 198308 kb
Host smart-21fd7db5-912a-4d11-94ca-95d4e5ef4f94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094098563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.4094098563
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2357788874
Short name T669
Test name
Test status
Simulation time 67355306 ps
CPU time 1.04 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 196028 kb
Host smart-18b40e03-0767-4d9e-9483-c1c12a2e2dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357788874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2357788874
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3433667663
Short name T663
Test name
Test status
Simulation time 144219104 ps
CPU time 1.24 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 196112 kb
Host smart-3f1a2764-e300-4406-a812-7aae8ef55469
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433667663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3433667663
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2350043695
Short name T614
Test name
Test status
Simulation time 28425115167 ps
CPU time 76.6 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:25:44 PM PDT 24
Peak memory 198456 kb
Host smart-5f03917c-57d4-4dc9-87d1-5f7bf4551168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350043695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2350043695
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1527332298
Short name T718
Test name
Test status
Simulation time 23886203 ps
CPU time 0.6 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:24:23 PM PDT 24
Peak memory 194044 kb
Host smart-087b9fcb-801e-4856-bd38-c17b6a2431a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527332298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1527332298
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1155508071
Short name T567
Test name
Test status
Simulation time 145597730 ps
CPU time 0.82 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:30 PM PDT 24
Peak memory 195568 kb
Host smart-6100fb58-6d31-42a1-b48d-0202c658a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155508071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1155508071
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2334037397
Short name T229
Test name
Test status
Simulation time 1894162959 ps
CPU time 27.33 seconds
Started Mar 14 01:24:20 PM PDT 24
Finished Mar 14 01:24:48 PM PDT 24
Peak memory 197256 kb
Host smart-a42915b0-3a4f-4c19-aacb-cf50a5b22359
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334037397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2334037397
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2674277833
Short name T644
Test name
Test status
Simulation time 77669124 ps
CPU time 0.93 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:24 PM PDT 24
Peak memory 196376 kb
Host smart-db318a58-501b-492f-889a-6de38790f8df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674277833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2674277833
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.702141744
Short name T240
Test name
Test status
Simulation time 41463127 ps
CPU time 1.16 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 196512 kb
Host smart-80f40230-ce12-4365-80df-8777f1ec0173
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702141744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.702141744
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.4208582866
Short name T142
Test name
Test status
Simulation time 59468960 ps
CPU time 0.9 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 196488 kb
Host smart-f80aaa87-8d67-4013-a73a-978bc1efe716
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208582866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.4208582866
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.386449163
Short name T225
Test name
Test status
Simulation time 327669450 ps
CPU time 3.58 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:33 PM PDT 24
Peak memory 198344 kb
Host smart-ad3d7736-61b2-45b3-8c9a-cb00026ab505
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386449163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
386449163
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3059145361
Short name T328
Test name
Test status
Simulation time 39729479 ps
CPU time 0.89 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:29 PM PDT 24
Peak memory 196308 kb
Host smart-4fb39eb0-c0de-4bbf-8d03-2ac8b6b5a0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059145361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3059145361
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.627315853
Short name T332
Test name
Test status
Simulation time 161497158 ps
CPU time 0.92 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:29 PM PDT 24
Peak memory 196200 kb
Host smart-6d4e54a4-bee4-4060-aca7-e7be98f27eda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627315853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.627315853
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2444196350
Short name T392
Test name
Test status
Simulation time 140640057 ps
CPU time 3.32 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:30 PM PDT 24
Peak memory 198340 kb
Host smart-4c895647-53ba-41ea-808f-0d9b08fcf38f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444196350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2444196350
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1226423708
Short name T269
Test name
Test status
Simulation time 49016328 ps
CPU time 0.85 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 196368 kb
Host smart-6a1095b8-9882-4e41-bb06-c274b5db5870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226423708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1226423708
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1073504203
Short name T694
Test name
Test status
Simulation time 69021965 ps
CPU time 1.01 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:30 PM PDT 24
Peak memory 196088 kb
Host smart-ee97a6fe-8b8b-4905-891b-02760fcf6f40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073504203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1073504203
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.557590032
Short name T548
Test name
Test status
Simulation time 39983301878 ps
CPU time 20.72 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:24:44 PM PDT 24
Peak memory 198492 kb
Host smart-3606ce8a-eb1b-4255-b2dd-54cf06caceb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557590032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.557590032
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.350300831
Short name T199
Test name
Test status
Simulation time 23228174 ps
CPU time 0.59 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 194172 kb
Host smart-66b42d98-7159-4eb3-aefb-7544f8777f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350300831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.350300831
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1450124835
Short name T573
Test name
Test status
Simulation time 90932042 ps
CPU time 0.79 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 196364 kb
Host smart-4901dfbc-ac78-4940-85ad-e89a4401a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450124835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1450124835
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1458454582
Short name T608
Test name
Test status
Simulation time 893729614 ps
CPU time 24.82 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:24:48 PM PDT 24
Peak memory 197096 kb
Host smart-28569950-833a-4094-8a9c-79a31837ba11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458454582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1458454582
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1004303624
Short name T346
Test name
Test status
Simulation time 136417448 ps
CPU time 0.76 seconds
Started Mar 14 01:24:24 PM PDT 24
Finished Mar 14 01:24:25 PM PDT 24
Peak memory 195088 kb
Host smart-1782c254-4d6c-4c02-a04f-1e4cc0b968f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004303624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1004303624
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3534542464
Short name T675
Test name
Test status
Simulation time 24295375 ps
CPU time 0.71 seconds
Started Mar 14 01:24:21 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 195224 kb
Host smart-fb7ee367-40d1-4694-a255-50ed0187733c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534542464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3534542464
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2814289832
Short name T348
Test name
Test status
Simulation time 104908347 ps
CPU time 1.33 seconds
Started Mar 14 01:24:24 PM PDT 24
Finished Mar 14 01:24:26 PM PDT 24
Peak memory 197080 kb
Host smart-80a5eebc-3f40-4a19-9fb3-94be1609db0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814289832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2814289832
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2722138917
Short name T337
Test name
Test status
Simulation time 95302847 ps
CPU time 2.13 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:24:26 PM PDT 24
Peak memory 196596 kb
Host smart-6ef68339-a164-4625-8f7c-844efc3c0f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722138917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2722138917
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1441986979
Short name T238
Test name
Test status
Simulation time 467043138 ps
CPU time 1.21 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:24:24 PM PDT 24
Peak memory 196224 kb
Host smart-2ee51ab6-1c9c-4b88-8ada-0a9df73642fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441986979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1441986979
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3035995379
Short name T243
Test name
Test status
Simulation time 102107805 ps
CPU time 1.08 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 196400 kb
Host smart-45e7bd78-9c45-4668-8412-eef5f15f3c38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035995379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3035995379
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3975387359
Short name T592
Test name
Test status
Simulation time 29412270 ps
CPU time 1.22 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:24 PM PDT 24
Peak memory 197960 kb
Host smart-326208f3-5cd0-42b4-a304-482fd6a59b66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975387359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3975387359
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2825222388
Short name T615
Test name
Test status
Simulation time 262028514 ps
CPU time 1.28 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:24 PM PDT 24
Peak memory 196064 kb
Host smart-8aa9a016-f098-446e-87e1-59bea077464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825222388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2825222388
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1570505030
Short name T666
Test name
Test status
Simulation time 441672243 ps
CPU time 1.38 seconds
Started Mar 14 01:24:26 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 195904 kb
Host smart-5fcabc07-bfd0-4fca-9d15-e74a55fd93d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570505030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1570505030
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.275090659
Short name T443
Test name
Test status
Simulation time 86733961159 ps
CPU time 245.38 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:28:28 PM PDT 24
Peak memory 198392 kb
Host smart-19486ef1-32d0-4beb-aedf-9d7880c162ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275090659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.275090659
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2882151638
Short name T351
Test name
Test status
Simulation time 14515950 ps
CPU time 0.63 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:24:24 PM PDT 24
Peak memory 194360 kb
Host smart-4ceafa81-189e-4889-8f08-d88dd8980716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882151638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2882151638
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2819934925
Short name T235
Test name
Test status
Simulation time 39863439 ps
CPU time 0.6 seconds
Started Mar 14 01:24:25 PM PDT 24
Finished Mar 14 01:24:26 PM PDT 24
Peak memory 194864 kb
Host smart-368ef70f-1376-4c5b-9ece-93ef06fab00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819934925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2819934925
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.22662025
Short name T497
Test name
Test status
Simulation time 213580633 ps
CPU time 11.7 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:24:34 PM PDT 24
Peak memory 197260 kb
Host smart-3506391e-b901-4d30-bd56-4cd215e8ca00
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22662025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stress
.22662025
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.541035569
Short name T291
Test name
Test status
Simulation time 37392956 ps
CPU time 0.73 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 194928 kb
Host smart-87531d30-ba34-4d16-9858-092a8f0b0576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541035569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.541035569
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3350584074
Short name T506
Test name
Test status
Simulation time 423895730 ps
CPU time 1.53 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:24:24 PM PDT 24
Peak memory 198352 kb
Host smart-de1506de-554c-4245-bd2d-69528db606ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350584074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3350584074
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.186156556
Short name T228
Test name
Test status
Simulation time 233971356 ps
CPU time 2.35 seconds
Started Mar 14 01:24:24 PM PDT 24
Finished Mar 14 01:24:27 PM PDT 24
Peak memory 198268 kb
Host smart-e7b5ccaa-b212-44e6-9c89-086f90ab7724
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186156556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.186156556
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3934820574
Short name T438
Test name
Test status
Simulation time 161967767 ps
CPU time 3.49 seconds
Started Mar 14 01:24:22 PM PDT 24
Finished Mar 14 01:24:26 PM PDT 24
Peak memory 197492 kb
Host smart-6bf2d9dd-faee-41e4-9682-2e2df43a711d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934820574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3934820574
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2027229998
Short name T620
Test name
Test status
Simulation time 40340213 ps
CPU time 1.27 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 197268 kb
Host smart-0b335732-940e-4626-bf91-540f9a062ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027229998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2027229998
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2708454837
Short name T263
Test name
Test status
Simulation time 215386693 ps
CPU time 1.07 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:31 PM PDT 24
Peak memory 196212 kb
Host smart-18771e43-ee36-4d0a-8d26-32d3db4baa9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708454837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2708454837
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3202612139
Short name T368
Test name
Test status
Simulation time 167267977 ps
CPU time 4.08 seconds
Started Mar 14 01:24:33 PM PDT 24
Finished Mar 14 01:24:37 PM PDT 24
Peak memory 198264 kb
Host smart-26af17e0-d4de-4b42-aaf8-d947f4f7570f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202612139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3202612139
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.4126046209
Short name T129
Test name
Test status
Simulation time 91775995 ps
CPU time 1.31 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 197192 kb
Host smart-7202dfbd-d54b-4607-a661-d640c6e34abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126046209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.4126046209
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2923706918
Short name T431
Test name
Test status
Simulation time 48933531 ps
CPU time 1.23 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:24:25 PM PDT 24
Peak memory 195876 kb
Host smart-92117c1e-24ff-4ee6-a771-b486fc9e82bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923706918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2923706918
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2144114839
Short name T113
Test name
Test status
Simulation time 4236101215 ps
CPU time 53.84 seconds
Started Mar 14 01:24:23 PM PDT 24
Finished Mar 14 01:25:17 PM PDT 24
Peak memory 198428 kb
Host smart-0a966399-0056-424f-a97b-01e553b1c816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144114839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2144114839
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1184846407
Short name T577
Test name
Test status
Simulation time 50437999 ps
CPU time 0.56 seconds
Started Mar 14 01:24:40 PM PDT 24
Finished Mar 14 01:24:41 PM PDT 24
Peak memory 194216 kb
Host smart-9fd8505b-e226-4a2f-acaf-aa5990e220c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184846407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1184846407
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.195648121
Short name T363
Test name
Test status
Simulation time 81842152 ps
CPU time 0.73 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:30 PM PDT 24
Peak memory 195436 kb
Host smart-06ff1566-6e74-4253-85d2-3ab44004e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195648121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.195648121
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3791308042
Short name T551
Test name
Test status
Simulation time 845317058 ps
CPU time 22.24 seconds
Started Mar 14 01:24:33 PM PDT 24
Finished Mar 14 01:24:56 PM PDT 24
Peak memory 197048 kb
Host smart-daca79dd-5d63-4144-a9c9-ecd0e573e93e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791308042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3791308042
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.783030850
Short name T1
Test name
Test status
Simulation time 119518422 ps
CPU time 0.86 seconds
Started Mar 14 01:24:37 PM PDT 24
Finished Mar 14 01:24:38 PM PDT 24
Peak memory 196156 kb
Host smart-354899ed-8265-4aac-a2ec-bd0329b9cafe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783030850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.783030850
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1658277331
Short name T504
Test name
Test status
Simulation time 29017079 ps
CPU time 0.77 seconds
Started Mar 14 01:24:33 PM PDT 24
Finished Mar 14 01:24:34 PM PDT 24
Peak memory 195636 kb
Host smart-c882e554-1b69-4817-8ba7-488085c77d0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658277331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1658277331
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.869783716
Short name T437
Test name
Test status
Simulation time 72116172 ps
CPU time 3.14 seconds
Started Mar 14 01:24:34 PM PDT 24
Finished Mar 14 01:24:38 PM PDT 24
Peak memory 198524 kb
Host smart-627d2079-86d9-4854-888b-739cce849075
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869783716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.869783716
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3687648657
Short name T396
Test name
Test status
Simulation time 1058223445 ps
CPU time 2.96 seconds
Started Mar 14 01:24:33 PM PDT 24
Finished Mar 14 01:24:37 PM PDT 24
Peak memory 197508 kb
Host smart-be531903-9c4b-412c-9092-6aab554055c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687648657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3687648657
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2314642727
Short name T388
Test name
Test status
Simulation time 286571671 ps
CPU time 1.35 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:28 PM PDT 24
Peak memory 197336 kb
Host smart-614f5cb7-6ab3-46a3-8498-07de80f97293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314642727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2314642727
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.741574058
Short name T657
Test name
Test status
Simulation time 143605579 ps
CPU time 0.95 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:30 PM PDT 24
Peak memory 196384 kb
Host smart-9e0e0536-9c47-449a-8cf7-49fa0dbe6bd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741574058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.741574058
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.401318664
Short name T237
Test name
Test status
Simulation time 338958010 ps
CPU time 4.11 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:39 PM PDT 24
Peak memory 198332 kb
Host smart-2019fd95-359b-42c5-858a-402f41de456c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401318664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.401318664
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3216616809
Short name T681
Test name
Test status
Simulation time 193032686 ps
CPU time 1.08 seconds
Started Mar 14 01:24:28 PM PDT 24
Finished Mar 14 01:24:30 PM PDT 24
Peak memory 195952 kb
Host smart-31217845-cb87-490b-a392-6b21b056a0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216616809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3216616809
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.4264596992
Short name T309
Test name
Test status
Simulation time 142236194 ps
CPU time 0.9 seconds
Started Mar 14 01:24:27 PM PDT 24
Finished Mar 14 01:24:29 PM PDT 24
Peak memory 196760 kb
Host smart-4d8d1279-5c71-4f4f-83fd-b7c86a9d4e4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264596992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.4264596992
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1610220460
Short name T265
Test name
Test status
Simulation time 5756822507 ps
CPU time 72.76 seconds
Started Mar 14 01:24:38 PM PDT 24
Finished Mar 14 01:25:51 PM PDT 24
Peak memory 198424 kb
Host smart-dccb1193-1727-482c-bf96-ba245663f897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610220460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1610220460
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1883352817
Short name T698
Test name
Test status
Simulation time 19469180 ps
CPU time 0.64 seconds
Started Mar 14 01:24:37 PM PDT 24
Finished Mar 14 01:24:37 PM PDT 24
Peak memory 194868 kb
Host smart-9861141f-340b-49f3-b67c-eec4dd865288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883352817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1883352817
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.867740387
Short name T639
Test name
Test status
Simulation time 26894312 ps
CPU time 1.06 seconds
Started Mar 14 01:24:34 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 196764 kb
Host smart-95251d4e-cb03-4e16-bb43-91ac7487a191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867740387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.867740387
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.923651817
Short name T690
Test name
Test status
Simulation time 466477141 ps
CPU time 24.34 seconds
Started Mar 14 01:24:38 PM PDT 24
Finished Mar 14 01:25:03 PM PDT 24
Peak memory 197064 kb
Host smart-ba9abd46-a90e-405b-a805-cfe2e75740b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923651817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.923651817
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.4092807679
Short name T163
Test name
Test status
Simulation time 50008661 ps
CPU time 0.84 seconds
Started Mar 14 01:24:36 PM PDT 24
Finished Mar 14 01:24:37 PM PDT 24
Peak memory 196088 kb
Host smart-483a06ca-24a4-49b6-8a19-1a8690e21f28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092807679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.4092807679
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1392243147
Short name T29
Test name
Test status
Simulation time 205628843 ps
CPU time 1.43 seconds
Started Mar 14 01:24:33 PM PDT 24
Finished Mar 14 01:24:35 PM PDT 24
Peak memory 197244 kb
Host smart-2ba59d3d-fba2-4e85-a00c-57f8d7055466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392243147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1392243147
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.695020959
Short name T165
Test name
Test status
Simulation time 71512104 ps
CPU time 2.8 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:38 PM PDT 24
Peak memory 196812 kb
Host smart-b8bfd96b-8563-41a2-98a0-861f79f0a0e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695020959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.695020959
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3810717051
Short name T211
Test name
Test status
Simulation time 333671198 ps
CPU time 2.71 seconds
Started Mar 14 01:24:40 PM PDT 24
Finished Mar 14 01:24:43 PM PDT 24
Peak memory 198312 kb
Host smart-65c0f6cf-a230-47f6-927d-e79c452906bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810717051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3810717051
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.609048507
Short name T126
Test name
Test status
Simulation time 506990802 ps
CPU time 1.04 seconds
Started Mar 14 01:24:38 PM PDT 24
Finished Mar 14 01:24:40 PM PDT 24
Peak memory 196396 kb
Host smart-94030362-4b8a-426d-b86b-de3753100cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609048507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.609048507
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1202777115
Short name T516
Test name
Test status
Simulation time 199918450 ps
CPU time 1.08 seconds
Started Mar 14 01:24:34 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 196128 kb
Host smart-68602f6e-1d92-469c-b449-f8c343d4fd97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202777115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1202777115
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1682522985
Short name T703
Test name
Test status
Simulation time 319777268 ps
CPU time 2.89 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:38 PM PDT 24
Peak memory 198348 kb
Host smart-18d65686-5f82-45fe-b97f-b84e1193af55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682522985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1682522985
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1953692861
Short name T546
Test name
Test status
Simulation time 129764142 ps
CPU time 1.31 seconds
Started Mar 14 01:24:34 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 196536 kb
Host smart-15ad62d6-7958-47b1-9351-11876fff5a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953692861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1953692861
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1421134294
Short name T369
Test name
Test status
Simulation time 52067996 ps
CPU time 0.78 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 195460 kb
Host smart-600f3dfa-e1a7-4c12-a112-a9ef26ff82f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421134294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1421134294
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2509104098
Short name T685
Test name
Test status
Simulation time 15349735365 ps
CPU time 102.53 seconds
Started Mar 14 01:24:34 PM PDT 24
Finished Mar 14 01:26:17 PM PDT 24
Peak memory 198504 kb
Host smart-a09154f0-15d5-444e-9fea-6bb7f3b6e3f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509104098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2509104098
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.301888587
Short name T711
Test name
Test status
Simulation time 20021747588 ps
CPU time 449.73 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:32:05 PM PDT 24
Peak memory 198476 kb
Host smart-4ed15ab1-f0f3-410d-be89-bb10b35f45e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=301888587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.301888587
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.577180714
Short name T21
Test name
Test status
Simulation time 13385352 ps
CPU time 0.61 seconds
Started Mar 14 01:24:41 PM PDT 24
Finished Mar 14 01:24:42 PM PDT 24
Peak memory 194316 kb
Host smart-4365e542-96fb-4f42-b159-ca2b317e15aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577180714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.577180714
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3295109964
Short name T593
Test name
Test status
Simulation time 105014049 ps
CPU time 0.73 seconds
Started Mar 14 01:24:40 PM PDT 24
Finished Mar 14 01:24:41 PM PDT 24
Peak memory 195604 kb
Host smart-1b6eeaa7-bce3-4c2e-b2ca-04fe5fd0620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295109964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3295109964
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.829428538
Short name T253
Test name
Test status
Simulation time 214458849 ps
CPU time 6.01 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:41 PM PDT 24
Peak memory 195888 kb
Host smart-7e19f5fa-21b3-42fa-b8ca-5df54b30a335
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829428538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.829428538
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.4028367823
Short name T557
Test name
Test status
Simulation time 115426522 ps
CPU time 0.83 seconds
Started Mar 14 01:24:44 PM PDT 24
Finished Mar 14 01:24:45 PM PDT 24
Peak memory 196244 kb
Host smart-0f1b9978-3ad1-49ed-bbab-ea22add17c54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028367823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.4028367823
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3505884565
Short name T382
Test name
Test status
Simulation time 92236597 ps
CPU time 1.56 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:37 PM PDT 24
Peak memory 197364 kb
Host smart-311b7122-1cd3-4d34-a034-5b63d8ea72d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505884565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3505884565
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1354650426
Short name T183
Test name
Test status
Simulation time 164581770 ps
CPU time 3.77 seconds
Started Mar 14 01:24:38 PM PDT 24
Finished Mar 14 01:24:42 PM PDT 24
Peak memory 198428 kb
Host smart-0d319ab1-6450-4abb-8fc7-0a563e8a173f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354650426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1354650426
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3751656222
Short name T533
Test name
Test status
Simulation time 41197998 ps
CPU time 1.26 seconds
Started Mar 14 01:24:38 PM PDT 24
Finished Mar 14 01:24:40 PM PDT 24
Peak memory 196600 kb
Host smart-b06cf5e9-e854-440a-88da-52efd31e77b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751656222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3751656222
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.824288145
Short name T63
Test name
Test status
Simulation time 170296878 ps
CPU time 1.16 seconds
Started Mar 14 01:24:38 PM PDT 24
Finished Mar 14 01:24:40 PM PDT 24
Peak memory 196224 kb
Host smart-07b90c24-206e-4c7a-83fc-a2fdaa4c1462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824288145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.824288145
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3955203055
Short name T339
Test name
Test status
Simulation time 47160867 ps
CPU time 0.73 seconds
Started Mar 14 01:24:33 PM PDT 24
Finished Mar 14 01:24:33 PM PDT 24
Peak memory 196348 kb
Host smart-f5accb99-877a-4aaa-a671-b191454c0ed9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955203055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3955203055
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2684380979
Short name T655
Test name
Test status
Simulation time 215377930 ps
CPU time 3.53 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:54 PM PDT 24
Peak memory 198276 kb
Host smart-1d8c6a98-94bd-442a-92e3-fd0b2a924da7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684380979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2684380979
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1173268943
Short name T499
Test name
Test status
Simulation time 46571630 ps
CPU time 0.88 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 196124 kb
Host smart-af7343dd-a3ce-4bd6-9fa6-3aa9fbfd35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173268943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1173268943
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1273740167
Short name T169
Test name
Test status
Simulation time 261850257 ps
CPU time 1.13 seconds
Started Mar 14 01:24:39 PM PDT 24
Finished Mar 14 01:24:40 PM PDT 24
Peak memory 196044 kb
Host smart-558774d4-3533-4e94-bf7f-43c011647cec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273740167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1273740167
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2327060966
Short name T717
Test name
Test status
Simulation time 11388318364 ps
CPU time 124.33 seconds
Started Mar 14 01:24:53 PM PDT 24
Finished Mar 14 01:26:58 PM PDT 24
Peak memory 198388 kb
Host smart-8bd513e7-8209-469f-b083-c43c3dac32dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327060966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2327060966
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1980279362
Short name T69
Test name
Test status
Simulation time 279900112000 ps
CPU time 1578.82 seconds
Started Mar 14 01:24:38 PM PDT 24
Finished Mar 14 01:50:58 PM PDT 24
Peak memory 206688 kb
Host smart-7db7ed5d-9cd2-487c-9bb9-4a1839de9fd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1980279362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1980279362
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.318459246
Short name T456
Test name
Test status
Simulation time 16460571 ps
CPU time 0.65 seconds
Started Mar 14 01:24:37 PM PDT 24
Finished Mar 14 01:24:38 PM PDT 24
Peak memory 194928 kb
Host smart-b8dfa35c-e53d-4643-b3c1-3dc6985230ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318459246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.318459246
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.569805281
Short name T625
Test name
Test status
Simulation time 47226586 ps
CPU time 0.61 seconds
Started Mar 14 01:24:42 PM PDT 24
Finished Mar 14 01:24:43 PM PDT 24
Peak memory 194088 kb
Host smart-d09c228f-c820-40bd-9902-3ff941a3771e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569805281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.569805281
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2422897869
Short name T290
Test name
Test status
Simulation time 451740418 ps
CPU time 12.51 seconds
Started Mar 14 01:24:41 PM PDT 24
Finished Mar 14 01:24:54 PM PDT 24
Peak memory 195384 kb
Host smart-8de6413b-2d14-4d56-96ea-827ca4146a41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422897869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2422897869
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.477032799
Short name T376
Test name
Test status
Simulation time 135447165 ps
CPU time 0.78 seconds
Started Mar 14 01:24:40 PM PDT 24
Finished Mar 14 01:24:41 PM PDT 24
Peak memory 194900 kb
Host smart-36fcb861-1e32-485a-bbac-aad30245dff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477032799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.477032799
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3035715012
Short name T585
Test name
Test status
Simulation time 427747273 ps
CPU time 1.44 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:37 PM PDT 24
Peak memory 197216 kb
Host smart-ce6bf1cc-a8a3-4ab5-8b81-1f1c5e43e66e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035715012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3035715012
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.369766719
Short name T394
Test name
Test status
Simulation time 294450256 ps
CPU time 1.9 seconds
Started Mar 14 01:24:41 PM PDT 24
Finished Mar 14 01:24:44 PM PDT 24
Peak memory 198416 kb
Host smart-9df4a725-7541-4706-8dbd-2a43f65792b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369766719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.369766719
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3066747580
Short name T308
Test name
Test status
Simulation time 695381724 ps
CPU time 2.5 seconds
Started Mar 14 01:24:41 PM PDT 24
Finished Mar 14 01:24:44 PM PDT 24
Peak memory 197864 kb
Host smart-e703836e-e8e9-4703-aead-af98af63120f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066747580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3066747580
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.542570468
Short name T272
Test name
Test status
Simulation time 22960271 ps
CPU time 0.83 seconds
Started Mar 14 01:24:39 PM PDT 24
Finished Mar 14 01:24:40 PM PDT 24
Peak memory 197612 kb
Host smart-7c04a179-cb0a-4bb6-879b-e98a83ee7618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542570468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.542570468
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2637833753
Short name T128
Test name
Test status
Simulation time 38699948 ps
CPU time 0.86 seconds
Started Mar 14 01:24:45 PM PDT 24
Finished Mar 14 01:24:47 PM PDT 24
Peak memory 196848 kb
Host smart-58a06fb3-9b77-4194-bcc9-020cbf28ce81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637833753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2637833753
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1630224552
Short name T158
Test name
Test status
Simulation time 64559261 ps
CPU time 3.07 seconds
Started Mar 14 01:24:40 PM PDT 24
Finished Mar 14 01:24:44 PM PDT 24
Peak memory 198284 kb
Host smart-727fcc0f-e4d2-47f4-84c3-9c05f540e40e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630224552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1630224552
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.710397383
Short name T406
Test name
Test status
Simulation time 92506507 ps
CPU time 1.48 seconds
Started Mar 14 01:24:41 PM PDT 24
Finished Mar 14 01:24:43 PM PDT 24
Peak memory 197132 kb
Host smart-878b1b53-935a-466e-b981-121792290c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710397383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.710397383
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1482665496
Short name T168
Test name
Test status
Simulation time 130524952 ps
CPU time 0.94 seconds
Started Mar 14 01:24:41 PM PDT 24
Finished Mar 14 01:24:43 PM PDT 24
Peak memory 195700 kb
Host smart-516e8c21-220b-4fd4-b7b1-99470519904c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482665496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1482665496
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1485749506
Short name T622
Test name
Test status
Simulation time 15145670734 ps
CPU time 218.78 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:28:14 PM PDT 24
Peak memory 198424 kb
Host smart-cb96868a-61e0-4a5c-a9cd-4c9a96ee7fc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485749506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1485749506
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1767967299
Short name T487
Test name
Test status
Simulation time 12678494 ps
CPU time 0.59 seconds
Started Mar 14 01:24:39 PM PDT 24
Finished Mar 14 01:24:40 PM PDT 24
Peak memory 194840 kb
Host smart-3de3d7dc-2032-483a-bf1a-df33378868cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767967299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1767967299
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1113358505
Short name T433
Test name
Test status
Simulation time 158798098 ps
CPU time 0.82 seconds
Started Mar 14 01:24:38 PM PDT 24
Finished Mar 14 01:24:39 PM PDT 24
Peak memory 195516 kb
Host smart-8fc9aab2-0034-4ff9-b6fb-cf0e24657c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113358505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1113358505
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2825717163
Short name T33
Test name
Test status
Simulation time 375760937 ps
CPU time 18.37 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:54 PM PDT 24
Peak memory 197072 kb
Host smart-1dbfb2c7-6ad3-42d3-95ac-28d1360e0d30
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825717163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2825717163
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.791433041
Short name T241
Test name
Test status
Simulation time 762445276 ps
CPU time 0.99 seconds
Started Mar 14 01:24:34 PM PDT 24
Finished Mar 14 01:24:35 PM PDT 24
Peak memory 196940 kb
Host smart-915e744b-53f0-4083-a06b-52a8d06ebd1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791433041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.791433041
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1153336365
Short name T692
Test name
Test status
Simulation time 59947352 ps
CPU time 1.08 seconds
Started Mar 14 01:24:34 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 196100 kb
Host smart-b36fe6a3-c722-4b40-8d1e-902416ef7f17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153336365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1153336365
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.12251267
Short name T493
Test name
Test status
Simulation time 140831102 ps
CPU time 3.12 seconds
Started Mar 14 01:24:38 PM PDT 24
Finished Mar 14 01:24:42 PM PDT 24
Peak memory 198476 kb
Host smart-0a19d37f-98a9-4b19-b3f2-0c1f21841bba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.gpio_intr_with_filter_rand_intr_event.12251267
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1465333843
Short name T224
Test name
Test status
Simulation time 52688934 ps
CPU time 1.69 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:37 PM PDT 24
Peak memory 196668 kb
Host smart-71c9f032-1d36-4b4a-a95b-858944f57b1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465333843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1465333843
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1250948244
Short name T469
Test name
Test status
Simulation time 20386810 ps
CPU time 0.82 seconds
Started Mar 14 01:24:34 PM PDT 24
Finished Mar 14 01:24:35 PM PDT 24
Peak memory 195676 kb
Host smart-a0c93a42-49cf-4bcc-b6f4-52e5d3975b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250948244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1250948244
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2930525512
Short name T693
Test name
Test status
Simulation time 35434402 ps
CPU time 0.8 seconds
Started Mar 14 01:24:36 PM PDT 24
Finished Mar 14 01:24:37 PM PDT 24
Peak memory 195756 kb
Host smart-991d26a0-d6f6-42ea-9b2b-57a74e4f69c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930525512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2930525512
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2913964907
Short name T354
Test name
Test status
Simulation time 423597705 ps
CPU time 4.63 seconds
Started Mar 14 01:24:36 PM PDT 24
Finished Mar 14 01:24:41 PM PDT 24
Peak memory 198160 kb
Host smart-1ca29ae8-dbc3-457c-b82c-164a59d53d58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913964907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2913964907
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.773874271
Short name T258
Test name
Test status
Simulation time 174895891 ps
CPU time 1.12 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 196084 kb
Host smart-566ab831-c438-46f9-8472-fcd4f3b51f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773874271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.773874271
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1035198319
Short name T327
Test name
Test status
Simulation time 135372504 ps
CPU time 1.3 seconds
Started Mar 14 01:24:41 PM PDT 24
Finished Mar 14 01:24:42 PM PDT 24
Peak memory 197184 kb
Host smart-4763406d-ed2e-4897-83a6-2b49a7ed38a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035198319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1035198319
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1080378058
Short name T422
Test name
Test status
Simulation time 8491109188 ps
CPU time 25.45 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:25:01 PM PDT 24
Peak memory 198476 kb
Host smart-98859d6b-b08b-4428-a8b1-b692bcf5a578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080378058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1080378058
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1409000796
Short name T119
Test name
Test status
Simulation time 38414079 ps
CPU time 0.63 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:48 PM PDT 24
Peak memory 194164 kb
Host smart-4a9fa355-51d1-401d-91f1-fdf11123a4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409000796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1409000796
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1789957544
Short name T594
Test name
Test status
Simulation time 30771347 ps
CPU time 0.81 seconds
Started Mar 14 01:24:37 PM PDT 24
Finished Mar 14 01:24:38 PM PDT 24
Peak memory 195612 kb
Host smart-ff734963-b4e9-441c-b89e-d847b4880718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789957544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1789957544
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3546726206
Short name T602
Test name
Test status
Simulation time 1688420844 ps
CPU time 17.98 seconds
Started Mar 14 01:24:37 PM PDT 24
Finished Mar 14 01:24:55 PM PDT 24
Peak memory 198344 kb
Host smart-728c3c7e-e96e-4254-9214-9086b43df4d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546726206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3546726206
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.4045615620
Short name T492
Test name
Test status
Simulation time 96291457 ps
CPU time 0.78 seconds
Started Mar 14 01:24:45 PM PDT 24
Finished Mar 14 01:24:46 PM PDT 24
Peak memory 196184 kb
Host smart-c5cbaa14-3f43-4c61-ac6a-3f4feb328a28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045615620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.4045615620
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.530076458
Short name T702
Test name
Test status
Simulation time 81840385 ps
CPU time 1.43 seconds
Started Mar 14 01:24:45 PM PDT 24
Finished Mar 14 01:24:47 PM PDT 24
Peak memory 197428 kb
Host smart-a9b8ad5e-bb4f-45f6-8721-e5cf2c98f622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530076458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.530076458
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3086820182
Short name T571
Test name
Test status
Simulation time 59106050 ps
CPU time 2.15 seconds
Started Mar 14 01:24:44 PM PDT 24
Finished Mar 14 01:24:47 PM PDT 24
Peak memory 198424 kb
Host smart-cc1cd880-75b9-4787-99f7-9407082591db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086820182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3086820182
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.61590929
Short name T597
Test name
Test status
Simulation time 46116348 ps
CPU time 1.13 seconds
Started Mar 14 01:24:45 PM PDT 24
Finished Mar 14 01:24:46 PM PDT 24
Peak memory 195716 kb
Host smart-5299cf9a-b95b-4c85-9718-7e2d09be73e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61590929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.61590929
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.4196874039
Short name T179
Test name
Test status
Simulation time 31397140 ps
CPU time 1.1 seconds
Started Mar 14 01:24:35 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 196368 kb
Host smart-7f2af89f-ca68-404f-91c9-04f1102157b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196874039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.4196874039
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3059960775
Short name T300
Test name
Test status
Simulation time 49142690 ps
CPU time 1 seconds
Started Mar 14 01:24:39 PM PDT 24
Finished Mar 14 01:24:40 PM PDT 24
Peak memory 196332 kb
Host smart-06687e99-3844-4f03-974a-57306e1a6c28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059960775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3059960775
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3406660893
Short name T223
Test name
Test status
Simulation time 177961512 ps
CPU time 2.87 seconds
Started Mar 14 01:24:41 PM PDT 24
Finished Mar 14 01:24:44 PM PDT 24
Peak memory 198256 kb
Host smart-90d0bdc7-24b4-4c8d-bb61-f4ee21d65967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406660893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3406660893
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2811882030
Short name T647
Test name
Test status
Simulation time 196839997 ps
CPU time 1.44 seconds
Started Mar 14 01:24:34 PM PDT 24
Finished Mar 14 01:24:35 PM PDT 24
Peak memory 198336 kb
Host smart-119950fb-9798-4cbc-9388-6dc92501ba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811882030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2811882030
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.380700572
Short name T281
Test name
Test status
Simulation time 39633905 ps
CPU time 1.06 seconds
Started Mar 14 01:24:45 PM PDT 24
Finished Mar 14 01:24:46 PM PDT 24
Peak memory 195968 kb
Host smart-73555a7a-14c2-4335-9c62-aabcb1b3c7f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380700572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.380700572
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.413655371
Short name T16
Test name
Test status
Simulation time 19331099188 ps
CPU time 80.09 seconds
Started Mar 14 01:24:41 PM PDT 24
Finished Mar 14 01:26:02 PM PDT 24
Peak memory 198420 kb
Host smart-cf7cdb27-5619-470d-b19a-50351bf2f5bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413655371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.413655371
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.593819479
Short name T520
Test name
Test status
Simulation time 14209698 ps
CPU time 0.62 seconds
Started Mar 14 01:23:04 PM PDT 24
Finished Mar 14 01:23:05 PM PDT 24
Peak memory 194072 kb
Host smart-54bab86b-dabd-42c8-b846-45d33321b35d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593819479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.593819479
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.4098019987
Short name T649
Test name
Test status
Simulation time 17405623 ps
CPU time 0.68 seconds
Started Mar 14 01:23:01 PM PDT 24
Finished Mar 14 01:23:03 PM PDT 24
Peak memory 194880 kb
Host smart-af493fbb-415d-45c9-a2da-067446916de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098019987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.4098019987
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3993963165
Short name T429
Test name
Test status
Simulation time 3156703343 ps
CPU time 28.1 seconds
Started Mar 14 01:22:57 PM PDT 24
Finished Mar 14 01:23:26 PM PDT 24
Peak memory 197256 kb
Host smart-26b45e18-5663-497f-ae95-68be294353f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993963165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3993963165
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1144745698
Short name T421
Test name
Test status
Simulation time 154212837 ps
CPU time 1.03 seconds
Started Mar 14 01:23:01 PM PDT 24
Finished Mar 14 01:23:02 PM PDT 24
Peak memory 196948 kb
Host smart-e97251ce-a18b-4497-8eac-a95de9d3e0a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144745698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1144745698
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2770644812
Short name T60
Test name
Test status
Simulation time 38771619 ps
CPU time 0.87 seconds
Started Mar 14 01:22:55 PM PDT 24
Finished Mar 14 01:22:56 PM PDT 24
Peak memory 195936 kb
Host smart-216622cf-9ee7-4da5-ad36-851589815359
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770644812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2770644812
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3039802191
Short name T172
Test name
Test status
Simulation time 24955599 ps
CPU time 1.13 seconds
Started Mar 14 01:22:57 PM PDT 24
Finished Mar 14 01:22:59 PM PDT 24
Peak memory 197740 kb
Host smart-3320c5f7-f1e2-44ff-ba4c-8470a30ca2a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039802191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3039802191
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3451404638
Short name T708
Test name
Test status
Simulation time 918081454 ps
CPU time 3.23 seconds
Started Mar 14 01:22:58 PM PDT 24
Finished Mar 14 01:23:01 PM PDT 24
Peak memory 197744 kb
Host smart-f04dbe37-cfc0-40a5-9532-ea6ae4c6229e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451404638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3451404638
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.524843762
Short name T246
Test name
Test status
Simulation time 105814839 ps
CPU time 0.81 seconds
Started Mar 14 01:22:58 PM PDT 24
Finished Mar 14 01:22:59 PM PDT 24
Peak memory 197536 kb
Host smart-9c5d9e60-95d8-4ba3-81b0-791e1e54985b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524843762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.524843762
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1519220717
Short name T144
Test name
Test status
Simulation time 143048351 ps
CPU time 1.44 seconds
Started Mar 14 01:23:02 PM PDT 24
Finished Mar 14 01:23:03 PM PDT 24
Peak memory 197304 kb
Host smart-36b46c64-172a-4cb9-be9a-a31b250ef110
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519220717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1519220717
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2524740335
Short name T136
Test name
Test status
Simulation time 52493069 ps
CPU time 1.16 seconds
Started Mar 14 01:22:57 PM PDT 24
Finished Mar 14 01:22:59 PM PDT 24
Peak memory 196828 kb
Host smart-c659231b-ae93-4d16-b8b2-362a20f0fb3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524740335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2524740335
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3028680613
Short name T508
Test name
Test status
Simulation time 213781471 ps
CPU time 0.83 seconds
Started Mar 14 01:23:01 PM PDT 24
Finished Mar 14 01:23:03 PM PDT 24
Peak memory 195408 kb
Host smart-8fedc62b-6cf5-4928-983b-a9abe4d30bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028680613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3028680613
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2718732145
Short name T367
Test name
Test status
Simulation time 155120017 ps
CPU time 0.95 seconds
Started Mar 14 01:22:57 PM PDT 24
Finished Mar 14 01:22:58 PM PDT 24
Peak memory 196696 kb
Host smart-4b0c707d-c239-4879-9fa8-0710112a14c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718732145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2718732145
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1592006303
Short name T712
Test name
Test status
Simulation time 9182673330 ps
CPU time 137.63 seconds
Started Mar 14 01:22:55 PM PDT 24
Finished Mar 14 01:25:13 PM PDT 24
Peak memory 198452 kb
Host smart-557344a0-0f55-4ae2-8b7a-63ad1b5f4a51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592006303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1592006303
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3414228760
Short name T67
Test name
Test status
Simulation time 29790375280 ps
CPU time 823.73 seconds
Started Mar 14 01:23:04 PM PDT 24
Finished Mar 14 01:36:48 PM PDT 24
Peak memory 198432 kb
Host smart-47737a01-bdbf-4f63-998e-1df0fbc05d45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3414228760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3414228760
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.874215073
Short name T15
Test name
Test status
Simulation time 19533636 ps
CPU time 0.56 seconds
Started Mar 14 01:22:57 PM PDT 24
Finished Mar 14 01:22:58 PM PDT 24
Peak memory 194880 kb
Host smart-77639efa-8d23-4629-b710-b78d191ebcf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874215073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.874215073
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2037382386
Short name T194
Test name
Test status
Simulation time 51781360 ps
CPU time 0.93 seconds
Started Mar 14 01:23:03 PM PDT 24
Finished Mar 14 01:23:04 PM PDT 24
Peak memory 196148 kb
Host smart-f2ae8480-dee8-4a56-a12f-d11c10f3d22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037382386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2037382386
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2620736632
Short name T558
Test name
Test status
Simulation time 183819550 ps
CPU time 9.48 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:23:06 PM PDT 24
Peak memory 197364 kb
Host smart-7d4a040e-29a1-4057-a02e-720b9b9c7d53
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620736632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2620736632
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.178862357
Short name T31
Test name
Test status
Simulation time 281746923 ps
CPU time 1.11 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:22:57 PM PDT 24
Peak memory 198084 kb
Host smart-993695ad-be76-49ef-a975-df524c2adf79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178862357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.178862357
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3011548841
Short name T288
Test name
Test status
Simulation time 31371228 ps
CPU time 1.01 seconds
Started Mar 14 01:23:00 PM PDT 24
Finished Mar 14 01:23:01 PM PDT 24
Peak memory 197020 kb
Host smart-ed309a6d-6cb5-44fe-b9ba-e286f4dfdeb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011548841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3011548841
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1194395001
Short name T55
Test name
Test status
Simulation time 117253648 ps
CPU time 1.88 seconds
Started Mar 14 01:22:58 PM PDT 24
Finished Mar 14 01:23:01 PM PDT 24
Peak memory 198472 kb
Host smart-e7e042ea-8d0a-4d7a-8922-e1aec437b6f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194395001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1194395001
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.58387524
Short name T25
Test name
Test status
Simulation time 489037008 ps
CPU time 2.49 seconds
Started Mar 14 01:22:59 PM PDT 24
Finished Mar 14 01:23:02 PM PDT 24
Peak memory 197484 kb
Host smart-9ef5ae97-9168-4a33-842b-d1ad36898cc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58387524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.58387524
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.226614932
Short name T62
Test name
Test status
Simulation time 108249948 ps
CPU time 1 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:22:57 PM PDT 24
Peak memory 196184 kb
Host smart-56b23b04-6ff7-44b3-bdbc-1bf94e1d3792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226614932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.226614932
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3507188071
Short name T414
Test name
Test status
Simulation time 296484380 ps
CPU time 0.75 seconds
Started Mar 14 01:22:57 PM PDT 24
Finished Mar 14 01:22:58 PM PDT 24
Peak memory 195628 kb
Host smart-64dd2bfe-6e18-4e96-84a7-464d6e2903fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507188071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3507188071
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1613115678
Short name T521
Test name
Test status
Simulation time 946462130 ps
CPU time 5.89 seconds
Started Mar 14 01:23:00 PM PDT 24
Finished Mar 14 01:23:06 PM PDT 24
Peak memory 198280 kb
Host smart-315b7d9b-728d-4a3d-adda-ed2cb6fdcac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613115678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1613115678
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3077262855
Short name T77
Test name
Test status
Simulation time 196540642 ps
CPU time 1.01 seconds
Started Mar 14 01:22:57 PM PDT 24
Finished Mar 14 01:22:59 PM PDT 24
Peak memory 196212 kb
Host smart-3fce7c5d-0ae5-4e4a-a604-ff95ef08c3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077262855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3077262855
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1959794119
Short name T323
Test name
Test status
Simulation time 49748344 ps
CPU time 1.28 seconds
Started Mar 14 01:22:58 PM PDT 24
Finished Mar 14 01:22:59 PM PDT 24
Peak memory 195976 kb
Host smart-2dbc8f99-a16a-4a13-bad4-e9e4e2e926dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959794119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1959794119
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3755462286
Short name T572
Test name
Test status
Simulation time 32311947191 ps
CPU time 84.76 seconds
Started Mar 14 01:22:56 PM PDT 24
Finished Mar 14 01:24:21 PM PDT 24
Peak memory 198472 kb
Host smart-cfec6e7c-7804-49c1-8e54-781466e0957d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755462286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3755462286
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.170727245
Short name T292
Test name
Test status
Simulation time 247235777690 ps
CPU time 1417.8 seconds
Started Mar 14 01:22:59 PM PDT 24
Finished Mar 14 01:46:37 PM PDT 24
Peak memory 198508 kb
Host smart-665a8993-8cbc-4e52-a164-f08106714e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=170727245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.170727245
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1783487329
Short name T254
Test name
Test status
Simulation time 20863770 ps
CPU time 0.6 seconds
Started Mar 14 01:23:14 PM PDT 24
Finished Mar 14 01:23:14 PM PDT 24
Peak memory 194136 kb
Host smart-cea2fba4-31ba-4218-aa85-56eb6a83ccfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783487329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1783487329
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.966653862
Short name T214
Test name
Test status
Simulation time 84482246 ps
CPU time 0.84 seconds
Started Mar 14 01:23:21 PM PDT 24
Finished Mar 14 01:23:22 PM PDT 24
Peak memory 196720 kb
Host smart-0ffa6736-2064-415c-b72c-ea7966ddd931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966653862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.966653862
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2334596280
Short name T578
Test name
Test status
Simulation time 284442443 ps
CPU time 4.48 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:21 PM PDT 24
Peak memory 195968 kb
Host smart-b9c32242-9930-43a2-a3b9-5bf95502a02d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334596280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2334596280
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.714911768
Short name T152
Test name
Test status
Simulation time 178282804 ps
CPU time 0.75 seconds
Started Mar 14 01:23:13 PM PDT 24
Finished Mar 14 01:23:14 PM PDT 24
Peak memory 195064 kb
Host smart-0f427b2d-ae18-40f0-9b83-30ecd48ca5e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714911768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.714911768
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2047282349
Short name T331
Test name
Test status
Simulation time 175003272 ps
CPU time 1.3 seconds
Started Mar 14 01:23:11 PM PDT 24
Finished Mar 14 01:23:12 PM PDT 24
Peak memory 196148 kb
Host smart-0b00428a-ca1c-4037-9e03-455706be5a30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047282349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2047282349
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2413855678
Short name T320
Test name
Test status
Simulation time 132435362 ps
CPU time 2.68 seconds
Started Mar 14 01:23:17 PM PDT 24
Finished Mar 14 01:23:20 PM PDT 24
Peak memory 198388 kb
Host smart-a92034cc-d012-4355-b596-2483470b0c33
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413855678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2413855678
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2591713224
Short name T133
Test name
Test status
Simulation time 355899991 ps
CPU time 3.6 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:19 PM PDT 24
Peak memory 197372 kb
Host smart-29861488-d760-4f42-b17a-ba534d9e9193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591713224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2591713224
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.737117410
Short name T481
Test name
Test status
Simulation time 30061428 ps
CPU time 1.17 seconds
Started Mar 14 01:22:58 PM PDT 24
Finished Mar 14 01:23:00 PM PDT 24
Peak memory 196388 kb
Host smart-9cb9cd76-9cdc-4cfe-b0c5-065339004729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737117410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.737117410
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2936793815
Short name T160
Test name
Test status
Simulation time 46988742 ps
CPU time 0.97 seconds
Started Mar 14 01:23:00 PM PDT 24
Finished Mar 14 01:23:02 PM PDT 24
Peak memory 196288 kb
Host smart-186c9283-3a6c-403f-8cb0-6419dab77113
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936793815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2936793815
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.895291491
Short name T695
Test name
Test status
Simulation time 99353597 ps
CPU time 2.17 seconds
Started Mar 14 01:23:17 PM PDT 24
Finished Mar 14 01:23:19 PM PDT 24
Peak memory 198156 kb
Host smart-06535f10-7f6e-4fc3-baea-8ecf368e9b28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895291491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.895291491
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1623747043
Short name T432
Test name
Test status
Simulation time 230440948 ps
CPU time 1.12 seconds
Started Mar 14 01:23:03 PM PDT 24
Finished Mar 14 01:23:05 PM PDT 24
Peak memory 196664 kb
Host smart-f396774f-6c71-4eb4-b64a-36a8841f9cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623747043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1623747043
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.604956209
Short name T637
Test name
Test status
Simulation time 178154860 ps
CPU time 1.11 seconds
Started Mar 14 01:22:58 PM PDT 24
Finished Mar 14 01:22:59 PM PDT 24
Peak memory 195808 kb
Host smart-92d5cee5-7ecf-46fb-bc37-7afc7cbdb208
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604956209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.604956209
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3258954557
Short name T131
Test name
Test status
Simulation time 13285876441 ps
CPU time 100.75 seconds
Started Mar 14 01:23:14 PM PDT 24
Finished Mar 14 01:24:55 PM PDT 24
Peak memory 198476 kb
Host smart-11b9f5ac-076d-4530-b983-535caff0122d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258954557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3258954557
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2597858116
Short name T139
Test name
Test status
Simulation time 17012149 ps
CPU time 0.63 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:15 PM PDT 24
Peak memory 194312 kb
Host smart-21201f61-9e46-439b-b3c5-b65162fbbcef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597858116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2597858116
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2540949183
Short name T251
Test name
Test status
Simulation time 37781669 ps
CPU time 0.85 seconds
Started Mar 14 01:23:14 PM PDT 24
Finished Mar 14 01:23:15 PM PDT 24
Peak memory 196440 kb
Host smart-9734609d-33d3-43b9-961e-40e3102fd916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540949183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2540949183
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.610581337
Short name T450
Test name
Test status
Simulation time 1806204425 ps
CPU time 13.38 seconds
Started Mar 14 01:23:19 PM PDT 24
Finished Mar 14 01:23:33 PM PDT 24
Peak memory 197084 kb
Host smart-3d2623d7-43bf-4ceb-bbcb-cd2565ada840
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610581337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.610581337
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.925008001
Short name T81
Test name
Test status
Simulation time 100769246 ps
CPU time 1.03 seconds
Started Mar 14 01:23:20 PM PDT 24
Finished Mar 14 01:23:22 PM PDT 24
Peak memory 196908 kb
Host smart-0b5e5317-1da3-45eb-9daf-6dc533031f5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925008001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.925008001
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.881639417
Short name T586
Test name
Test status
Simulation time 62177918 ps
CPU time 1.16 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 197024 kb
Host smart-594a1e52-b538-47d8-9429-3b599abc2765
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881639417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.881639417
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.602847311
Short name T311
Test name
Test status
Simulation time 68013161 ps
CPU time 1.54 seconds
Started Mar 14 01:23:19 PM PDT 24
Finished Mar 14 01:23:21 PM PDT 24
Peak memory 196768 kb
Host smart-9bdb1d7b-d6e4-41ff-b7cc-550f3520b362
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602847311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.602847311
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2570742452
Short name T317
Test name
Test status
Simulation time 203911995 ps
CPU time 3.27 seconds
Started Mar 14 01:23:14 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 197492 kb
Host smart-acd0b1f3-60de-45b0-85d7-c19e2df93b2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570742452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2570742452
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.972617545
Short name T28
Test name
Test status
Simulation time 21034916 ps
CPU time 0.73 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:16 PM PDT 24
Peak memory 194536 kb
Host smart-a1bea47a-adfe-488d-a71a-246c69a286b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972617545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.972617545
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1512660691
Short name T539
Test name
Test status
Simulation time 52556522 ps
CPU time 1.1 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:18 PM PDT 24
Peak memory 196764 kb
Host smart-9d4c1a18-ea8d-47de-a8d9-7b434e5ce5a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512660691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1512660691
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.4001585108
Short name T20
Test name
Test status
Simulation time 344508285 ps
CPU time 3.79 seconds
Started Mar 14 01:23:23 PM PDT 24
Finished Mar 14 01:23:27 PM PDT 24
Peak memory 198340 kb
Host smart-9a45f930-60bb-4831-9c08-2b3136a265f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001585108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.4001585108
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1221980418
Short name T691
Test name
Test status
Simulation time 43617691 ps
CPU time 1.02 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:16 PM PDT 24
Peak memory 195872 kb
Host smart-226e7bf1-bc75-459c-8863-ced38e575542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221980418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1221980418
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2656774063
Short name T566
Test name
Test status
Simulation time 235489747 ps
CPU time 1.3 seconds
Started Mar 14 01:23:13 PM PDT 24
Finished Mar 14 01:23:14 PM PDT 24
Peak memory 196888 kb
Host smart-d1b5e286-e7ae-4956-bc0f-bc9fc3b0e942
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656774063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2656774063
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1297356562
Short name T404
Test name
Test status
Simulation time 60769193862 ps
CPU time 119.21 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:25:14 PM PDT 24
Peak memory 198460 kb
Host smart-1f437546-7132-402e-84df-e8b164fc5ed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297356562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1297356562
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1621359521
Short name T68
Test name
Test status
Simulation time 28654668939 ps
CPU time 757.79 seconds
Started Mar 14 01:23:13 PM PDT 24
Finished Mar 14 01:35:51 PM PDT 24
Peak memory 198504 kb
Host smart-0100df57-29e7-459f-ae4b-e57406ab0d78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1621359521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1621359521
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2438701287
Short name T616
Test name
Test status
Simulation time 16787302 ps
CPU time 0.62 seconds
Started Mar 14 01:23:18 PM PDT 24
Finished Mar 14 01:23:19 PM PDT 24
Peak memory 194060 kb
Host smart-e9aa6b6e-a7d0-432e-ad23-9e2eec02ac4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438701287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2438701287
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3184891004
Short name T273
Test name
Test status
Simulation time 35320637 ps
CPU time 0.67 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 194980 kb
Host smart-e956f156-dc64-4152-8dc2-5d6a385f5d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184891004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3184891004
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1219227685
Short name T424
Test name
Test status
Simulation time 1912770464 ps
CPU time 13.2 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:29 PM PDT 24
Peak memory 197096 kb
Host smart-b6e64a97-fe18-4fbe-b706-634025d03917
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219227685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1219227685
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2023315103
Short name T632
Test name
Test status
Simulation time 85659188 ps
CPU time 0.81 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 196888 kb
Host smart-e139b9f1-5b14-4833-84ba-7d8940a2d7ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023315103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2023315103
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1404628186
Short name T496
Test name
Test status
Simulation time 196836790 ps
CPU time 1.42 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:16 PM PDT 24
Peak memory 198268 kb
Host smart-4470fe09-3b38-4670-a948-12cbf4d444ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404628186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1404628186
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1740450851
Short name T677
Test name
Test status
Simulation time 77205019 ps
CPU time 3.13 seconds
Started Mar 14 01:23:17 PM PDT 24
Finished Mar 14 01:23:20 PM PDT 24
Peak memory 198288 kb
Host smart-6ee5da11-7984-4f31-bec6-cc5d7bd9d71a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740450851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1740450851
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.4013378060
Short name T145
Test name
Test status
Simulation time 51279821 ps
CPU time 0.95 seconds
Started Mar 14 01:23:23 PM PDT 24
Finished Mar 14 01:23:24 PM PDT 24
Peak memory 196436 kb
Host smart-02b3197f-44c6-4ee4-949a-ae7e1b5bcd3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013378060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
4013378060
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2528619583
Short name T658
Test name
Test status
Simulation time 153319284 ps
CPU time 1.04 seconds
Started Mar 14 01:23:17 PM PDT 24
Finished Mar 14 01:23:18 PM PDT 24
Peak memory 197452 kb
Host smart-3ae6978d-6d78-4f3a-9f7b-07e988647727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528619583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2528619583
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2924270208
Short name T617
Test name
Test status
Simulation time 174605077 ps
CPU time 0.99 seconds
Started Mar 14 01:23:24 PM PDT 24
Finished Mar 14 01:23:25 PM PDT 24
Peak memory 196868 kb
Host smart-bed38ebd-eeca-486a-97f4-fd5c055afe4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924270208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2924270208
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.987677899
Short name T600
Test name
Test status
Simulation time 54960369 ps
CPU time 3.09 seconds
Started Mar 14 01:23:15 PM PDT 24
Finished Mar 14 01:23:18 PM PDT 24
Peak memory 198256 kb
Host smart-ccb550dc-1b1b-4223-b6f0-a2ed13d2b2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987677899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.987677899
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4086495798
Short name T18
Test name
Test status
Simulation time 181802057 ps
CPU time 0.87 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:23:17 PM PDT 24
Peak memory 195800 kb
Host smart-e5afc48e-f0fe-457c-b842-fb39e43c042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086495798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4086495798
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1385346362
Short name T154
Test name
Test status
Simulation time 45538873 ps
CPU time 1.11 seconds
Started Mar 14 01:23:20 PM PDT 24
Finished Mar 14 01:23:21 PM PDT 24
Peak memory 196056 kb
Host smart-b6c4f862-e08c-49a8-bbc7-4b27fb72c9a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385346362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1385346362
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3165783296
Short name T303
Test name
Test status
Simulation time 7238697529 ps
CPU time 81.36 seconds
Started Mar 14 01:23:23 PM PDT 24
Finished Mar 14 01:24:45 PM PDT 24
Peak memory 198504 kb
Host smart-04afbc74-9a58-4fe7-aae8-6978d8db7070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165783296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3165783296
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.299503149
Short name T72
Test name
Test status
Simulation time 28857512335 ps
CPU time 786.62 seconds
Started Mar 14 01:23:16 PM PDT 24
Finished Mar 14 01:36:23 PM PDT 24
Peak memory 198520 kb
Host smart-79eb7815-f65a-4e76-beeb-c01cd34ecc36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=299503149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.299503149
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2488340311
Short name T937
Test name
Test status
Simulation time 33951492 ps
CPU time 0.91 seconds
Started Mar 14 01:08:19 PM PDT 24
Finished Mar 14 01:08:20 PM PDT 24
Peak memory 195448 kb
Host smart-47036e1b-9439-4501-b971-c7c07a7b269e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2488340311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2488340311
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2680914752
Short name T845
Test name
Test status
Simulation time 355488877 ps
CPU time 1.17 seconds
Started Mar 14 01:08:11 PM PDT 24
Finished Mar 14 01:08:12 PM PDT 24
Peak memory 195688 kb
Host smart-fa17f2b2-5295-4a95-8b16-05ac435ccf90
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680914752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2680914752
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3589289775
Short name T941
Test name
Test status
Simulation time 79788770 ps
CPU time 1.16 seconds
Started Mar 14 01:08:11 PM PDT 24
Finished Mar 14 01:08:12 PM PDT 24
Peak memory 195800 kb
Host smart-43ee4631-ccc3-49c0-ac7a-c368392be759
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3589289775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3589289775
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.841898490
Short name T870
Test name
Test status
Simulation time 283391297 ps
CPU time 1.24 seconds
Started Mar 14 01:08:10 PM PDT 24
Finished Mar 14 01:08:11 PM PDT 24
Peak memory 197956 kb
Host smart-5bbff305-1dc5-43fe-a3ef-e5ba142dd6f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841898490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.841898490
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2590807639
Short name T851
Test name
Test status
Simulation time 203371343 ps
CPU time 1.04 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 195792 kb
Host smart-1f356e42-f34c-44bf-8869-ce20069d4eaa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2590807639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2590807639
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1275913112
Short name T896
Test name
Test status
Simulation time 36468484 ps
CPU time 0.99 seconds
Started Mar 14 01:08:29 PM PDT 24
Finished Mar 14 01:08:31 PM PDT 24
Peak memory 196468 kb
Host smart-8584a180-2aef-4d6e-8772-b83235080bc0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275913112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1275913112
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3130765244
Short name T857
Test name
Test status
Simulation time 29111439 ps
CPU time 0.84 seconds
Started Mar 14 01:08:29 PM PDT 24
Finished Mar 14 01:08:31 PM PDT 24
Peak memory 195584 kb
Host smart-72799700-dd82-45c6-a47e-5fd091db6aa1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3130765244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3130765244
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3349565741
Short name T865
Test name
Test status
Simulation time 82272527 ps
CPU time 0.73 seconds
Started Mar 14 01:08:26 PM PDT 24
Finished Mar 14 01:08:27 PM PDT 24
Peak memory 194384 kb
Host smart-b1e82364-b27c-4195-919d-a0b7168175ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349565741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3349565741
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3897057732
Short name T891
Test name
Test status
Simulation time 50521490 ps
CPU time 1.35 seconds
Started Mar 14 01:08:28 PM PDT 24
Finished Mar 14 01:08:30 PM PDT 24
Peak memory 196760 kb
Host smart-913cfc11-0593-4da5-bf2e-61546de9dd16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3897057732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3897057732
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3059440633
Short name T848
Test name
Test status
Simulation time 34361244 ps
CPU time 1.08 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:29 PM PDT 24
Peak memory 195780 kb
Host smart-5a6dcba1-2e41-4043-9c81-570be5906f75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059440633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3059440633
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.78852570
Short name T926
Test name
Test status
Simulation time 92250127 ps
CPU time 1.59 seconds
Started Mar 14 01:08:28 PM PDT 24
Finished Mar 14 01:08:30 PM PDT 24
Peak memory 198108 kb
Host smart-2c5720f0-09f0-4664-8bde-ec19f6ffc216
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=78852570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.78852570
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2186286725
Short name T864
Test name
Test status
Simulation time 173479978 ps
CPU time 1.48 seconds
Started Mar 14 01:08:28 PM PDT 24
Finished Mar 14 01:08:29 PM PDT 24
Peak memory 197996 kb
Host smart-43830b88-fc7b-422e-8c85-af992be7238b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186286725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2186286725
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2457101296
Short name T919
Test name
Test status
Simulation time 81694613 ps
CPU time 1.33 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 196676 kb
Host smart-09bdd21f-fdd9-404b-8f33-cae10016da78
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2457101296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2457101296
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4090382281
Short name T881
Test name
Test status
Simulation time 165986650 ps
CPU time 1.37 seconds
Started Mar 14 01:08:26 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 195640 kb
Host smart-4878e8a9-b4c9-4710-9461-edd53be85e6b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090382281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4090382281
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2268723328
Short name T879
Test name
Test status
Simulation time 111456798 ps
CPU time 0.85 seconds
Started Mar 14 01:08:26 PM PDT 24
Finished Mar 14 01:08:27 PM PDT 24
Peak memory 196108 kb
Host smart-718e573b-62e7-4ba2-a470-dcfb63700adf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2268723328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2268723328
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.828473583
Short name T934
Test name
Test status
Simulation time 105794697 ps
CPU time 1.17 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 196880 kb
Host smart-812da149-01c5-4bce-be56-dd3a3689f5eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828473583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.828473583
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2238877671
Short name T849
Test name
Test status
Simulation time 54460355 ps
CPU time 1.22 seconds
Started Mar 14 01:08:31 PM PDT 24
Finished Mar 14 01:08:33 PM PDT 24
Peak memory 195924 kb
Host smart-5b5e4f00-a40d-49f8-b2b9-94af739964f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2238877671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2238877671
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2412004189
Short name T894
Test name
Test status
Simulation time 52856694 ps
CPU time 1.06 seconds
Started Mar 14 01:08:28 PM PDT 24
Finished Mar 14 01:08:29 PM PDT 24
Peak memory 195612 kb
Host smart-83dc3edf-10a2-4fdd-b6b5-a547cba46c4c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412004189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2412004189
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3980305672
Short name T850
Test name
Test status
Simulation time 365271369 ps
CPU time 1.42 seconds
Started Mar 14 01:08:28 PM PDT 24
Finished Mar 14 01:08:30 PM PDT 24
Peak memory 196800 kb
Host smart-f0e48da1-9b88-421d-9143-388fd8d33580
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3980305672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3980305672
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2819265315
Short name T932
Test name
Test status
Simulation time 277013391 ps
CPU time 0.8 seconds
Started Mar 14 01:08:29 PM PDT 24
Finished Mar 14 01:08:31 PM PDT 24
Peak memory 195276 kb
Host smart-3697e08f-550b-4c48-98a7-899e4f720b8e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819265315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2819265315
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3126554873
Short name T874
Test name
Test status
Simulation time 37376877 ps
CPU time 0.75 seconds
Started Mar 14 01:08:26 PM PDT 24
Finished Mar 14 01:08:27 PM PDT 24
Peak memory 194436 kb
Host smart-2955e3b5-a5bc-4f45-a143-b8c5e5b2215c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3126554873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3126554873
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3557073288
Short name T844
Test name
Test status
Simulation time 41507433 ps
CPU time 1.03 seconds
Started Mar 14 01:08:26 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 196456 kb
Host smart-e16dccf6-820a-47d2-999a-345f87a009f7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557073288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3557073288
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1322101265
Short name T927
Test name
Test status
Simulation time 29981844 ps
CPU time 0.95 seconds
Started Mar 14 01:08:29 PM PDT 24
Finished Mar 14 01:08:30 PM PDT 24
Peak memory 196464 kb
Host smart-0f9744b4-0785-425c-a761-9223dca6759c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1322101265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1322101265
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.634149408
Short name T901
Test name
Test status
Simulation time 609102330 ps
CPU time 0.78 seconds
Started Mar 14 01:08:26 PM PDT 24
Finished Mar 14 01:08:27 PM PDT 24
Peak memory 195512 kb
Host smart-62a59519-5f18-45e1-b937-877dcc8c6147
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634149408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.634149408
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4273364421
Short name T929
Test name
Test status
Simulation time 36971437 ps
CPU time 0.98 seconds
Started Mar 14 01:08:15 PM PDT 24
Finished Mar 14 01:08:16 PM PDT 24
Peak memory 196484 kb
Host smart-ab545db6-03dd-4e9a-b630-f49857d79a67
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4273364421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.4273364421
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.852859745
Short name T868
Test name
Test status
Simulation time 34456902 ps
CPU time 1.06 seconds
Started Mar 14 01:08:06 PM PDT 24
Finished Mar 14 01:08:07 PM PDT 24
Peak memory 196512 kb
Host smart-afe14ce7-c441-42c3-987f-91bc17212b34
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852859745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.852859745
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3953805480
Short name T885
Test name
Test status
Simulation time 124116102 ps
CPU time 1.18 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:29 PM PDT 24
Peak memory 196544 kb
Host smart-839b01a0-8fbc-4c9f-9a41-8c2fd16332a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3953805480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3953805480
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1235829208
Short name T890
Test name
Test status
Simulation time 124517435 ps
CPU time 0.83 seconds
Started Mar 14 01:08:29 PM PDT 24
Finished Mar 14 01:08:30 PM PDT 24
Peak memory 195376 kb
Host smart-392e0e57-5163-4084-9756-3b50726a860e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235829208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1235829208
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2228519267
Short name T872
Test name
Test status
Simulation time 132332584 ps
CPU time 1.22 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 197992 kb
Host smart-3fbb30d1-acf5-4c5b-8d96-e42fc17a21bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2228519267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2228519267
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999302429
Short name T853
Test name
Test status
Simulation time 204912487 ps
CPU time 1.43 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 196744 kb
Host smart-0c441d79-c00d-4382-b241-0a11c721e471
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999302429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2999302429
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1561854246
Short name T884
Test name
Test status
Simulation time 146129070 ps
CPU time 1.2 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 197964 kb
Host smart-d2a7f90c-6df2-47ad-bc39-1f42c1cd0f86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1561854246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1561854246
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3961374023
Short name T908
Test name
Test status
Simulation time 174397035 ps
CPU time 0.98 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 196732 kb
Host smart-c7ead680-5faa-4dc4-b24d-0e21698993c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961374023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3961374023
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1265053339
Short name T880
Test name
Test status
Simulation time 86440743 ps
CPU time 0.9 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:42 PM PDT 24
Peak memory 197256 kb
Host smart-571bf4be-ee80-4a14-92ae-fdfbc07a997a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1265053339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1265053339
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2759851990
Short name T897
Test name
Test status
Simulation time 135392065 ps
CPU time 1.18 seconds
Started Mar 14 01:08:39 PM PDT 24
Finished Mar 14 01:08:41 PM PDT 24
Peak memory 196576 kb
Host smart-97b7351f-dd21-4411-a0ee-f5c5e10255f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759851990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2759851990
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2546927538
Short name T856
Test name
Test status
Simulation time 75313263 ps
CPU time 0.94 seconds
Started Mar 14 01:08:40 PM PDT 24
Finished Mar 14 01:08:41 PM PDT 24
Peak memory 196660 kb
Host smart-822e7bd6-45d3-4193-adf4-4316f4bf9505
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2546927538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2546927538
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.214365
Short name T925
Test name
Test status
Simulation time 50396712 ps
CPU time 1.04 seconds
Started Mar 14 01:08:49 PM PDT 24
Finished Mar 14 01:08:51 PM PDT 24
Peak memory 195632 kb
Host smart-42cc5c90-bfca-492f-9a37-5e67e17c1c5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_en_
cdc_prim.214365
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4084390568
Short name T928
Test name
Test status
Simulation time 107968175 ps
CPU time 0.81 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:42 PM PDT 24
Peak memory 195444 kb
Host smart-9d8441d8-7da5-4376-ad0d-5fc0da7988b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4084390568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.4084390568
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1886211537
Short name T855
Test name
Test status
Simulation time 102044210 ps
CPU time 0.88 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:42 PM PDT 24
Peak memory 195348 kb
Host smart-d9dd7f73-6eee-411a-b59c-841b6c9e2c9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886211537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1886211537
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3417388267
Short name T889
Test name
Test status
Simulation time 110603275 ps
CPU time 1.08 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:42 PM PDT 24
Peak memory 198028 kb
Host smart-5609c3fb-32e8-49bc-8817-0dd04c81c492
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3417388267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3417388267
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3088070978
Short name T888
Test name
Test status
Simulation time 171040721 ps
CPU time 1.27 seconds
Started Mar 14 01:08:43 PM PDT 24
Finished Mar 14 01:08:44 PM PDT 24
Peak memory 197956 kb
Host smart-1be4cddb-91ec-4ddd-b184-ab2143c6c9db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088070978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3088070978
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1266647937
Short name T907
Test name
Test status
Simulation time 42059888 ps
CPU time 1.32 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:42 PM PDT 24
Peak memory 197960 kb
Host smart-598389c9-c304-43d5-b405-12c74a3c8d28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1266647937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1266647937
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1270616838
Short name T900
Test name
Test status
Simulation time 57844507 ps
CPU time 1.14 seconds
Started Mar 14 01:08:42 PM PDT 24
Finished Mar 14 01:08:43 PM PDT 24
Peak memory 196372 kb
Host smart-66f0f151-5964-42bf-81d4-9b7873f2a154
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270616838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1270616838
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.209659680
Short name T917
Test name
Test status
Simulation time 202695738 ps
CPU time 0.98 seconds
Started Mar 14 01:08:40 PM PDT 24
Finished Mar 14 01:08:41 PM PDT 24
Peak memory 196660 kb
Host smart-3fb17bfa-749b-4a71-a4e1-38d619411482
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=209659680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.209659680
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3365202880
Short name T852
Test name
Test status
Simulation time 58717607 ps
CPU time 0.71 seconds
Started Mar 14 01:08:39 PM PDT 24
Finished Mar 14 01:08:40 PM PDT 24
Peak memory 194408 kb
Host smart-b50ec5dc-7ff8-4881-95d8-23d703ba184b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365202880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3365202880
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3946149731
Short name T904
Test name
Test status
Simulation time 1233618202 ps
CPU time 1.5 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:42 PM PDT 24
Peak memory 196704 kb
Host smart-e2666a64-ff92-4a20-beb7-8133a8cf1384
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3946149731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3946149731
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3931545795
Short name T913
Test name
Test status
Simulation time 149208780 ps
CPU time 1.29 seconds
Started Mar 14 01:08:39 PM PDT 24
Finished Mar 14 01:08:41 PM PDT 24
Peak memory 196668 kb
Host smart-3f793216-8a13-44c2-bc13-f95a7a39055d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931545795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3931545795
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1103304186
Short name T860
Test name
Test status
Simulation time 70024112 ps
CPU time 1.13 seconds
Started Mar 14 01:08:10 PM PDT 24
Finished Mar 14 01:08:11 PM PDT 24
Peak memory 196712 kb
Host smart-d7cbb0b8-4390-4973-886e-f13448a9d41f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1103304186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1103304186
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.672258769
Short name T903
Test name
Test status
Simulation time 107417600 ps
CPU time 1.03 seconds
Started Mar 14 01:08:13 PM PDT 24
Finished Mar 14 01:08:15 PM PDT 24
Peak memory 196492 kb
Host smart-febdb18c-e1e0-4aeb-8cdb-e4b25b4ef8af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672258769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.672258769
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.475507016
Short name T846
Test name
Test status
Simulation time 131179167 ps
CPU time 1.29 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:43 PM PDT 24
Peak memory 198040 kb
Host smart-450bafcd-debf-4261-9e45-1890fe4b0e68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=475507016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.475507016
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3316387915
Short name T918
Test name
Test status
Simulation time 46696456 ps
CPU time 0.81 seconds
Started Mar 14 01:08:38 PM PDT 24
Finished Mar 14 01:08:39 PM PDT 24
Peak memory 196100 kb
Host smart-2dee6f18-b392-49e6-a45e-99eb626fb29a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316387915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3316387915
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.825154686
Short name T920
Test name
Test status
Simulation time 284939993 ps
CPU time 1.42 seconds
Started Mar 14 01:08:40 PM PDT 24
Finished Mar 14 01:08:41 PM PDT 24
Peak memory 196800 kb
Host smart-db9212b2-fff8-4e0e-9fcc-6f5b2621ad1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=825154686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.825154686
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894856560
Short name T895
Test name
Test status
Simulation time 77453945 ps
CPU time 1.39 seconds
Started Mar 14 01:08:39 PM PDT 24
Finished Mar 14 01:08:41 PM PDT 24
Peak memory 196360 kb
Host smart-cc7b51b2-d27e-48e7-b026-716ac7dc70fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894856560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2894856560
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3645135891
Short name T847
Test name
Test status
Simulation time 301318127 ps
CPU time 1.28 seconds
Started Mar 14 01:08:39 PM PDT 24
Finished Mar 14 01:08:40 PM PDT 24
Peak memory 196748 kb
Host smart-d794c4b3-16e7-426c-9dae-ed81dd0d059f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3645135891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3645135891
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3615890015
Short name T883
Test name
Test status
Simulation time 188095998 ps
CPU time 1.02 seconds
Started Mar 14 01:08:39 PM PDT 24
Finished Mar 14 01:08:40 PM PDT 24
Peak memory 196360 kb
Host smart-89cc24ae-2241-4099-886b-7a05a87c1407
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615890015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3615890015
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.40143820
Short name T915
Test name
Test status
Simulation time 70216223 ps
CPU time 1.38 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:43 PM PDT 24
Peak memory 196672 kb
Host smart-c3fb65a1-2e76-4d00-b176-d2181b140629
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=40143820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.40143820
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.188766547
Short name T859
Test name
Test status
Simulation time 151905330 ps
CPU time 1.36 seconds
Started Mar 14 01:08:39 PM PDT 24
Finished Mar 14 01:08:40 PM PDT 24
Peak memory 196768 kb
Host smart-55c0d6fa-73e1-4cf2-b361-0a439d288613
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188766547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.188766547
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1416571492
Short name T931
Test name
Test status
Simulation time 59932108 ps
CPU time 1.11 seconds
Started Mar 14 01:08:40 PM PDT 24
Finished Mar 14 01:08:41 PM PDT 24
Peak memory 195668 kb
Host smart-6a8e28e5-73b5-4ca9-87bf-5d00c4dc7b50
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1416571492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1416571492
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3717267998
Short name T886
Test name
Test status
Simulation time 71009564 ps
CPU time 1.42 seconds
Started Mar 14 01:08:40 PM PDT 24
Finished Mar 14 01:08:41 PM PDT 24
Peak memory 197892 kb
Host smart-bd70ef57-9d29-48cb-ae5c-3239664d24b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717267998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3717267998
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1335334614
Short name T921
Test name
Test status
Simulation time 77449468 ps
CPU time 1.23 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:43 PM PDT 24
Peak memory 196672 kb
Host smart-4ddb9075-1e20-4925-a828-6e5f85c6376b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1335334614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1335334614
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3326189968
Short name T911
Test name
Test status
Simulation time 67451708 ps
CPU time 1.28 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:43 PM PDT 24
Peak memory 197940 kb
Host smart-0365122e-9266-4ca3-8468-65230cf51d36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326189968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3326189968
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3219285352
Short name T939
Test name
Test status
Simulation time 73267438 ps
CPU time 1.24 seconds
Started Mar 14 01:08:39 PM PDT 24
Finished Mar 14 01:08:40 PM PDT 24
Peak memory 196808 kb
Host smart-8d31b707-eddf-4a51-b535-8e374cebe4a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3219285352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3219285352
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.452976667
Short name T902
Test name
Test status
Simulation time 75715746 ps
CPU time 1.35 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:43 PM PDT 24
Peak memory 196924 kb
Host smart-ddee7e88-9228-4281-ae0a-49bc62a978b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452976667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.452976667
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.754691180
Short name T893
Test name
Test status
Simulation time 59526924 ps
CPU time 1.16 seconds
Started Mar 14 01:08:40 PM PDT 24
Finished Mar 14 01:08:42 PM PDT 24
Peak memory 196544 kb
Host smart-e175d395-e5f8-4da8-b8d7-f24d11a97057
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=754691180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.754691180
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.462187342
Short name T933
Test name
Test status
Simulation time 192917174 ps
CPU time 0.99 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:43 PM PDT 24
Peak memory 196588 kb
Host smart-bf6c7050-f947-4036-8f82-0b523a0fd659
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462187342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.462187342
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3187661706
Short name T863
Test name
Test status
Simulation time 257797743 ps
CPU time 1.16 seconds
Started Mar 14 01:08:40 PM PDT 24
Finished Mar 14 01:08:41 PM PDT 24
Peak memory 195712 kb
Host smart-a0c7d7ae-3b1b-4c3b-87c3-f0a29f2e3f34
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3187661706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3187661706
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1610109
Short name T905
Test name
Test status
Simulation time 545700849 ps
CPU time 1.01 seconds
Started Mar 14 01:08:42 PM PDT 24
Finished Mar 14 01:08:43 PM PDT 24
Peak memory 196580 kb
Host smart-6a5569cd-3b1c-4cfa-b671-f0c178b8ecb9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.1610109
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3857708447
Short name T914
Test name
Test status
Simulation time 699141624 ps
CPU time 1.51 seconds
Started Mar 14 01:08:41 PM PDT 24
Finished Mar 14 01:08:42 PM PDT 24
Peak memory 196636 kb
Host smart-8b643da7-663f-4926-bc3e-d102d0e8ffe9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3857708447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3857708447
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2813088187
Short name T867
Test name
Test status
Simulation time 333748084 ps
CPU time 1.46 seconds
Started Mar 14 01:08:52 PM PDT 24
Finished Mar 14 01:08:53 PM PDT 24
Peak memory 196820 kb
Host smart-dbe85f4d-f52a-4fe7-8400-250f4f1623ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813088187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2813088187
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2649322214
Short name T922
Test name
Test status
Simulation time 100847520 ps
CPU time 1.32 seconds
Started Mar 14 01:08:16 PM PDT 24
Finished Mar 14 01:08:18 PM PDT 24
Peak memory 195576 kb
Host smart-5c641fb7-c2de-4f67-a948-d790ceed9807
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2649322214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2649322214
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1213116137
Short name T942
Test name
Test status
Simulation time 303002636 ps
CPU time 1.12 seconds
Started Mar 14 01:08:16 PM PDT 24
Finished Mar 14 01:08:17 PM PDT 24
Peak memory 195640 kb
Host smart-b8642366-3ff4-49ff-a22e-7d0724ed806b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213116137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1213116137
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.767729624
Short name T910
Test name
Test status
Simulation time 358999905 ps
CPU time 1.42 seconds
Started Mar 14 01:08:50 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 196816 kb
Host smart-e316974c-0274-4eeb-a77d-8a52d973ddca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=767729624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.767729624
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3475523649
Short name T887
Test name
Test status
Simulation time 36081521 ps
CPU time 1.1 seconds
Started Mar 14 01:08:53 PM PDT 24
Finished Mar 14 01:08:55 PM PDT 24
Peak memory 195900 kb
Host smart-76bdfbd8-b337-45e5-98db-66fb91ddedf4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475523649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3475523649
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3015417363
Short name T843
Test name
Test status
Simulation time 98364013 ps
CPU time 1.21 seconds
Started Mar 14 01:08:53 PM PDT 24
Finished Mar 14 01:08:54 PM PDT 24
Peak memory 196488 kb
Host smart-70bc5bf6-8e68-425c-9f18-a02018ed80f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3015417363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3015417363
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3462272807
Short name T936
Test name
Test status
Simulation time 48402696 ps
CPU time 0.95 seconds
Started Mar 14 01:08:53 PM PDT 24
Finished Mar 14 01:08:54 PM PDT 24
Peak memory 196660 kb
Host smart-c3b79c06-41a7-4334-a8d9-19f39c817c9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462272807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3462272807
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3696113412
Short name T862
Test name
Test status
Simulation time 48765565 ps
CPU time 1.19 seconds
Started Mar 14 01:08:51 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 196600 kb
Host smart-8915f18a-9f68-4fc5-a450-cac539a42ffb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3696113412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3696113412
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.967339797
Short name T909
Test name
Test status
Simulation time 54950978 ps
CPU time 1.13 seconds
Started Mar 14 01:08:51 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 196496 kb
Host smart-7fafc445-0f42-493a-9c09-07d792bbe187
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967339797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.967339797
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.354323901
Short name T875
Test name
Test status
Simulation time 169673852 ps
CPU time 1.32 seconds
Started Mar 14 01:08:50 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 197264 kb
Host smart-7df8877e-14f7-479b-815e-d8875e3aa488
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=354323901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.354323901
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2001137670
Short name T876
Test name
Test status
Simulation time 307897200 ps
CPU time 1.5 seconds
Started Mar 14 01:08:51 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 196352 kb
Host smart-c48be6df-54a0-4558-a62c-2910034342fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001137670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2001137670
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3728556209
Short name T869
Test name
Test status
Simulation time 481500937 ps
CPU time 1.32 seconds
Started Mar 14 01:08:50 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 198032 kb
Host smart-d0a580b8-46d7-4b71-b063-d150563ce9a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3728556209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3728556209
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1615250690
Short name T906
Test name
Test status
Simulation time 89526038 ps
CPU time 1.35 seconds
Started Mar 14 01:08:52 PM PDT 24
Finished Mar 14 01:08:54 PM PDT 24
Peak memory 196652 kb
Host smart-9b96e618-fdc8-40d1-ad80-9df887562d4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615250690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1615250690
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2813673492
Short name T873
Test name
Test status
Simulation time 51346846 ps
CPU time 1.29 seconds
Started Mar 14 01:08:51 PM PDT 24
Finished Mar 14 01:08:53 PM PDT 24
Peak memory 196540 kb
Host smart-296afb09-206f-491d-a6e8-e50aa4fb9ef6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2813673492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2813673492
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1425657279
Short name T861
Test name
Test status
Simulation time 19663062 ps
CPU time 0.77 seconds
Started Mar 14 01:08:51 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 195452 kb
Host smart-c61d962d-2076-47d7-9e21-576aceb3c3de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425657279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1425657279
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2761771789
Short name T940
Test name
Test status
Simulation time 94072026 ps
CPU time 0.93 seconds
Started Mar 14 01:08:52 PM PDT 24
Finished Mar 14 01:08:53 PM PDT 24
Peak memory 196500 kb
Host smart-057b79d7-3dd3-4af2-9982-08684bc59ba6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2761771789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2761771789
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3228452916
Short name T899
Test name
Test status
Simulation time 495575765 ps
CPU time 1.27 seconds
Started Mar 14 01:08:51 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 196580 kb
Host smart-f7ce10f5-0fd7-40d8-8ac7-e1f611cf7c06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228452916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3228452916
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1985442676
Short name T923
Test name
Test status
Simulation time 41898618 ps
CPU time 1.22 seconds
Started Mar 14 01:08:51 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 196612 kb
Host smart-79bcf8fa-b1e3-491f-92ae-2cbe072cb6fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1985442676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1985442676
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.971487909
Short name T924
Test name
Test status
Simulation time 87729707 ps
CPU time 1.5 seconds
Started Mar 14 01:08:55 PM PDT 24
Finished Mar 14 01:08:57 PM PDT 24
Peak memory 196952 kb
Host smart-37c512dc-9da3-4b9a-91b8-cd21d897b81f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971487909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.971487909
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3869419654
Short name T858
Test name
Test status
Simulation time 137399851 ps
CPU time 1.2 seconds
Started Mar 14 01:08:53 PM PDT 24
Finished Mar 14 01:08:54 PM PDT 24
Peak memory 196796 kb
Host smart-d3d566f2-ec4f-4be5-8306-352c220c84b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3869419654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3869419654
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3884167497
Short name T866
Test name
Test status
Simulation time 21685921 ps
CPU time 0.78 seconds
Started Mar 14 01:08:51 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 196176 kb
Host smart-523e3b8f-dfbc-439f-84df-93d929782834
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884167497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3884167497
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2665189948
Short name T930
Test name
Test status
Simulation time 321748021 ps
CPU time 1.33 seconds
Started Mar 14 01:08:49 PM PDT 24
Finished Mar 14 01:08:51 PM PDT 24
Peak memory 196952 kb
Host smart-19ee5183-8d51-49d4-b4a2-044e8e11bd57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2665189948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2665189948
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1463369825
Short name T898
Test name
Test status
Simulation time 247354804 ps
CPU time 0.9 seconds
Started Mar 14 01:08:51 PM PDT 24
Finished Mar 14 01:08:52 PM PDT 24
Peak memory 196484 kb
Host smart-0156eb12-91b2-417c-b6da-c9b3d685635b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463369825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1463369825
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2771084403
Short name T882
Test name
Test status
Simulation time 234599951 ps
CPU time 0.93 seconds
Started Mar 14 01:08:17 PM PDT 24
Finished Mar 14 01:08:18 PM PDT 24
Peak memory 197908 kb
Host smart-dcd96a01-c757-4194-9b73-cc739db8bf89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2771084403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2771084403
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3913044763
Short name T877
Test name
Test status
Simulation time 362816467 ps
CPU time 1.06 seconds
Started Mar 14 01:08:11 PM PDT 24
Finished Mar 14 01:08:12 PM PDT 24
Peak memory 197344 kb
Host smart-49570175-71f5-4ab3-9f1f-38c18ab82314
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913044763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3913044763
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.4093206735
Short name T892
Test name
Test status
Simulation time 34658556 ps
CPU time 1.16 seconds
Started Mar 14 01:08:16 PM PDT 24
Finished Mar 14 01:08:18 PM PDT 24
Peak memory 195616 kb
Host smart-ab66129f-376c-4245-9607-d8a613214cee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4093206735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.4093206735
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2158993706
Short name T912
Test name
Test status
Simulation time 81487431 ps
CPU time 1.34 seconds
Started Mar 14 01:08:17 PM PDT 24
Finished Mar 14 01:08:19 PM PDT 24
Peak memory 195636 kb
Host smart-aba30b60-fbfc-4130-b45e-0d39af39fc27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158993706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2158993706
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.950854614
Short name T871
Test name
Test status
Simulation time 320837205 ps
CPU time 1.55 seconds
Started Mar 14 01:08:12 PM PDT 24
Finished Mar 14 01:08:14 PM PDT 24
Peak memory 197976 kb
Host smart-fdb46e1f-13d0-4107-aab7-e48cfadb4246
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=950854614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.950854614
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3215318802
Short name T878
Test name
Test status
Simulation time 99499503 ps
CPU time 1.23 seconds
Started Mar 14 01:08:29 PM PDT 24
Finished Mar 14 01:08:30 PM PDT 24
Peak memory 197944 kb
Host smart-00372d3a-eb16-4099-83be-ebf541d007bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215318802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3215318802
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3116956917
Short name T916
Test name
Test status
Simulation time 32846408 ps
CPU time 0.93 seconds
Started Mar 14 01:08:28 PM PDT 24
Finished Mar 14 01:08:29 PM PDT 24
Peak memory 195480 kb
Host smart-299e4d6d-a3a7-4134-9ede-6951fafb0a21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3116956917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3116956917
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1321703027
Short name T854
Test name
Test status
Simulation time 57325472 ps
CPU time 0.93 seconds
Started Mar 14 01:08:26 PM PDT 24
Finished Mar 14 01:08:27 PM PDT 24
Peak memory 197920 kb
Host smart-56d48124-5b3f-45a8-801b-1e793079fcd9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321703027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1321703027
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2474880150
Short name T935
Test name
Test status
Simulation time 123038477 ps
CPU time 1.03 seconds
Started Mar 14 01:08:27 PM PDT 24
Finished Mar 14 01:08:28 PM PDT 24
Peak memory 196472 kb
Host smart-f18c4662-a96e-4196-92fa-50f7e9330945
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2474880150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2474880150
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.297032555
Short name T938
Test name
Test status
Simulation time 33767810 ps
CPU time 1.02 seconds
Started Mar 14 01:08:28 PM PDT 24
Finished Mar 14 01:08:29 PM PDT 24
Peak memory 196552 kb
Host smart-3458a777-2edb-4299-b22c-5a26b7b408b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297032555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.297032555
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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