Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3823183	1			T21	1		T22	230732		T23	1
all_pins[1]	3823183	1			T21	1		T22	230732		T23	1
all_pins[2]	3823183	1			T21	1		T22	230732		T23	1
all_pins[3]	3823183	1			T21	1		T22	230732		T23	1
all_pins[4]	3823183	1			T21	1		T22	230732		T23	1
all_pins[5]	3823183	1			T21	1		T22	230732		T23	1
all_pins[6]	3823183	1			T21	1		T22	230732		T23	1
all_pins[7]	3823183	1			T21	1		T22	230732		T23	1
all_pins[8]	3823183	1			T21	1		T22	230732		T23	1
all_pins[9]	3823183	1			T21	1		T22	230732		T23	1
all_pins[10]	3823183	1			T21	1		T22	230732		T23	1
all_pins[11]	3823183	1			T21	1		T22	230732		T23	1
all_pins[12]	3823183	1			T21	1		T22	230732		T23	1
all_pins[13]	3823183	1			T21	1		T22	230732		T23	1
all_pins[14]	3823183	1			T21	1		T22	230732		T23	1
all_pins[15]	3823183	1			T21	1		T22	230732		T23	1
all_pins[16]	3823183	1			T21	1		T22	230732		T23	1
all_pins[17]	3823183	1			T21	1		T22	230732		T23	1
all_pins[18]	3823183	1			T21	1		T22	230732		T23	1
all_pins[19]	3823183	1			T21	1		T22	230732		T23	1
all_pins[20]	3823183	1			T21	1		T22	230732		T23	1
all_pins[21]	3823183	1			T21	1		T22	230732		T23	1
all_pins[22]	3823183	1			T21	1		T22	230732		T23	1
all_pins[23]	3823183	1			T21	1		T22	230732		T23	1
all_pins[24]	3823183	1			T21	1		T22	230732		T23	1
all_pins[25]	3823183	1			T21	1		T22	230732		T23	1
all_pins[26]	3823183	1			T21	1		T22	230732		T23	1
all_pins[27]	3823183	1			T21	1		T22	230732		T23	1
all_pins[28]	3823183	1			T21	1		T22	230732		T23	1
all_pins[29]	3823183	1			T21	1		T22	230732		T23	1
all_pins[30]	3823183	1			T21	1		T22	230732		T23	1
all_pins[31]	3823183	1			T21	1		T22	230732		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	76010643	1			T21	32		T22	458350		T23	32
values[0x1]	46331213	1			T22	279991		T26	2165		T27	895198
transitions[0x0=>0x1]	27773535	1			T22	167994		T26	1328		T27	540518
transitions[0x1=>0x0]	27773368	1			T22	167994		T26	1327		T27	540518

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2378345	1			T21	1		T22	142506		T23	1
all_pins[0]	values[0x1]	1444838	1			T22	88226		T26	38		T27	28377
all_pins[0]	transitions[0x0=>0x1]	896983	1			T22	53453		T26	25		T27	17379
all_pins[0]	transitions[0x1=>0x0]	896104	1			T22	54467		T26	26		T27	17182
all_pins[1]	values[0x0]	2376035	1			T21	1		T22	143450		T23	1
all_pins[1]	values[0x1]	1447148	1			T22	87282		T26	34		T27	27635
all_pins[1]	transitions[0x0=>0x1]	869360	1			T22	52058		T26	26		T27	16369
all_pins[1]	transitions[0x1=>0x0]	867050	1			T22	53002		T26	30		T27	17111
all_pins[2]	values[0x0]	2376750	1			T21	1		T22	143945		T23	1
all_pins[2]	values[0x1]	1446433	1			T22	86787		T26	66		T27	28623
all_pins[2]	transitions[0x0=>0x1]	865536	1			T22	52336		T26	44		T27	17390
all_pins[2]	transitions[0x1=>0x0]	866251	1			T22	52831		T26	12		T27	16402
all_pins[3]	values[0x0]	2370660	1			T21	1		T22	143337		T23	1
all_pins[3]	values[0x1]	1452523	1			T22	87395		T26	95		T27	28459
all_pins[3]	transitions[0x0=>0x1]	872855	1			T22	52844		T26	58		T27	16791
all_pins[3]	transitions[0x1=>0x0]	866765	1			T22	52236		T26	29		T27	16955
all_pins[4]	values[0x0]	2374078	1			T21	1		T22	142297		T23	1
all_pins[4]	values[0x1]	1449105	1			T22	88435		T26	70		T27	28317
all_pins[4]	transitions[0x0=>0x1]	864746	1			T22	52807		T26	31		T27	16989
all_pins[4]	transitions[0x1=>0x0]	868164	1			T22	51767		T26	56		T27	17131
all_pins[5]	values[0x0]	2373934	1			T21	1		T22	143806		T23	1
all_pins[5]	values[0x1]	1449249	1			T22	86926		T26	62		T27	28261
all_pins[5]	transitions[0x0=>0x1]	865778	1			T22	51814		T26	17		T27	16671
all_pins[5]	transitions[0x1=>0x0]	865634	1			T22	53323		T26	25		T27	16727
all_pins[6]	values[0x0]	2370247	1			T21	1		T22	142875		T23	1
all_pins[6]	values[0x1]	1452936	1			T22	87857		T26	72		T27	28213
all_pins[6]	transitions[0x0=>0x1]	869636	1			T22	52453		T26	54		T27	17024
all_pins[6]	transitions[0x1=>0x0]	865949	1			T22	51522		T26	44		T27	17072
all_pins[7]	values[0x0]	2375758	1			T21	1		T22	142021		T23	1
all_pins[7]	values[0x1]	1447425	1			T22	88711		T26	88		T27	28131
all_pins[7]	transitions[0x0=>0x1]	866455	1			T22	52431		T26	53		T27	17033
all_pins[7]	transitions[0x1=>0x0]	871966	1			T22	51577		T26	37		T27	17115
all_pins[8]	values[0x0]	2380113	1			T21	1		T22	143356		T23	1
all_pins[8]	values[0x1]	1443070	1			T22	87376		T26	54		T27	28372
all_pins[8]	transitions[0x0=>0x1]	861387	1			T22	51873		T26	29		T27	17289
all_pins[8]	transitions[0x1=>0x0]	865742	1			T22	53208		T26	63		T27	17048
all_pins[9]	values[0x0]	2375989	1			T21	1		T22	144597		T23	1
all_pins[9]	values[0x1]	1447194	1			T22	86135		T26	72		T27	28789
all_pins[9]	transitions[0x0=>0x1]	868431	1			T22	51467		T26	58		T27	17314
all_pins[9]	transitions[0x1=>0x0]	864307	1			T22	52708		T26	40		T27	16897
all_pins[10]	values[0x0]	2374048	1			T21	1		T22	141699		T23	1
all_pins[10]	values[0x1]	1449135	1			T22	89033		T26	62		T27	27795
all_pins[10]	transitions[0x0=>0x1]	869020	1			T22	53906		T26	40		T27	16480
all_pins[10]	transitions[0x1=>0x0]	867079	1			T22	51008		T26	50		T27	17474
all_pins[11]	values[0x0]	2374687	1			T21	1		T22	143296		T23	1
all_pins[11]	values[0x1]	1448496	1			T22	87436		T26	60		T27	27609
all_pins[11]	transitions[0x0=>0x1]	864328	1			T22	51414		T26	37		T27	16540
all_pins[11]	transitions[0x1=>0x0]	864967	1			T22	53011		T26	39		T27	16726
all_pins[12]	values[0x0]	2377448	1			T21	1		T22	143925		T23	1
all_pins[12]	values[0x1]	1445735	1			T22	86807		T26	52		T27	28063
all_pins[12]	transitions[0x0=>0x1]	866245	1			T22	52065		T26	42		T27	17140
all_pins[12]	transitions[0x1=>0x0]	869006	1			T22	52694		T26	50		T27	16686
all_pins[13]	values[0x0]	2378074	1			T21	1		T22	142332		T23	1
all_pins[13]	values[0x1]	1445109	1			T22	88400		T26	57		T27	27691
all_pins[13]	transitions[0x0=>0x1]	866492	1			T22	53268		T26	46		T27	16786
all_pins[13]	transitions[0x1=>0x0]	867118	1			T22	51675		T26	41		T27	17158
all_pins[14]	values[0x0]	2374554	1			T21	1		T22	144124		T23	1
all_pins[14]	values[0x1]	1448629	1			T22	86608		T26	61		T27	27803
all_pins[14]	transitions[0x0=>0x1]	867999	1			T22	51704		T26	57		T27	16935
all_pins[14]	transitions[0x1=>0x0]	864479	1			T22	53496		T26	53		T27	16823
all_pins[15]	values[0x0]	2371540	1			T21	1		T22	143719		T23	1
all_pins[15]	values[0x1]	1451643	1			T22	87013		T26	81		T27	28159
all_pins[15]	transitions[0x0=>0x1]	865975	1			T22	52188		T26	58		T27	17250
all_pins[15]	transitions[0x1=>0x0]	862961	1			T22	51783		T26	38		T27	16894
all_pins[16]	values[0x0]	2376617	1			T21	1		T22	143029		T23	1
all_pins[16]	values[0x1]	1446566	1			T22	87703		T26	65		T27	28284
all_pins[16]	transitions[0x0=>0x1]	864544	1			T22	52983		T26	27		T27	17033
all_pins[16]	transitions[0x1=>0x0]	869621	1			T22	52293		T26	43		T27	16908
all_pins[17]	values[0x0]	2377805	1			T21	1		T22	144426		T23	1
all_pins[17]	values[0x1]	1445378	1			T22	86306		T26	84		T27	28122
all_pins[17]	transitions[0x0=>0x1]	864731	1			T22	51172		T26	51		T27	16408
all_pins[17]	transitions[0x1=>0x0]	865919	1			T22	52569		T26	32		T27	16570
all_pins[18]	values[0x0]	2376384	1			T21	1		T22	144642		T23	1
all_pins[18]	values[0x1]	1446799	1			T22	86090		T26	63		T27	27913
all_pins[18]	transitions[0x0=>0x1]	869319	1			T22	52794		T26	28		T27	16399
all_pins[18]	transitions[0x1=>0x0]	867898	1			T22	53010		T26	49		T27	16608
all_pins[19]	values[0x0]	2377319	1			T21	1		T22	142643		T23	1
all_pins[19]	values[0x1]	1445864	1			T22	88089		T26	40		T27	28351
all_pins[19]	transitions[0x0=>0x1]	867989	1			T22	53378		T26	18		T27	16930
all_pins[19]	transitions[0x1=>0x0]	868924	1			T22	51379		T26	41		T27	16492
all_pins[20]	values[0x0]	2372382	1			T21	1		T22	143146		T23	1
all_pins[20]	values[0x1]	1450801	1			T22	87586		T26	55		T27	27569
all_pins[20]	transitions[0x0=>0x1]	868749	1			T22	51966		T26	41		T27	16753
all_pins[20]	transitions[0x1=>0x0]	863812	1			T22	52469		T26	26		T27	17535
all_pins[21]	values[0x0]	2377148	1			T21	1		T22	143656		T23	1
all_pins[21]	values[0x1]	1446035	1			T22	87076		T26	87		T27	27537
all_pins[21]	transitions[0x0=>0x1]	863225	1			T22	52476		T26	72		T27	16906
all_pins[21]	transitions[0x1=>0x0]	867991	1			T22	52986		T26	40		T27	16938
all_pins[22]	values[0x0]	2379905	1			T21	1		T22	143602		T23	1
all_pins[22]	values[0x1]	1443278	1			T22	87130		T26	81		T27	27454
all_pins[22]	transitions[0x0=>0x1]	866471	1			T22	52742		T26	42		T27	17022
all_pins[22]	transitions[0x1=>0x0]	869228	1			T22	52688		T26	48		T27	17105
all_pins[23]	values[0x0]	2373651	1			T21	1		T22	142981		T23	1
all_pins[23]	values[0x1]	1449532	1			T22	87751		T26	69		T27	27266
all_pins[23]	transitions[0x0=>0x1]	869085	1			T22	52726		T26	44		T27	16450
all_pins[23]	transitions[0x1=>0x0]	862831	1			T22	52105		T26	56		T27	16638
all_pins[24]	values[0x0]	2375216	1			T21	1		T22	143905		T23	1
all_pins[24]	values[0x1]	1447967	1			T22	86827		T26	83		T27	27419
all_pins[24]	transitions[0x0=>0x1]	866104	1			T22	52146		T26	52		T27	17109
all_pins[24]	transitions[0x1=>0x0]	867669	1			T22	53070		T26	38		T27	16956
all_pins[25]	values[0x0]	2375824	1			T21	1		T22	143121		T23	1
all_pins[25]	values[0x1]	1447359	1			T22	87611		T26	44		T27	28213
all_pins[25]	transitions[0x0=>0x1]	866600	1			T22	52597		T26	26		T27	17182
all_pins[25]	transitions[0x1=>0x0]	867208	1			T22	51813		T26	65		T27	16388
all_pins[26]	values[0x0]	2376515	1			T21	1		T22	143745		T23	1
all_pins[26]	values[0x1]	1446668	1			T22	86987		T26	82		T27	27322
all_pins[26]	transitions[0x0=>0x1]	867792	1			T22	52107		T26	62		T27	16168
all_pins[26]	transitions[0x1=>0x0]	868483	1			T22	52731		T26	24		T27	17059
all_pins[27]	values[0x0]	2375663	1			T21	1		T22	143845		T23	1
all_pins[27]	values[0x1]	1447520	1			T22	86887		T26	109		T27	27853
all_pins[27]	transitions[0x0=>0x1]	867703	1			T22	51804		T26	51		T27	17128
all_pins[27]	transitions[0x1=>0x0]	866851	1			T22	51904		T26	24		T27	16597
all_pins[28]	values[0x0]	2370129	1			T21	1		T22	142639		T23	1
all_pins[28]	values[0x1]	1453054	1			T22	88093		T26	84		T27	27949
all_pins[28]	transitions[0x0=>0x1]	870568	1			T22	53083		T26	25		T27	16953
all_pins[28]	transitions[0x1=>0x0]	865034	1			T22	51877		T26	50		T27	16857
all_pins[29]	values[0x0]	2372933	1			T21	1		T22	142738		T23	1
all_pins[29]	values[0x1]	1450250	1			T22	87994		T26	84		T27	27736
all_pins[29]	transitions[0x0=>0x1]	866105	1			T22	53207		T26	53		T27	16753
all_pins[29]	transitions[0x1=>0x0]	868909	1			T22	53306		T26	53		T27	16966
all_pins[30]	values[0x0]	2371835	1			T21	1		T22	142611		T23	1
all_pins[30]	values[0x1]	1451348	1			T22	88121		T26	71		T27	27733
all_pins[30]	transitions[0x0=>0x1]	869587	1			T22	52762		T26	44		T27	16981
all_pins[30]	transitions[0x1=>0x0]	868489	1			T22	52635		T26	57		T27	16984
all_pins[31]	values[0x0]	2379057	1			T21	1		T22	141492		T23	1
all_pins[31]	values[0x1]	1444126	1			T22	89240		T26	40		T27	28180
all_pins[31]	transitions[0x0=>0x1]	863737	1			T22	53916		T26	17		T27	16963
all_pins[31]	transitions[0x1=>0x0]	870959	1			T22	52797		T26	48		T27	16516