Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12837296	1			T21	393		T22	649920		T23	65
all_values[1]	12837296	1			T21	393		T22	649920		T23	65
all_values[2]	12837296	1			T21	393		T22	649920		T23	65
all_values[3]	12837296	1			T21	393		T22	649920		T23	65
all_values[4]	12837296	1			T21	393		T22	649920		T23	65
all_values[5]	12837296	1			T21	393		T22	649920		T23	65
all_values[6]	12837296	1			T21	393		T22	649920		T23	65
all_values[7]	12837296	1			T21	393		T22	649920		T23	65
all_values[8]	12837296	1			T21	393		T22	649920		T23	65
all_values[9]	12837296	1			T21	393		T22	649920		T23	65
all_values[10]	12837296	1			T21	393		T22	649920		T23	65
all_values[11]	12837296	1			T21	393		T22	649920		T23	65
all_values[12]	12837296	1			T21	393		T22	649920		T23	65
all_values[13]	12837296	1			T21	393		T22	649920		T23	65
all_values[14]	12837296	1			T21	393		T22	649920		T23	65
all_values[15]	12837296	1			T21	393		T22	649920		T23	65
all_values[16]	12837296	1			T21	393		T22	649920		T23	65
all_values[17]	12837296	1			T21	393		T22	649920		T23	65
all_values[18]	12837296	1			T21	393		T22	649920		T23	65
all_values[19]	12837296	1			T21	393		T22	649920		T23	65
all_values[20]	12837296	1			T21	393		T22	649920		T23	65
all_values[21]	12837296	1			T21	393		T22	649920		T23	65
all_values[22]	12837296	1			T21	393		T22	649920		T23	65
all_values[23]	12837296	1			T21	393		T22	649920		T23	65
all_values[24]	12837296	1			T21	393		T22	649920		T23	65
all_values[25]	12837296	1			T21	393		T22	649920		T23	65
all_values[26]	12837296	1			T21	393		T22	649920		T23	65
all_values[27]	12837296	1			T21	393		T22	649920		T23	65
all_values[28]	12837296	1			T21	393		T22	649920		T23	65
all_values[29]	12837296	1			T21	393		T22	649920		T23	65
all_values[30]	12837296	1			T21	393		T22	649920		T23	65
all_values[31]	12837296	1			T21	393		T22	649920		T23	65

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238470492

1

T21

12576

T22

104399

T23

2080

auto[1]

172322980

1

T22

103575

T26

4629

T27

340683

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99283331

1

T21

12576

T22

213291

T23

2080

auto[1]

311510141

1

T22

186645

T26

7398

T27

615199

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

406338453

1

T21

12576

T22

205323

T23

2080

auto[1]

4455019

1

T22

265106

T27

101028

T31

206

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2583943	1			T21	393		T22	36325		T23	65
all_values[0]	auto[0]	auto[0]	auto[1]	4819755	1			T22	287659		T26	139		T27	92865
all_values[0]	auto[0]	auto[1]	auto[0]	527279	1			T22	32247		T26	16		T27	9945
all_values[0]	auto[0]	auto[1]	auto[1]	4767084	1			T22	285420		T26	80		T27	95803
all_values[0]	auto[1]	auto[0]	auto[1]	69543	1			T22	4048		T27	1640		T31	2
all_values[0]	auto[1]	auto[1]	auto[1]	69692	1			T22	4221		T27	1559		T31	2
all_values[1]	auto[0]	auto[0]	auto[0]	2578790	1			T21	393		T22	33805		T23	65
all_values[1]	auto[0]	auto[0]	auto[1]	4794153	1			T22	274722		T26	181		T27	90688
all_values[1]	auto[0]	auto[1]	auto[0]	528813	1			T22	32968		T26	5		T27	10011
all_values[1]	auto[0]	auto[1]	auto[1]	4796861	1			T22	300173		T26	50		T27	98975
all_values[1]	auto[1]	auto[0]	auto[1]	69976	1			T22	4155		T27	1581		T31	4
all_values[1]	auto[1]	auto[1]	auto[1]	68703	1			T22	4097		T27	1610		T31	2
all_values[2]	auto[0]	auto[0]	auto[0]	2578412	1			T21	393		T22	35363		T23	65
all_values[2]	auto[0]	auto[0]	auto[1]	4803906	1			T22	288627		T26	148		T27	96332
all_values[2]	auto[0]	auto[1]	auto[0]	517535	1			T22	28870		T26	18		T27	10554
all_values[2]	auto[0]	auto[1]	auto[1]	4797971	1			T22	288818		T26	102		T27	92612
all_values[2]	auto[1]	auto[0]	auto[1]	70098	1			T22	4107		T27	1620		T31	7
all_values[2]	auto[1]	auto[1]	auto[1]	69374	1			T22	4135		T27	1533		T31	2
all_values[3]	auto[0]	auto[0]	auto[0]	2586610	1			T21	393		T22	35736		T23	65
all_values[3]	auto[0]	auto[0]	auto[1]	4812238	1			T22	288694		T26	89		T27	93273
all_values[3]	auto[0]	auto[1]	auto[0]	519543	1			T22	30811		T26	27		T27	10089
all_values[3]	auto[0]	auto[1]	auto[1]	4779656	1			T22	286377		T26	157		T27	95887
all_values[3]	auto[1]	auto[0]	auto[1]	69873	1			T22	4297		T27	1598		T31	3
all_values[3]	auto[1]	auto[1]	auto[1]	69376	1			T22	4005		T27	1602		T31	4
all_values[4]	auto[0]	auto[0]	auto[0]	2579349	1			T21	393		T22	34727		T23	65
all_values[4]	auto[0]	auto[0]	auto[1]	4798774	1			T22	282816		T26	76		T27	92740
all_values[4]	auto[0]	auto[1]	auto[0]	522470	1			T22	32115		T26	60		T27	9614
all_values[4]	auto[0]	auto[1]	auto[1]	4797711	1			T22	291897		T26	135		T27	98008
all_values[4]	auto[1]	auto[0]	auto[1]	69707	1			T22	4162		T27	1532		T31	3
all_values[4]	auto[1]	auto[1]	auto[1]	69285	1			T22	4203		T27	1583		T31	2
all_values[5]	auto[0]	auto[0]	auto[0]	2584011	1			T21	393		T22	35162		T23	65
all_values[5]	auto[0]	auto[0]	auto[1]	4811421	1			T22	289691		T26	99		T27	90820
all_values[5]	auto[0]	auto[1]	auto[0]	524123	1			T22	31931		T26	49		T27	10660
all_values[5]	auto[0]	auto[1]	auto[1]	4778791	1			T22	284901		T26	116		T27	98474
all_values[5]	auto[1]	auto[0]	auto[1]	69343	1			T22	4104		T27	1556		T31	2
all_values[5]	auto[1]	auto[1]	auto[1]	69607	1			T22	4131		T27	1587		T31	1
all_values[6]	auto[0]	auto[0]	auto[0]	2581037	1			T21	393		T22	34557		T23	65
all_values[6]	auto[0]	auto[0]	auto[1]	4768360	1			T22	284853		T26	124		T27	95704
all_values[6]	auto[0]	auto[1]	auto[0]	527447	1			T22	30808		T26	16		T27	10573
all_values[6]	auto[0]	auto[1]	auto[1]	4821312	1			T22	291467		T26	122		T27	93465
all_values[6]	auto[1]	auto[0]	auto[1]	70112	1			T22	4161		T27	1573		T31	6
all_values[6]	auto[1]	auto[1]	auto[1]	69028	1			T22	4074		T27	1553		T31	3
all_values[7]	auto[0]	auto[0]	auto[0]	2580346	1			T21	393		T22	34794		T23	65
all_values[7]	auto[0]	auto[0]	auto[1]	4792391	1			T22	281563		T26	84		T27	93679
all_values[7]	auto[0]	auto[1]	auto[0]	522533	1			T22	31050		T26	25		T27	10032
all_values[7]	auto[0]	auto[1]	auto[1]	4802665	1			T22	294062		T26	159		T27	94266
all_values[7]	auto[1]	auto[0]	auto[1]	69805	1			T22	4143		T27	1588		T31	2
all_values[7]	auto[1]	auto[1]	auto[1]	69556	1			T22	4308		T27	1548		T31	3
all_values[8]	auto[0]	auto[0]	auto[0]	2583817	1			T21	393		T22	35813		T23	65
all_values[8]	auto[0]	auto[0]	auto[1]	4826337	1			T22	287519		T26	159		T27	95921
all_values[8]	auto[0]	auto[1]	auto[0]	522238	1			T22	31440		T26	19		T27	10154
all_values[8]	auto[0]	auto[1]	auto[1]	4765898	1			T22	286812		T26	89		T27	93727
all_values[8]	auto[1]	auto[0]	auto[1]	69639	1			T22	4174		T27	1576		T31	3
all_values[8]	auto[1]	auto[1]	auto[1]	69367	1			T22	4162		T27	1647		T31	2
all_values[9]	auto[0]	auto[0]	auto[0]	2574870	1			T21	393		T22	35497		T23	65
all_values[9]	auto[0]	auto[0]	auto[1]	4800723	1			T22	296756		T26	113		T27	95379
all_values[9]	auto[0]	auto[1]	auto[0]	517296	1			T22	32581		T26	30		T27	10253
all_values[9]	auto[0]	auto[1]	auto[1]	4805048	1			T22	276778		T26	109		T27	94477
all_values[9]	auto[1]	auto[0]	auto[1]	69975	1			T22	4173		T27	1502		T31	4
all_values[9]	auto[1]	auto[1]	auto[1]	69384	1			T22	4135		T27	1622		T31	2
all_values[10]	auto[0]	auto[0]	auto[0]	2579758	1			T21	393		T22	34736		T23	65
all_values[10]	auto[0]	auto[0]	auto[1]	4798494	1			T22	279276		T26	149		T27	94363
all_values[10]	auto[0]	auto[1]	auto[0]	513140	1			T22	31597		T26	16		T27	9482
all_values[10]	auto[0]	auto[1]	auto[1]	4806747	1			T22	296084		T26	92		T27	94996
all_values[10]	auto[1]	auto[0]	auto[1]	69929	1			T22	4031		T27	1593		T31	1
all_values[10]	auto[1]	auto[1]	auto[1]	69228	1			T22	4196		T27	1570		T31	4
all_values[11]	auto[0]	auto[0]	auto[0]	2579875	1			T21	393		T22	35759		T23	65
all_values[11]	auto[0]	auto[0]	auto[1]	4793347	1			T22	290786		T26	122		T27	93661
all_values[11]	auto[0]	auto[1]	auto[0]	533928	1			T22	28834		T26	37		T27	10320
all_values[11]	auto[0]	auto[1]	auto[1]	4790940	1			T22	286305		T26	102		T27	95622
all_values[11]	auto[1]	auto[0]	auto[1]	69119	1			T22	3990		T27	1559		T31	6
all_values[11]	auto[1]	auto[1]	auto[1]	70087	1			T22	4246		T27	1594		T31	2
all_values[12]	auto[0]	auto[0]	auto[0]	2582565	1			T21	393		T22	36190		T23	65
all_values[12]	auto[0]	auto[0]	auto[1]	4804492	1			T22	288480		T26	162		T27	95410
all_values[12]	auto[0]	auto[1]	auto[0]	519194	1			T22	30354		T26	27		T27	9699
all_values[12]	auto[0]	auto[1]	auto[1]	4791801	1			T22	286546		T26	85		T27	94158
all_values[12]	auto[1]	auto[0]	auto[1]	69711	1			T22	4126		T27	1597		T31	4
all_values[12]	auto[1]	auto[1]	auto[1]	69533	1			T22	4224		T27	1558		T31	5
all_values[13]	auto[0]	auto[0]	auto[0]	2583250	1			T21	393		T22	36194		T23	65
all_values[13]	auto[0]	auto[0]	auto[1]	4810173	1			T22	288960		T26	136		T27	96672
all_values[13]	auto[0]	auto[1]	auto[0]	513666	1			T22	29283		T26	17		T27	9559
all_values[13]	auto[0]	auto[1]	auto[1]	4790610	1			T22	286999		T26	117		T27	93029
all_values[13]	auto[1]	auto[0]	auto[1]	70118	1			T22	4189		T27	1540		T31	5
all_values[13]	auto[1]	auto[1]	auto[1]	69479	1			T22	4295		T27	1612		T31	2
all_values[14]	auto[0]	auto[0]	auto[0]	2587908	1			T21	393		T22	36138		T23	65
all_values[14]	auto[0]	auto[0]	auto[1]	4793945	1			T22	289415		T26	145		T27	93166
all_values[14]	auto[0]	auto[1]	auto[0]	525210	1			T22	30043		T26	29		T27	9878
all_values[14]	auto[0]	auto[1]	auto[1]	4790749	1			T22	286003		T26	96		T27	96379
all_values[14]	auto[1]	auto[0]	auto[1]	70225	1			T22	4249		T27	1587		T31	4
all_values[14]	auto[1]	auto[1]	auto[1]	69259	1			T22	4072		T27	1590		T31	2
all_values[15]	auto[0]	auto[0]	auto[0]	2585013	1			T21	393		T22	36233		T23	65
all_values[15]	auto[0]	auto[0]	auto[1]	4811253	1			T22	289740		T26	59		T27	96059
all_values[15]	auto[0]	auto[1]	auto[0]	527015	1			T22	30248		T26	27		T27	10631
all_values[15]	auto[0]	auto[1]	auto[1]	4774765	1			T22	285516		T26	150		T27	92545
all_values[15]	auto[1]	auto[0]	auto[1]	70137	1			T22	4203		T27	1573		T31	4
all_values[15]	auto[1]	auto[1]	auto[1]	69113	1			T22	3980		T27	1589		T31	1
all_values[16]	auto[0]	auto[0]	auto[0]	2576812	1			T21	393		T22	36898		T23	65
all_values[16]	auto[0]	auto[0]	auto[1]	4811023	1			T22	287490		T26	104		T27	91290
all_values[16]	auto[0]	auto[1]	auto[0]	521898	1			T22	29946		T26	38		T27	10263
all_values[16]	auto[0]	auto[1]	auto[1]	4787987	1			T22	287170		T26	127		T27	97627
all_values[16]	auto[1]	auto[0]	auto[1]	69779	1			T22	4212		T27	1537		T31	4
all_values[16]	auto[1]	auto[1]	auto[1]	69797	1			T22	4204		T27	1573		T31	2
all_values[17]	auto[0]	auto[0]	auto[0]	2579135	1			T21	393		T22	34882		T23	65
all_values[17]	auto[0]	auto[0]	auto[1]	4818656	1			T22	290878		T26	49		T27	90601
all_values[17]	auto[0]	auto[1]	auto[0]	521148	1			T22	31455		T26	43		T27	10160
all_values[17]	auto[0]	auto[1]	auto[1]	4779246	1			T22	284403		T26	154		T27	98681
all_values[17]	auto[1]	auto[0]	auto[1]	70262	1			T22	4194		T27	1661		T31	5
all_values[17]	auto[1]	auto[1]	auto[1]	68849	1			T22	4108		T27	1582		T31	4
all_values[18]	auto[0]	auto[0]	auto[0]	2585395	1			T21	393		T22	36797		T23	65
all_values[18]	auto[0]	auto[0]	auto[1]	4792359	1			T22	289407		T26	104		T27	100334
all_values[18]	auto[0]	auto[1]	auto[0]	524532	1			T22	32891		T26	36		T27	10391
all_values[18]	auto[0]	auto[1]	auto[1]	4795603	1			T22	282590		T26	119		T27	88616
all_values[18]	auto[1]	auto[0]	auto[1]	70171	1			T22	4240		T27	1581		T31	3
all_values[18]	auto[1]	auto[1]	auto[1]	69236	1			T22	3995		T27	1517		T31	4
all_values[19]	auto[0]	auto[0]	auto[0]	2583663	1			T21	393		T22	35337		T23	65
all_values[19]	auto[0]	auto[0]	auto[1]	4812798	1			T22	286778		T26	137		T27	95959
all_values[19]	auto[0]	auto[1]	auto[0]	522307	1			T22	32371		T26	25		T27	9946
all_values[19]	auto[0]	auto[1]	auto[1]	4779071	1			T22	287226		T26	70		T27	94367
all_values[19]	auto[1]	auto[0]	auto[1]	70019	1			T22	4070		T27	1557		T31	2
all_values[19]	auto[1]	auto[1]	auto[1]	69438	1			T22	4138		T27	1586		T33	54
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all_values[20]	auto[0]	auto[1]	auto[1]	4782224	1			T22	286867		T26	89		T27	92750
all_values[20]	auto[1]	auto[0]	auto[1]	69508	1			T22	4155		T27	1603		T31	2
all_values[20]	auto[1]	auto[1]	auto[1]	69456	1			T22	4131		T27	1552		T31	1
all_values[21]	auto[0]	auto[0]	auto[0]	2576282	1			T21	393		T22	36572		T23	65
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all_values[21]	auto[0]	auto[1]	auto[1]	4797099	1			T22	287545		T26	140		T27	91533
all_values[21]	auto[1]	auto[0]	auto[1]	69868	1			T22	3999		T27	1605		T31	4
all_values[21]	auto[1]	auto[1]	auto[1]	69086	1			T22	4187		T27	1529		T31	2
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all_values[23]	auto[1]	auto[0]	auto[1]	69300	1			T22	4080		T27	1603		T31	6
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all_values[27]	auto[0]	auto[0]	auto[1]	4795806	1			T22	284443		T26	91		T27	93272
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all_values[27]	auto[0]	auto[1]	auto[1]	4811816	1			T22	289183		T26	180		T27	93930
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all_values[28]	auto[0]	auto[0]	auto[1]	4797845	1			T22	286435		T26	87		T27	95381
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all_values[28]	auto[1]	auto[0]	auto[1]	70088	1			T22	4140		T27	1566		T31	3
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all_values[29]	auto[1]	auto[1]	auto[1]	69293	1			T22	4077		T27	1496		T31	3
all_values[30]	auto[0]	auto[0]	auto[0]	2581243	1			T21	393		T22	34197		T23	65
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all_values[30]	auto[0]	auto[1]	auto[1]	4799326	1			T22	290858		T26	132		T27	95982
all_values[30]	auto[1]	auto[0]	auto[1]	70178	1			T22	4105		T27	1473		T31	6
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all_values[31]	auto[0]	auto[0]	auto[0]	2582609	1			T21	393		T22	35775		T23	65
all_values[31]	auto[0]	auto[0]	auto[1]	4805851	1			T22	279985		T26	136		T27	93869
all_values[31]	auto[0]	auto[1]	auto[0]	518348	1			T22	30746		T26	40		T27	10476
all_values[31]	auto[0]	auto[1]	auto[1]	4791409	1			T22	295155		T26	78		T27	95048
all_values[31]	auto[1]	auto[0]	auto[1]	69990	1			T22	4013		T27	1615		T31	3
all_values[31]	auto[1]	auto[1]	auto[1]	69089	1			T22	4246		T27	1598		T31	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal