Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[1]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[2]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[3]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[4]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[5]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[6]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[7]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[8]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[9]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[10]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[11]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[12]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[13]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[14]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[15]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[16]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[17]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[18]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[19]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[20]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[21]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[22]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[23]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[24]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[25]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[26]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[27]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[28]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[29]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[30]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[31]	12650569	1			T21	753		T22	626084		T23	121

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244729343

1

T21

18701

T22

131457

T23

3099

auto[1]

160088865

1

T21

5395

T22

688898

T23

773

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

325476396

1

T21

17814

T22

156125

T23

3091

auto[1]

79341812

1

T21

6282

T22

442217

T23

781

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301990257

1

T21

11705

T22

142799

T23

2123

auto[1]

102827951

1

T21

12391

T22

575476

T23

1749

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4763406	1			T21	189		T22	237552		T23	46
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3426640	1			T21	17		T22	139417		T23	9
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1249885	1			T21	62		T22	69787		T23	8
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1635432	1			T21	336		T22	103370		T23	47
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	340037	1			T21	49		T22	7391		T23	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1235169	1			T21	100		T22	68567		T23	8
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4754033	1			T21	259		T22	236879		T23	65
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3435974	1			T21	33		T22	138808		T23	13
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1247829	1			T21	94		T22	69119		T23	22
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1633440	1			T21	253		T22	104522		T23	14
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	340188	1			T21	43		T22	7593		T23	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1239105	1			T21	71		T22	69163		T23	6
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4766232	1			T21	200		T22	238191		T23	63
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3421387	1			T21	26		T22	139455		T23	15
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1246482	1			T21	105		T22	69458		T23	2
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1640580	1			T21	246		T22	103872		T23	20
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	339798	1			T21	53		T22	7107		T23	2
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1236090	1			T21	123		T22	68001		T23	19
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4774364	1			T21	281		T22	237955		T23	20
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3417223	1			T21	44		T22	139088		T23	2
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1246976	1			T21	92		T22	69605		T23	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1640050	1			T21	219		T22	104066		T23	52
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	340540	1			T21	24		T22	7211		T23	10
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1231416	1			T21	93		T22	68159		T23	27
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4764556	1			T21	242		T22	237353		T23	49
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3423487	1			T21	31		T22	138626		T23	5
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1248694	1			T21	105		T22	69581		T23	8
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1635288	1			T21	188		T22	104226		T23	46
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	341578	1			T21	43		T22	7669		T23	5
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1236966	1			T21	144		T22	68629		T23	8
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4767922	1			T21	292		T22	236689		T23	34
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3422100	1			T21	49		T22	139413		T23	4
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1239797	1			T21	119		T22	70072		T23	6
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1641221	1			T21	180		T22	103526		T23	48
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	340232	1			T21	24		T22	7463		T23	4
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1239297	1			T21	89		T22	68921		T23	25
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4761291	1			T21	306		T22	238677		T23	40
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3426330	1			T21	53		T22	139041		T23	7
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1252919	1			T21	102		T22	68197		T23	6
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1638538	1			T21	184		T22	104360		T23	40
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	337525	1			T21	25		T22	7379		T23	7
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1233966	1			T21	83		T22	68430		T23	21
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4766530	1			T21	262		T22	238259		T23	57
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3425407	1			T21	36		T22	139271		T23	8
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1246631	1			T21	98		T22	69561		T23	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1631958	1			T21	215		T22	101971		T23	32
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	339057	1			T21	30		T22	7239		T23	4
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1240986	1			T21	112		T22	69783		T23	18
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4767004	1			T21	226		T22	237911		T23	17
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3423868	1			T21	39		T22	139100		T23	2
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1247291	1			T21	103		T22	69585		T23	12
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1641393	1			T21	255		T22	102925		T23	65
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	342887	1			T21	31		T22	7271		T23	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1228126	1			T21	99		T22	69292		T23	11
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4756915	1			T21	297		T22	237233		T23	52
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3435872	1			T21	51		T22	139230		T23	4
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1246450	1			T21	102		T22	69342		T23	8
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1637169	1			T21	218		T22	103789		T23	39
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	339337	1			T21	24		T22	7254		T23	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1234826	1			T21	61		T22	69236		T23	14
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4756549	1			T21	179		T22	238426		T23	43
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3431793	1			T21	26		T22	138510		T23	10
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1244074	1			T21	131		T22	69097		T23	10
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1642959	1			T21	239		T22	103782		T23	41
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	339845	1			T21	47		T22	7461		T23	5
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1235349	1			T21	131		T22	68808		T23	12
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4765864	1			T21	212		T22	237926		T23	33
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3429413	1			T21	33		T22	139412		T23	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1243944	1			T21	85		T22	69607		T23	24
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1634729	1			T21	312		T22	103093		T23	33
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	340915	1			T21	39		T22	7264		T23	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1235704	1			T21	72		T22	68782		T23	25
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4760562	1			T21	253		T22	237255		T23	36
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3428708	1			T21	26		T22	138956		T23	9
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1244280	1			T21	127		T22	69250		T23	35
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1639280	1			T21	213		T22	103694		T23	32
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	340238	1			T21	37		T22	7373		T23	3
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1237501	1			T21	97		T22	69556		T23	6
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4766798	1			T21	171		T22	237859		T23	27
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3425182	1			T21	31		T22	138486		T23	5
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1249354	1			T21	58		T22	70093		T23	6
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1632541	1			T21	331		T22	104357		T23	57
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	340890	1			T21	35		T22	7099		T23	8
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1235804	1			T21	127		T22	68190		T23	18
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4766321	1			T21	260		T22	238801		T23	58
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3419723	1			T21	34		T22	139001		T23	9
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1244590	1			T21	80		T22	69299		T23	21
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1641265	1			T21	257		T22	103089		T23	28
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	340442	1			T21	41		T22	7220		T23	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1238228	1			T21	81		T22	68674		T24	5
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4757386	1			T21	234		T22	238524		T23	73
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3443806	1			T21	22		T22	139155		T23	3
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1254259	1			T21	87		T22	70202		T23	10
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1625677	1			T21	269		T22	102863		T23	29
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	338407	1			T21	30		T22	7111		T23	3
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1231034	1			T21	111		T22	68229		T23	3
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4764452	1			T21	307		T22	236877		T23	45
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3423530	1			T21	44		T22	138959		T23	5
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1242150	1			T21	98		T22	67290		T23	23
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1645679	1			T21	192		T22	105014		T23	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	341624	1			T21	30		T22	7590		T23	6
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1233134	1			T21	82		T22	70354		T23	18
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4767363	1			T21	220		T22	236439		T23	59
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3424663	1			T21	62		T22	139320		T23	11
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1244918	1			T21	122		T22	68866		T23	14
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1638731	1			T21	204		T22	105151		T23	29
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	341075	1			T21	27		T22	7500		T23	4
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1233819	1			T21	118		T22	68808		T23	4
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4767358	1			T21	198		T22	238843		T23	23
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3430739	1			T21	24		T22	139038		T23	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1246243	1			T21	83		T22	70240		T23	6
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1639907	1			T21	321		T22	102242		T23	63
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	337941	1			T21	37		T22	7051		T23	8
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1228381	1			T21	90		T22	68670		T23	20
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4771522	1			T21	195		T22	237432		T23	51
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3426327	1			T21	22		T22	138970		T23	5
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1236770	1			T21	80		T22	68604		T23	18
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1643415	1			T21	287		T22	105285		T23	35
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	339003	1			T21	43		T22	7356		T23	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1233532	1			T21	126		T22	68437		T23	8
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4771666	1			T21	225		T22	238943		T23	21
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3422561	1			T21	30		T22	139013		T23	5
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1242597	1			T21	65		T22	68474		T23	6
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1638903	1			T21	303		T22	102855		T23	57
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	342093	1			T21	38		T22	7320		T23	7
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1232749	1			T21	92		T22	69479		T23	25
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4761337	1			T21	193		T22	239197		T23	53
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3433572	1			T21	27		T22	139203		T23	5
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1242484	1			T21	66		T22	68708		T23	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1643198	1			T21	335		T22	103594		T23	55
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	340562	1			T21	44		T22	7207		T23	6
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1229416	1			T21	88		T22	68175		T24	6
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4770867	1			T21	225		T22	236805		T23	60
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3413327	1			T21	38		T22	138576		T23	9
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1246962	1			T21	102		T22	69765		T23	11
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1644142	1			T21	263		T22	103979		T23	35
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	341629	1			T21	26		T22	7423		T23	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1233642	1			T21	99		T22	69536		T23	2
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4763342	1			T21	293		T22	237847		T23	76
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3430061	1			T21	49		T22	139088		T23	11
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1245482	1			T21	112		T22	68739		T23	25
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1640387	1			T21	213		T22	105047		T23	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	339948	1			T21	29		T22	7363		T23	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1231349	1			T21	57		T22	68000		T24	4
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4758917	1			T21	211		T22	238402		T23	32
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3432097	1			T21	26		T22	139100		T23	2
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1243133	1			T21	75		T22	69390		T23	4
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1639378	1			T21	293		T22	102856		T23	47
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	341050	1			T21	39		T22	7204		T23	8
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1235994	1			T21	109		T22	69132		T23	28
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4767491	1			T21	196		T22	238533		T23	86
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3427472	1			T21	15		T22	139152		T23	15
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1248009	1			T21	88		T22	70032		T23	12
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1638929	1			T21	328		T22	101676		T23	8
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	339716	1			T21	44		T22	7102		T24	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1228952	1			T21	82		T22	69589		T25	165
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4749559	1			T21	206		T22	237457		T23	53
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3440537	1			T21	25		T22	138734		T23	7
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1242282	1			T21	117		T22	70212		T23	10
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1640636	1			T21	236		T22	103119		T23	42
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	340702	1			T21	36		T22	7494		T23	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1236853	1			T21	133		T22	69068		T23	8
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4766847	1			T21	305		T22	239600		T23	15
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3430895	1			T21	44		T22	138987		T23	5
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1238574	1			T21	117		T22	68723		T23	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1641155	1			T21	187		T22	102889		T23	74
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	340734	1			T21	15		T22	7435		T23	7
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1232364	1			T21	85		T22	68450		T23	8
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4759460	1			T21	305		T22	237643		T23	68
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3433035	1			T21	49		T22	139437		T23	9
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1239903	1			T21	156		T22	69107		T23	10
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1640763	1			T21	152		T22	102999		T23	28
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	342480	1			T21	24		T22	7196		T23	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1234928	1			T21	67		T22	69702		T23	4
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4760258	1			T21	220		T22	238398		T23	50
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3435240	1			T21	22		T22	139578		T23	12
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1244229	1			T21	98		T22	69255		T23	10
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1636221	1			T21	279		T22	102872		T23	22
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	339899	1			T21	36		T22	6997		T23	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1234722	1			T21	98		T22	68984		T23	25
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4775070	1			T21	177		T22	237225		T23	59
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3423892	1			T21	20		T22	138596		T23	7
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1243184	1			T21	84		T22	69206		T23	19
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1636194	1			T21	303		T22	104561		T23	23
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	338884	1			T21	44		T22	7337		T23	3
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1233345	1			T21	125		T22	69159		T23	10
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4759557	1			T21	190		T22	237307		T23	54
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3433116	1			T21	34		T22	139540		T23	8
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1241106	1			T21	81		T22	68764		T23	10
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1637905	1			T21	267		T22	104395		T23	26
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	341301	1			T21	38		T22	7097		T23	5
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1237584	1			T21	143		T22	68981		T23	18

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal