Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[1]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[2]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[3]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[4]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[5]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[6]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[7]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[8]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[9]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[10]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[11]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[12]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[13]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[14]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[15]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[16]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[17]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[18]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[19]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[20]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[21]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[22]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[23]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[24]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[25]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[26]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[27]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[28]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[29]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[30]	12650569	1			T21	753		T22	626084		T23	121
bins_for_gpio_bits[31]	12650569	1			T21	753		T22	626084		T23	121

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244729343

1

T21

18701

T22

131457

T23

3099

auto[1]

160088865

1

T21

5395

T22

688898

T23

773

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244719866

1

T21

18699

T22

131457

T23

3099

auto[1]

160098342

1

T21

5397

T22

688898

T23

773

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7427719	1			T21	569		T22	398731		T23	99
bins_for_gpio_bits[0]	auto[0]	auto[1]	220688	1			T21	18		T22	11978		T23	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	221004	1			T21	18		T22	11978		T23	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	4781158	1			T21	148		T22	203397		T23	18
bins_for_gpio_bits[1]	auto[0]	auto[0]	7413889	1			T21	591		T22	398539		T23	99
bins_for_gpio_bits[1]	auto[0]	auto[1]	221080	1			T21	15		T22	11980		T23	2
bins_for_gpio_bits[1]	auto[1]	auto[0]	221413	1			T21	15		T22	11981		T23	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	4794187	1			T21	132		T22	203584		T23	18
bins_for_gpio_bits[2]	auto[0]	auto[0]	7432088	1			T21	532		T22	399600		T23	81
bins_for_gpio_bits[2]	auto[0]	auto[1]	220995	1			T21	19		T22	11921		T23	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	221206	1			T21	19		T22	11921		T23	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	4776280	1			T21	183		T22	202642		T23	32
bins_for_gpio_bits[3]	auto[0]	auto[0]	7440279	1			T21	576		T22	399644		T23	78
bins_for_gpio_bits[3]	auto[0]	auto[1]	220789	1			T21	16		T22	11982		T23	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	221111	1			T21	16		T22	11982		T23	4
bins_for_gpio_bits[3]	auto[1]	auto[1]	4768390	1			T21	145		T22	202476		T23	35
bins_for_gpio_bits[4]	auto[0]	auto[0]	7427236	1			T21	512		T22	399186		T23	101
bins_for_gpio_bits[4]	auto[0]	auto[1]	220985	1			T21	23		T22	11974		T23	2
bins_for_gpio_bits[4]	auto[1]	auto[0]	221302	1			T21	23		T22	11974		T23	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	4781046	1			T21	195		T22	202950		T23	16
bins_for_gpio_bits[5]	auto[0]	auto[0]	7427181	1			T21	576		T22	398405		T23	83
bins_for_gpio_bits[5]	auto[0]	auto[1]	221429	1			T21	14		T22	11882		T23	5
bins_for_gpio_bits[5]	auto[1]	auto[0]	221759	1			T21	15		T22	11882		T23	5
bins_for_gpio_bits[5]	auto[1]	auto[1]	4780200	1			T21	148		T22	203915		T23	28
bins_for_gpio_bits[6]	auto[0]	auto[0]	7431540	1			T21	576		T22	399213		T23	82
bins_for_gpio_bits[6]	auto[0]	auto[1]	220906	1			T21	15		T22	12020		T23	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	221208	1			T21	16		T22	12021		T23	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	4776915	1			T21	146		T22	202830		T23	31
bins_for_gpio_bits[7]	auto[0]	auto[0]	7423082	1			T21	554		T22	397663		T23	87
bins_for_gpio_bits[7]	auto[0]	auto[1]	221749	1			T21	21		T22	12128		T23	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	222037	1			T21	21		T22	12128		T23	4
bins_for_gpio_bits[7]	auto[1]	auto[1]	4783701	1			T21	157		T22	204165		T23	26
bins_for_gpio_bits[8]	auto[0]	auto[0]	7434490	1			T21	566		T22	398403		T23	91
bins_for_gpio_bits[8]	auto[0]	auto[1]	220899	1			T21	18		T22	12018		T23	3
bins_for_gpio_bits[8]	auto[1]	auto[0]	221198	1			T21	18		T22	12018		T23	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	4773982	1			T21	151		T22	203645		T23	24
bins_for_gpio_bits[9]	auto[0]	auto[0]	7419156	1			T21	605		T22	398308		T23	95
bins_for_gpio_bits[9]	auto[0]	auto[1]	221064	1			T21	12		T22	12056		T23	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	221378	1			T21	12		T22	12056		T23	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	4788971	1			T21	124		T22	203664		T23	18
bins_for_gpio_bits[10]	auto[0]	auto[0]	7421954	1			T21	524		T22	399344		T23	92
bins_for_gpio_bits[10]	auto[0]	auto[1]	221298	1			T21	25		T22	11961		T23	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	221628	1			T21	25		T22	11961		T23	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	4785689	1			T21	179		T22	202818		T23	25
bins_for_gpio_bits[11]	auto[0]	auto[0]	7423086	1			T21	595		T22	398621		T23	84
bins_for_gpio_bits[11]	auto[0]	auto[1]	221174	1			T21	14		T22	12005		T23	6
bins_for_gpio_bits[11]	auto[1]	auto[0]	221451	1			T21	14		T22	12005		T23	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	4784858	1			T21	130		T22	203453		T23	25
bins_for_gpio_bits[12]	auto[0]	auto[0]	7422933	1			T21	576		T22	398197		T23	101
bins_for_gpio_bits[12]	auto[0]	auto[1]	220864	1			T21	17		T22	12002		T23	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	221189	1			T21	17		T22	12002		T23	2
bins_for_gpio_bits[12]	auto[1]	auto[1]	4785583	1			T21	143		T22	203883		T23	16
bins_for_gpio_bits[13]	auto[0]	auto[0]	7427490	1			T21	538		T22	400393		T23	87
bins_for_gpio_bits[13]	auto[0]	auto[1]	220942	1			T21	22		T22	11916		T23	3
bins_for_gpio_bits[13]	auto[1]	auto[0]	221203	1			T21	22		T22	11916		T23	3
bins_for_gpio_bits[13]	auto[1]	auto[1]	4780934	1			T21	171		T22	201859		T23	28
bins_for_gpio_bits[14]	auto[0]	auto[0]	7430511	1			T21	580		T22	399301		T23	107
bins_for_gpio_bits[14]	auto[0]	auto[1]	221388	1			T21	17		T22	11888		T24	3
bins_for_gpio_bits[14]	auto[1]	auto[0]	221665	1			T21	17		T22	11888		T24	3
bins_for_gpio_bits[14]	auto[1]	auto[1]	4777005	1			T21	139		T22	203007		T23	14
bins_for_gpio_bits[15]	auto[0]	auto[0]	7416431	1			T21	573		T22	399627		T23	111
bins_for_gpio_bits[15]	auto[0]	auto[1]	220615	1			T21	17		T22	11962		T23	1
bins_for_gpio_bits[15]	auto[1]	auto[0]	220891	1			T21	17		T22	11962		T23	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	4792632	1			T21	146		T22	202533		T23	8
bins_for_gpio_bits[16]	auto[0]	auto[0]	7430314	1			T21	584		T22	397104		T23	89
bins_for_gpio_bits[16]	auto[0]	auto[1]	221703	1			T21	13		T22	12076		T23	3
bins_for_gpio_bits[16]	auto[1]	auto[0]	221967	1			T21	13		T22	12077		T23	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	4776585	1			T21	143		T22	204827		T23	26
bins_for_gpio_bits[17]	auto[0]	auto[0]	7429457	1			T21	527		T22	398419		T23	101
bins_for_gpio_bits[17]	auto[0]	auto[1]	221274	1			T21	19		T22	12037		T23	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	221555	1			T21	19		T22	12037		T23	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	4778283	1			T21	188		T22	203591		T23	18
bins_for_gpio_bits[18]	auto[0]	auto[0]	7431678	1			T21	586		T22	399348		T23	88
bins_for_gpio_bits[18]	auto[0]	auto[1]	221495	1			T21	16		T22	11977		T23	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	221830	1			T21	16		T22	11977		T23	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	4775566	1			T21	135		T22	202782		T23	25
bins_for_gpio_bits[19]	auto[0]	auto[0]	7430134	1			T21	541		T22	399338		T23	102
bins_for_gpio_bits[19]	auto[0]	auto[1]	221272	1			T21	21		T22	11983		T23	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	221573	1			T21	21		T22	11983		T23	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	4777590	1			T21	170		T22	202780		T23	15
bins_for_gpio_bits[20]	auto[0]	auto[0]	7431448	1			T21	577		T22	398195		T23	78
bins_for_gpio_bits[20]	auto[0]	auto[1]	221382	1			T21	16		T22	12076		T23	6
bins_for_gpio_bits[20]	auto[1]	auto[0]	221718	1			T21	16		T22	12077		T23	6
bins_for_gpio_bits[20]	auto[1]	auto[1]	4776021	1			T21	144		T22	203736		T23	31
bins_for_gpio_bits[21]	auto[0]	auto[0]	7425467	1			T21	576		T22	399477		T23	110
bins_for_gpio_bits[21]	auto[0]	auto[1]	221289	1			T21	18		T22	12022		T25	31
bins_for_gpio_bits[21]	auto[1]	auto[0]	221552	1			T21	18		T22	12022		T25	31
bins_for_gpio_bits[21]	auto[1]	auto[1]	4782261	1			T21	141		T22	202563		T23	11
bins_for_gpio_bits[22]	auto[0]	auto[0]	7440013	1			T21	576		T22	398375		T23	105
bins_for_gpio_bits[22]	auto[0]	auto[1]	221631	1			T21	14		T22	12174		T23	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	221958	1			T21	14		T22	12174		T23	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	4766967	1			T21	149		T22	203361		T23	14
bins_for_gpio_bits[23]	auto[0]	auto[0]	7427669	1			T21	607		T22	399796		T23	109
bins_for_gpio_bits[23]	auto[0]	auto[1]	221254	1			T21	11		T22	11837		T24	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	221542	1			T21	11		T22	11837		T24	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	4780104	1			T21	124		T22	202614		T23	12
bins_for_gpio_bits[24]	auto[0]	auto[0]	7419176	1			T21	563		T22	398644		T23	78
bins_for_gpio_bits[24]	auto[0]	auto[1]	222025	1			T21	16		T22	12004		T23	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	222252	1			T21	16		T22	12004		T23	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	4787116	1			T21	158		T22	203432		T23	33
bins_for_gpio_bits[25]	auto[0]	auto[0]	7432670	1			T21	595		T22	398213		T23	106
bins_for_gpio_bits[25]	auto[0]	auto[1]	221469	1			T21	17		T22	12027		T24	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	221759	1			T21	17		T22	12028		T24	4
bins_for_gpio_bits[25]	auto[1]	auto[1]	4774671	1			T21	124		T22	203816		T23	15
bins_for_gpio_bits[26]	auto[0]	auto[0]	7410194	1			T21	535		T22	398621		T23	103
bins_for_gpio_bits[26]	auto[0]	auto[1]	221948	1			T21	24		T22	12167		T23	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	222283	1			T21	24		T22	12167		T23	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	4796144	1			T21	170		T22	203129		T23	14
bins_for_gpio_bits[27]	auto[0]	auto[0]	7425126	1			T21	594		T22	399212		T23	99
bins_for_gpio_bits[27]	auto[0]	auto[1]	221162	1			T21	15		T22	12000		T23	2
bins_for_gpio_bits[27]	auto[1]	auto[0]	221450	1			T21	15		T22	12000		T23	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	4782831	1			T21	129		T22	202872		T23	18
bins_for_gpio_bits[28]	auto[0]	auto[0]	7418592	1			T21	600		T22	397746		T23	105
bins_for_gpio_bits[28]	auto[0]	auto[1]	221235	1			T21	13		T22	12003		T23	1
bins_for_gpio_bits[28]	auto[1]	auto[0]	221534	1			T21	13		T22	12003		T23	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	4789208	1			T21	127		T22	204332		T23	14
bins_for_gpio_bits[29]	auto[0]	auto[0]	7418964	1			T21	577		T22	398505		T23	77
bins_for_gpio_bits[29]	auto[0]	auto[1]	221452	1			T21	20		T22	12019		T23	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	221744	1			T21	20		T22	12020		T23	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	4788409	1			T21	136		T22	203540		T23	34
bins_for_gpio_bits[30]	auto[0]	auto[0]	7433094	1			T21	543		T22	398881		T23	100
bins_for_gpio_bits[30]	auto[0]	auto[1]	221057	1			T21	21		T22	12110		T23	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	221354	1			T21	21		T22	12111		T23	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	4775064	1			T21	168		T22	202982		T23	19
bins_for_gpio_bits[31]	auto[0]	auto[0]	7416664	1			T21	519		T22	398467		T23	86
bins_for_gpio_bits[31]	auto[0]	auto[1]	221628	1			T21	19		T22	11999		T23	4
bins_for_gpio_bits[31]	auto[1]	auto[0]	221904	1			T21	19		T22	11999		T23	4
bins_for_gpio_bits[31]	auto[1]	auto[1]	4790373	1			T21	196		T22	203619		T23	27