Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7473241 |
1 |
|
|
T21 |
393 |
|
T22 |
328032 |
|
T23 |
65 |
| auto[1] |
5364055 |
1 |
|
|
T22 |
321888 |
|
T26 |
96 |
|
T27 |
107307 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12152701 |
1 |
|
|
T21 |
393 |
|
T22 |
610416 |
|
T23 |
65 |
| auto[1] |
684595 |
1 |
|
|
T22 |
39504 |
|
T26 |
8 |
|
T27 |
12753 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7484319 |
1 |
|
|
T21 |
393 |
|
T22 |
336276 |
|
T23 |
65 |
| auto[1] |
5352977 |
1 |
|
|
T22 |
313644 |
|
T26 |
105 |
|
T27 |
105833 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2338052 |
1 |
|
|
T22 |
133657 |
|
T26 |
81 |
|
T27 |
46270 |
| auto[1] |
auto[0] |
auto[1] |
343619 |
1 |
|
|
T22 |
19414 |
|
T26 |
8 |
|
T27 |
6199 |
| auto[1] |
auto[1] |
auto[0] |
2330330 |
1 |
|
|
T22 |
140483 |
|
T26 |
16 |
|
T27 |
46810 |
| auto[1] |
auto[1] |
auto[1] |
340976 |
1 |
|
|
T22 |
20090 |
|
T27 |
6554 |
|
T29 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442919 |
1 |
|
|
T21 |
393 |
|
T22 |
312682 |
|
T23 |
65 |
| auto[1] |
5394377 |
1 |
|
|
T22 |
337238 |
|
T26 |
55 |
|
T27 |
110596 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12145068 |
1 |
|
|
T21 |
393 |
|
T22 |
608655 |
|
T23 |
65 |
| auto[1] |
692228 |
1 |
|
|
T22 |
41265 |
|
T26 |
13 |
|
T27 |
13048 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443177 |
1 |
|
|
T21 |
393 |
|
T22 |
326603 |
|
T23 |
65 |
| auto[1] |
5394119 |
1 |
|
|
T22 |
323317 |
|
T26 |
179 |
|
T27 |
108604 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2353626 |
1 |
|
|
T22 |
134126 |
|
T26 |
133 |
|
T27 |
47206 |
| auto[1] |
auto[0] |
auto[1] |
346526 |
1 |
|
|
T22 |
19236 |
|
T26 |
10 |
|
T27 |
6480 |
| auto[1] |
auto[1] |
auto[0] |
2348265 |
1 |
|
|
T22 |
147926 |
|
T26 |
33 |
|
T27 |
48350 |
| auto[1] |
auto[1] |
auto[1] |
345702 |
1 |
|
|
T22 |
22029 |
|
T26 |
3 |
|
T27 |
6568 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7448181 |
1 |
|
|
T21 |
393 |
|
T22 |
318043 |
|
T23 |
65 |
| auto[1] |
5389115 |
1 |
|
|
T22 |
331877 |
|
T26 |
108 |
|
T27 |
106048 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12145344 |
1 |
|
|
T21 |
393 |
|
T22 |
608122 |
|
T23 |
65 |
| auto[1] |
691952 |
1 |
|
|
T22 |
41798 |
|
T26 |
11 |
|
T27 |
13464 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435630 |
1 |
|
|
T21 |
393 |
|
T22 |
322203 |
|
T23 |
65 |
| auto[1] |
5401666 |
1 |
|
|
T22 |
327717 |
|
T26 |
138 |
|
T27 |
111370 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2349282 |
1 |
|
|
T22 |
142039 |
|
T26 |
66 |
|
T27 |
47738 |
| auto[1] |
auto[0] |
auto[1] |
344776 |
1 |
|
|
T22 |
20693 |
|
T26 |
6 |
|
T27 |
6462 |
| auto[1] |
auto[1] |
auto[0] |
2360432 |
1 |
|
|
T22 |
143880 |
|
T26 |
61 |
|
T27 |
50168 |
| auto[1] |
auto[1] |
auto[1] |
347176 |
1 |
|
|
T22 |
21105 |
|
T26 |
5 |
|
T27 |
7002 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442341 |
1 |
|
|
T21 |
393 |
|
T22 |
330535 |
|
T23 |
65 |
| auto[1] |
5394955 |
1 |
|
|
T22 |
319385 |
|
T26 |
139 |
|
T27 |
107536 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12148930 |
1 |
|
|
T21 |
393 |
|
T22 |
609136 |
|
T23 |
65 |
| auto[1] |
688366 |
1 |
|
|
T22 |
40784 |
|
T26 |
6 |
|
T27 |
12422 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7458266 |
1 |
|
|
T21 |
393 |
|
T22 |
330062 |
|
T23 |
65 |
| auto[1] |
5379030 |
1 |
|
|
T22 |
319858 |
|
T26 |
129 |
|
T27 |
105314 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2346985 |
1 |
|
|
T22 |
139214 |
|
T26 |
57 |
|
T27 |
45596 |
| auto[1] |
auto[0] |
auto[1] |
344187 |
1 |
|
|
T22 |
20438 |
|
T26 |
2 |
|
T27 |
5938 |
| auto[1] |
auto[1] |
auto[0] |
2343679 |
1 |
|
|
T22 |
139860 |
|
T26 |
66 |
|
T27 |
47296 |
| auto[1] |
auto[1] |
auto[1] |
344179 |
1 |
|
|
T22 |
20346 |
|
T26 |
4 |
|
T27 |
6484 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7456768 |
1 |
|
|
T21 |
393 |
|
T22 |
328796 |
|
T23 |
65 |
| auto[1] |
5380528 |
1 |
|
|
T22 |
321124 |
|
T26 |
112 |
|
T27 |
105415 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12146086 |
1 |
|
|
T21 |
393 |
|
T22 |
609206 |
|
T23 |
65 |
| auto[1] |
691210 |
1 |
|
|
T22 |
40714 |
|
T26 |
12 |
|
T27 |
13733 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7440086 |
1 |
|
|
T21 |
393 |
|
T22 |
329098 |
|
T23 |
65 |
| auto[1] |
5397210 |
1 |
|
|
T22 |
320822 |
|
T26 |
162 |
|
T27 |
111732 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2353081 |
1 |
|
|
T22 |
137002 |
|
T26 |
101 |
|
T27 |
50571 |
| auto[1] |
auto[0] |
auto[1] |
345299 |
1 |
|
|
T22 |
19701 |
|
T26 |
9 |
|
T27 |
7103 |
| auto[1] |
auto[1] |
auto[0] |
2352919 |
1 |
|
|
T22 |
143106 |
|
T26 |
49 |
|
T27 |
47428 |
| auto[1] |
auto[1] |
auto[1] |
345911 |
1 |
|
|
T22 |
21013 |
|
T26 |
3 |
|
T27 |
6630 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7463541 |
1 |
|
|
T21 |
393 |
|
T22 |
329343 |
|
T23 |
65 |
| auto[1] |
5373755 |
1 |
|
|
T22 |
320577 |
|
T26 |
134 |
|
T27 |
104200 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12144331 |
1 |
|
|
T21 |
393 |
|
T22 |
608403 |
|
T23 |
65 |
| auto[1] |
692965 |
1 |
|
|
T22 |
41517 |
|
T26 |
15 |
|
T27 |
12851 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7426443 |
1 |
|
|
T21 |
393 |
|
T22 |
323510 |
|
T23 |
65 |
| auto[1] |
5410853 |
1 |
|
|
T22 |
326410 |
|
T26 |
185 |
|
T27 |
107602 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2368458 |
1 |
|
|
T22 |
141808 |
|
T26 |
87 |
|
T27 |
48808 |
| auto[1] |
auto[0] |
auto[1] |
346494 |
1 |
|
|
T22 |
20690 |
|
T26 |
10 |
|
T27 |
6689 |
| auto[1] |
auto[1] |
auto[0] |
2349430 |
1 |
|
|
T22 |
143085 |
|
T26 |
83 |
|
T27 |
45943 |
| auto[1] |
auto[1] |
auto[1] |
346471 |
1 |
|
|
T22 |
20827 |
|
T26 |
5 |
|
T27 |
6162 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452078 |
1 |
|
|
T21 |
393 |
|
T22 |
329802 |
|
T23 |
65 |
| auto[1] |
5385218 |
1 |
|
|
T22 |
320118 |
|
T26 |
125 |
|
T27 |
107847 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12151228 |
1 |
|
|
T21 |
393 |
|
T22 |
609136 |
|
T23 |
65 |
| auto[1] |
686068 |
1 |
|
|
T22 |
40784 |
|
T26 |
10 |
|
T27 |
12594 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469199 |
1 |
|
|
T21 |
393 |
|
T22 |
326837 |
|
T23 |
65 |
| auto[1] |
5368097 |
1 |
|
|
T22 |
323083 |
|
T26 |
139 |
|
T27 |
105212 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2350709 |
1 |
|
|
T22 |
139264 |
|
T26 |
87 |
|
T27 |
45170 |
| auto[1] |
auto[0] |
auto[1] |
343637 |
1 |
|
|
T22 |
19831 |
|
T26 |
8 |
|
T27 |
5979 |
| auto[1] |
auto[1] |
auto[0] |
2331320 |
1 |
|
|
T22 |
143035 |
|
T26 |
42 |
|
T27 |
47448 |
| auto[1] |
auto[1] |
auto[1] |
342431 |
1 |
|
|
T22 |
20953 |
|
T26 |
2 |
|
T27 |
6615 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7466403 |
1 |
|
|
T21 |
393 |
|
T22 |
330176 |
|
T23 |
65 |
| auto[1] |
5370893 |
1 |
|
|
T22 |
319744 |
|
T26 |
177 |
|
T27 |
104765 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12152375 |
1 |
|
|
T21 |
393 |
|
T22 |
609282 |
|
T23 |
65 |
| auto[1] |
684921 |
1 |
|
|
T22 |
40638 |
|
T26 |
11 |
|
T27 |
12746 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7478671 |
1 |
|
|
T21 |
393 |
|
T22 |
327301 |
|
T23 |
65 |
| auto[1] |
5358625 |
1 |
|
|
T22 |
322619 |
|
T26 |
139 |
|
T27 |
107213 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2346712 |
1 |
|
|
T22 |
144348 |
|
T26 |
43 |
|
T27 |
48621 |
| auto[1] |
auto[0] |
auto[1] |
344116 |
1 |
|
|
T22 |
20899 |
|
T26 |
2 |
|
T27 |
6584 |
| auto[1] |
auto[1] |
auto[0] |
2326992 |
1 |
|
|
T22 |
137633 |
|
T26 |
85 |
|
T27 |
45846 |
| auto[1] |
auto[1] |
auto[1] |
340805 |
1 |
|
|
T22 |
19739 |
|
T26 |
9 |
|
T27 |
6162 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7457614 |
1 |
|
|
T21 |
393 |
|
T22 |
328600 |
|
T23 |
65 |
| auto[1] |
5379682 |
1 |
|
|
T22 |
321320 |
|
T26 |
165 |
|
T27 |
109463 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12145473 |
1 |
|
|
T21 |
393 |
|
T22 |
608786 |
|
T23 |
65 |
| auto[1] |
691823 |
1 |
|
|
T22 |
41134 |
|
T26 |
13 |
|
T27 |
12296 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443218 |
1 |
|
|
T21 |
393 |
|
T22 |
325217 |
|
T23 |
65 |
| auto[1] |
5394078 |
1 |
|
|
T22 |
324703 |
|
T26 |
184 |
|
T27 |
103433 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2350609 |
1 |
|
|
T22 |
142570 |
|
T26 |
78 |
|
T27 |
42399 |
| auto[1] |
auto[0] |
auto[1] |
345930 |
1 |
|
|
T22 |
20678 |
|
T26 |
6 |
|
T27 |
5563 |
| auto[1] |
auto[1] |
auto[0] |
2351646 |
1 |
|
|
T22 |
140999 |
|
T26 |
93 |
|
T27 |
48738 |
| auto[1] |
auto[1] |
auto[1] |
345893 |
1 |
|
|
T22 |
20456 |
|
T26 |
7 |
|
T27 |
6733 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468053 |
1 |
|
|
T21 |
393 |
|
T22 |
329954 |
|
T23 |
65 |
| auto[1] |
5369243 |
1 |
|
|
T22 |
319966 |
|
T26 |
197 |
|
T27 |
110423 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12152243 |
1 |
|
|
T21 |
393 |
|
T22 |
609361 |
|
T23 |
65 |
| auto[1] |
685053 |
1 |
|
|
T22 |
40559 |
|
T26 |
9 |
|
T27 |
11981 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476101 |
1 |
|
|
T21 |
393 |
|
T22 |
331178 |
|
T23 |
65 |
| auto[1] |
5361195 |
1 |
|
|
T22 |
318742 |
|
T26 |
136 |
|
T27 |
103015 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2342576 |
1 |
|
|
T22 |
138673 |
|
T26 |
34 |
|
T27 |
42537 |
| auto[1] |
auto[0] |
auto[1] |
343055 |
1 |
|
|
T22 |
20181 |
|
T26 |
2 |
|
T27 |
5469 |
| auto[1] |
auto[1] |
auto[0] |
2333566 |
1 |
|
|
T22 |
139510 |
|
T26 |
93 |
|
T27 |
48497 |
| auto[1] |
auto[1] |
auto[1] |
341998 |
1 |
|
|
T22 |
20378 |
|
T26 |
7 |
|
T27 |
6512 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447925 |
1 |
|
|
T21 |
393 |
|
T22 |
330444 |
|
T23 |
65 |
| auto[1] |
5389371 |
1 |
|
|
T22 |
319476 |
|
T26 |
155 |
|
T27 |
100524 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12152955 |
1 |
|
|
T21 |
393 |
|
T22 |
609067 |
|
T23 |
65 |
| auto[1] |
684341 |
1 |
|
|
T22 |
40853 |
|
T26 |
11 |
|
T27 |
12701 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7484614 |
1 |
|
|
T21 |
393 |
|
T22 |
327300 |
|
T23 |
65 |
| auto[1] |
5352682 |
1 |
|
|
T22 |
322620 |
|
T26 |
181 |
|
T27 |
106042 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2330711 |
1 |
|
|
T22 |
141706 |
|
T26 |
67 |
|
T27 |
49539 |
| auto[1] |
auto[0] |
auto[1] |
340683 |
1 |
|
|
T22 |
20785 |
|
T26 |
1 |
|
T27 |
6787 |
| auto[1] |
auto[1] |
auto[0] |
2337630 |
1 |
|
|
T22 |
140061 |
|
T26 |
103 |
|
T27 |
43802 |
| auto[1] |
auto[1] |
auto[1] |
343658 |
1 |
|
|
T22 |
20068 |
|
T26 |
10 |
|
T27 |
5914 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7466480 |
1 |
|
|
T21 |
393 |
|
T22 |
326185 |
|
T23 |
65 |
| auto[1] |
5370816 |
1 |
|
|
T22 |
323735 |
|
T26 |
95 |
|
T27 |
105899 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12138910 |
1 |
|
|
T21 |
393 |
|
T22 |
606859 |
|
T23 |
65 |
| auto[1] |
698386 |
1 |
|
|
T22 |
43061 |
|
T26 |
8 |
|
T27 |
14028 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7391462 |
1 |
|
|
T21 |
393 |
|
T22 |
314648 |
|
T23 |
65 |
| auto[1] |
5445834 |
1 |
|
|
T22 |
335272 |
|
T26 |
167 |
|
T27 |
112563 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2384461 |
1 |
|
|
T22 |
148139 |
|
T26 |
101 |
|
T27 |
49684 |
| auto[1] |
auto[0] |
auto[1] |
350844 |
1 |
|
|
T22 |
21926 |
|
T26 |
6 |
|
T27 |
7042 |
| auto[1] |
auto[1] |
auto[0] |
2362987 |
1 |
|
|
T22 |
144072 |
|
T26 |
58 |
|
T27 |
48851 |
| auto[1] |
auto[1] |
auto[1] |
347542 |
1 |
|
|
T22 |
21135 |
|
T26 |
2 |
|
T27 |
6986 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452416 |
1 |
|
|
T21 |
393 |
|
T22 |
328097 |
|
T23 |
65 |
| auto[1] |
5384880 |
1 |
|
|
T22 |
321823 |
|
T26 |
120 |
|
T27 |
104699 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12148156 |
1 |
|
|
T21 |
393 |
|
T22 |
608947 |
|
T23 |
65 |
| auto[1] |
689140 |
1 |
|
|
T22 |
40973 |
|
T26 |
10 |
|
T27 |
12483 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7446713 |
1 |
|
|
T21 |
393 |
|
T22 |
327479 |
|
T23 |
65 |
| auto[1] |
5390583 |
1 |
|
|
T22 |
322441 |
|
T26 |
142 |
|
T27 |
105592 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2352281 |
1 |
|
|
T22 |
136998 |
|
T26 |
73 |
|
T27 |
48078 |
| auto[1] |
auto[0] |
auto[1] |
344328 |
1 |
|
|
T22 |
20127 |
|
T26 |
6 |
|
T27 |
6520 |
| auto[1] |
auto[1] |
auto[0] |
2349162 |
1 |
|
|
T22 |
144470 |
|
T26 |
59 |
|
T27 |
45031 |
| auto[1] |
auto[1] |
auto[1] |
344812 |
1 |
|
|
T22 |
20846 |
|
T26 |
4 |
|
T27 |
5963 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7465129 |
1 |
|
|
T21 |
393 |
|
T22 |
329017 |
|
T23 |
65 |
| auto[1] |
5372167 |
1 |
|
|
T22 |
320903 |
|
T26 |
103 |
|
T27 |
104975 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12148187 |
1 |
|
|
T21 |
393 |
|
T22 |
608337 |
|
T23 |
65 |
| auto[1] |
689109 |
1 |
|
|
T22 |
41583 |
|
T26 |
11 |
|
T27 |
12562 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7448126 |
1 |
|
|
T21 |
393 |
|
T22 |
323350 |
|
T23 |
65 |
| auto[1] |
5389170 |
1 |
|
|
T22 |
326570 |
|
T26 |
144 |
|
T27 |
104269 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2358604 |
1 |
|
|
T22 |
142775 |
|
T26 |
90 |
|
T27 |
46087 |
| auto[1] |
auto[0] |
auto[1] |
346938 |
1 |
|
|
T22 |
20819 |
|
T26 |
6 |
|
T27 |
6455 |
| auto[1] |
auto[1] |
auto[0] |
2341457 |
1 |
|
|
T22 |
142212 |
|
T26 |
43 |
|
T27 |
45620 |
| auto[1] |
auto[1] |
auto[1] |
342171 |
1 |
|
|
T22 |
20764 |
|
T26 |
5 |
|
T27 |
6107 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447729 |
1 |
|
|
T21 |
393 |
|
T22 |
328146 |
|
T23 |
65 |
| auto[1] |
5389567 |
1 |
|
|
T22 |
321774 |
|
T26 |
149 |
|
T27 |
102576 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12148068 |
1 |
|
|
T21 |
393 |
|
T22 |
608963 |
|
T23 |
65 |
| auto[1] |
689228 |
1 |
|
|
T22 |
40957 |
|
T26 |
6 |
|
T27 |
11861 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452669 |
1 |
|
|
T21 |
393 |
|
T22 |
327605 |
|
T23 |
65 |
| auto[1] |
5384627 |
1 |
|
|
T22 |
322315 |
|
T26 |
95 |
|
T27 |
102605 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2351295 |
1 |
|
|
T22 |
140759 |
|
T26 |
39 |
|
T27 |
46751 |
| auto[1] |
auto[0] |
auto[1] |
344410 |
1 |
|
|
T22 |
20447 |
|
T26 |
1 |
|
T27 |
6240 |
| auto[1] |
auto[1] |
auto[0] |
2344104 |
1 |
|
|
T22 |
140599 |
|
T26 |
50 |
|
T27 |
43993 |
| auto[1] |
auto[1] |
auto[1] |
344818 |
1 |
|
|
T22 |
20510 |
|
T26 |
5 |
|
T27 |
5621 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445887 |
1 |
|
|
T21 |
393 |
|
T22 |
319810 |
|
T23 |
65 |
| auto[1] |
5391409 |
1 |
|
|
T22 |
330110 |
|
T26 |
168 |
|
T27 |
104641 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12151051 |
1 |
|
|
T21 |
393 |
|
T22 |
610473 |
|
T23 |
65 |
| auto[1] |
686245 |
1 |
|
|
T22 |
39447 |
|
T26 |
7 |
|
T27 |
13002 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7470144 |
1 |
|
|
T21 |
393 |
|
T22 |
337242 |
|
T23 |
65 |
| auto[1] |
5367152 |
1 |
|
|
T22 |
312678 |
|
T26 |
125 |
|
T27 |
108261 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2353533 |
1 |
|
|
T22 |
132520 |
|
T26 |
30 |
|
T27 |
48258 |
| auto[1] |
auto[0] |
auto[1] |
345155 |
1 |
|
|
T22 |
19148 |
|
T27 |
6635 |
|
T29 |
90 |
| auto[1] |
auto[1] |
auto[0] |
2327374 |
1 |
|
|
T22 |
140711 |
|
T26 |
88 |
|
T27 |
47001 |
| auto[1] |
auto[1] |
auto[1] |
341090 |
1 |
|
|
T22 |
20299 |
|
T26 |
7 |
|
T27 |
6367 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435983 |
1 |
|
|
T21 |
393 |
|
T22 |
315927 |
|
T23 |
65 |
| auto[1] |
5401313 |
1 |
|
|
T22 |
333993 |
|
T26 |
112 |
|
T27 |
107798 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12149605 |
1 |
|
|
T21 |
393 |
|
T22 |
609544 |
|
T23 |
65 |
| auto[1] |
687691 |
1 |
|
|
T22 |
40376 |
|
T26 |
6 |
|
T27 |
12709 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7464092 |
1 |
|
|
T21 |
393 |
|
T22 |
329966 |
|
T23 |
65 |
| auto[1] |
5373204 |
1 |
|
|
T22 |
319954 |
|
T26 |
114 |
|
T27 |
106754 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2345501 |
1 |
|
|
T22 |
133382 |
|
T26 |
44 |
|
T27 |
45676 |
| auto[1] |
auto[0] |
auto[1] |
344674 |
1 |
|
|
T22 |
19094 |
|
T26 |
2 |
|
T27 |
6108 |
| auto[1] |
auto[1] |
auto[0] |
2340012 |
1 |
|
|
T22 |
146196 |
|
T26 |
64 |
|
T27 |
48369 |
| auto[1] |
auto[1] |
auto[1] |
343017 |
1 |
|
|
T22 |
21282 |
|
T26 |
4 |
|
T27 |
6601 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443005 |
1 |
|
|
T21 |
393 |
|
T22 |
327738 |
|
T23 |
65 |
| auto[1] |
5394291 |
1 |
|
|
T22 |
322182 |
|
T26 |
185 |
|
T27 |
104998 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12147911 |
1 |
|
|
T21 |
393 |
|
T22 |
608566 |
|
T23 |
65 |
| auto[1] |
689385 |
1 |
|
|
T22 |
41354 |
|
T26 |
8 |
|
T27 |
12875 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452900 |
1 |
|
|
T21 |
393 |
|
T22 |
324193 |
|
T23 |
65 |
| auto[1] |
5384396 |
1 |
|
|
T22 |
325727 |
|
T26 |
107 |
|
T27 |
106180 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2343465 |
1 |
|
|
T22 |
142758 |
|
T26 |
38 |
|
T27 |
48121 |
| auto[1] |
auto[0] |
auto[1] |
344282 |
1 |
|
|
T22 |
20745 |
|
T26 |
6 |
|
T27 |
6705 |
| auto[1] |
auto[1] |
auto[0] |
2351546 |
1 |
|
|
T22 |
141615 |
|
T26 |
61 |
|
T27 |
45184 |
| auto[1] |
auto[1] |
auto[1] |
345103 |
1 |
|
|
T22 |
20609 |
|
T26 |
2 |
|
T27 |
6170 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7457125 |
1 |
|
|
T21 |
393 |
|
T22 |
328746 |
|
T23 |
65 |
| auto[1] |
5380171 |
1 |
|
|
T22 |
321174 |
|
T26 |
106 |
|
T27 |
103163 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12143222 |
1 |
|
|
T21 |
393 |
|
T22 |
607952 |
|
T23 |
65 |
| auto[1] |
694074 |
1 |
|
|
T22 |
41968 |
|
T26 |
12 |
|
T27 |
13565 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7423556 |
1 |
|
|
T21 |
393 |
|
T22 |
321312 |
|
T23 |
65 |
| auto[1] |
5413740 |
1 |
|
|
T22 |
328608 |
|
T26 |
176 |
|
T27 |
110955 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2378654 |
1 |
|
|
T22 |
146222 |
|
T26 |
102 |
|
T27 |
50823 |
| auto[1] |
auto[0] |
auto[1] |
350074 |
1 |
|
|
T22 |
21424 |
|
T26 |
8 |
|
T27 |
7143 |
| auto[1] |
auto[1] |
auto[0] |
2341012 |
1 |
|
|
T22 |
140418 |
|
T26 |
62 |
|
T27 |
46567 |
| auto[1] |
auto[1] |
auto[1] |
344000 |
1 |
|
|
T22 |
20544 |
|
T26 |
4 |
|
T27 |
6422 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |