Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7419509 |
1 |
|
|
T21 |
393 |
|
T22 |
323571 |
|
T23 |
65 |
| auto[1] |
5417787 |
1 |
|
|
T22 |
326349 |
|
T26 |
138 |
|
T27 |
105591 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12150801 |
1 |
|
|
T21 |
393 |
|
T22 |
608564 |
|
T23 |
65 |
| auto[1] |
686495 |
1 |
|
|
T22 |
41356 |
|
T26 |
9 |
|
T27 |
13588 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468968 |
1 |
|
|
T21 |
393 |
|
T22 |
324728 |
|
T23 |
65 |
| auto[1] |
5368328 |
1 |
|
|
T22 |
325192 |
|
T26 |
129 |
|
T27 |
111509 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2341285 |
1 |
|
|
T22 |
142050 |
|
T26 |
66 |
|
T27 |
48699 |
| auto[1] |
auto[0] |
auto[1] |
342872 |
1 |
|
|
T22 |
20867 |
|
T26 |
6 |
|
T27 |
6689 |
| auto[1] |
auto[1] |
auto[0] |
2340548 |
1 |
|
|
T22 |
141786 |
|
T26 |
54 |
|
T27 |
49222 |
| auto[1] |
auto[1] |
auto[1] |
343623 |
1 |
|
|
T22 |
20489 |
|
T26 |
3 |
|
T27 |
6899 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |