Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7456768 |
1 |
|
|
T21 |
393 |
|
T22 |
328796 |
|
T23 |
65 |
| auto[1] |
5380528 |
1 |
|
|
T22 |
321124 |
|
T26 |
112 |
|
T27 |
105415 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10650850 |
1 |
|
|
T21 |
393 |
|
T22 |
527396 |
|
T23 |
65 |
| auto[1] |
2186446 |
1 |
|
|
T22 |
122524 |
|
T26 |
119 |
|
T27 |
39048 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7446661 |
1 |
|
|
T21 |
393 |
|
T22 |
326695 |
|
T23 |
65 |
| auto[1] |
5390635 |
1 |
|
|
T22 |
323225 |
|
T26 |
196 |
|
T27 |
105302 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1609410 |
1 |
|
|
T22 |
102463 |
|
T26 |
47 |
|
T27 |
32833 |
| auto[1] |
auto[0] |
auto[1] |
1097739 |
1 |
|
|
T22 |
62212 |
|
T26 |
76 |
|
T27 |
19402 |
| auto[1] |
auto[1] |
auto[0] |
1594779 |
1 |
|
|
T22 |
98238 |
|
T26 |
30 |
|
T27 |
33421 |
| auto[1] |
auto[1] |
auto[1] |
1088707 |
1 |
|
|
T22 |
60312 |
|
T26 |
43 |
|
T27 |
19646 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |