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Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7452078 1 T21 393 T22 329802 T23 65
auto[1] 5385218 1 T22 320118 T26 125 T27 107847


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10666903 1 T21 393 T22 531027 T23 65
auto[1] 2170393 1 T22 118893 T26 74 T27 38976


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7481288 1 T21 393 T22 333231 T23 65
auto[1] 5356008 1 T22 316689 T26 158 T27 107890


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1594291 1 T22 100727 T26 35 T27 33959
auto[1] auto[0] auto[1] 1085499 1 T22 59681 T26 46 T27 19219
auto[1] auto[1] auto[0] 1591324 1 T22 97069 T26 49 T27 34955
auto[1] auto[1] auto[1] 1084894 1 T22 59212 T26 28 T27 19757


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

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