Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468053 |
1 |
|
|
T21 |
393 |
|
T22 |
329954 |
|
T23 |
65 |
| auto[1] |
5369243 |
1 |
|
|
T22 |
319966 |
|
T26 |
197 |
|
T27 |
110423 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10647342 |
1 |
|
|
T21 |
393 |
|
T22 |
526704 |
|
T23 |
65 |
| auto[1] |
2189954 |
1 |
|
|
T22 |
123216 |
|
T26 |
72 |
|
T27 |
39266 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7426603 |
1 |
|
|
T21 |
393 |
|
T22 |
325689 |
|
T23 |
65 |
| auto[1] |
5410693 |
1 |
|
|
T22 |
324231 |
|
T26 |
120 |
|
T27 |
107215 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1613863 |
1 |
|
|
T22 |
102080 |
|
T26 |
17 |
|
T27 |
30752 |
| auto[1] |
auto[0] |
auto[1] |
1098424 |
1 |
|
|
T22 |
62366 |
|
T26 |
12 |
|
T27 |
17996 |
| auto[1] |
auto[1] |
auto[0] |
1606876 |
1 |
|
|
T22 |
98935 |
|
T26 |
31 |
|
T27 |
37197 |
| auto[1] |
auto[1] |
auto[1] |
1091530 |
1 |
|
|
T22 |
60850 |
|
T26 |
60 |
|
T27 |
21270 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |