Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447925 |
1 |
|
|
T21 |
393 |
|
T22 |
330444 |
|
T23 |
65 |
| auto[1] |
5389371 |
1 |
|
|
T22 |
319476 |
|
T26 |
155 |
|
T27 |
100524 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10650482 |
1 |
|
|
T21 |
393 |
|
T22 |
525487 |
|
T23 |
65 |
| auto[1] |
2186814 |
1 |
|
|
T22 |
124433 |
|
T26 |
60 |
|
T27 |
40466 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7424645 |
1 |
|
|
T21 |
393 |
|
T22 |
318452 |
|
T23 |
65 |
| auto[1] |
5412651 |
1 |
|
|
T22 |
331468 |
|
T26 |
133 |
|
T27 |
110334 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1613964 |
1 |
|
|
T22 |
105313 |
|
T26 |
32 |
|
T27 |
35986 |
| auto[1] |
auto[0] |
auto[1] |
1094419 |
1 |
|
|
T22 |
63258 |
|
T26 |
25 |
|
T27 |
20402 |
| auto[1] |
auto[1] |
auto[0] |
1611873 |
1 |
|
|
T22 |
101722 |
|
T26 |
41 |
|
T27 |
33882 |
| auto[1] |
auto[1] |
auto[1] |
1092395 |
1 |
|
|
T22 |
61175 |
|
T26 |
35 |
|
T27 |
20064 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |