Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447729 |
1 |
|
|
T21 |
393 |
|
T22 |
328146 |
|
T23 |
65 |
| auto[1] |
5389567 |
1 |
|
|
T22 |
321774 |
|
T26 |
149 |
|
T27 |
102576 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10658647 |
1 |
|
|
T21 |
393 |
|
T22 |
527264 |
|
T23 |
65 |
| auto[1] |
2178649 |
1 |
|
|
T22 |
122656 |
|
T26 |
84 |
|
T27 |
38450 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447840 |
1 |
|
|
T21 |
393 |
|
T22 |
324785 |
|
T23 |
65 |
| auto[1] |
5389456 |
1 |
|
|
T22 |
325135 |
|
T26 |
199 |
|
T27 |
105841 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1599748 |
1 |
|
|
T22 |
100864 |
|
T26 |
53 |
|
T27 |
34004 |
| auto[1] |
auto[0] |
auto[1] |
1090072 |
1 |
|
|
T22 |
61392 |
|
T26 |
33 |
|
T27 |
19041 |
| auto[1] |
auto[1] |
auto[0] |
1611059 |
1 |
|
|
T22 |
101615 |
|
T26 |
62 |
|
T27 |
33387 |
| auto[1] |
auto[1] |
auto[1] |
1088577 |
1 |
|
|
T22 |
61264 |
|
T26 |
51 |
|
T27 |
19409 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |