Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468721 |
1 |
|
|
T21 |
393 |
|
T22 |
328727 |
|
T23 |
65 |
| auto[1] |
5368575 |
1 |
|
|
T22 |
321193 |
|
T26 |
184 |
|
T27 |
107578 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12143708 |
1 |
|
|
T21 |
393 |
|
T22 |
608216 |
|
T23 |
65 |
| auto[1] |
693588 |
1 |
|
|
T22 |
41704 |
|
T26 |
10 |
|
T27 |
12597 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7426686 |
1 |
|
|
T21 |
393 |
|
T22 |
320683 |
|
T23 |
65 |
| auto[1] |
5410610 |
1 |
|
|
T22 |
329237 |
|
T26 |
129 |
|
T27 |
105790 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2372721 |
1 |
|
|
T22 |
144167 |
|
T26 |
52 |
|
T27 |
47251 |
| auto[1] |
auto[0] |
auto[1] |
349587 |
1 |
|
|
T22 |
20860 |
|
T26 |
5 |
|
T27 |
6494 |
| auto[1] |
auto[1] |
auto[0] |
2344301 |
1 |
|
|
T22 |
143366 |
|
T26 |
67 |
|
T27 |
45942 |
| auto[1] |
auto[1] |
auto[1] |
344001 |
1 |
|
|
T22 |
20844 |
|
T26 |
5 |
|
T27 |
6103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |