Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7440922 |
1 |
|
|
T21 |
393 |
|
T22 |
321635 |
|
T23 |
65 |
| auto[1] |
5396374 |
1 |
|
|
T22 |
328285 |
|
T26 |
176 |
|
T27 |
109057 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12146507 |
1 |
|
|
T21 |
393 |
|
T22 |
608684 |
|
T23 |
65 |
| auto[1] |
690789 |
1 |
|
|
T22 |
41236 |
|
T26 |
7 |
|
T27 |
13089 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7440949 |
1 |
|
|
T21 |
393 |
|
T22 |
326025 |
|
T23 |
65 |
| auto[1] |
5396347 |
1 |
|
|
T22 |
323895 |
|
T26 |
148 |
|
T27 |
108420 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2357845 |
1 |
|
|
T22 |
141169 |
|
T26 |
41 |
|
T27 |
47602 |
| auto[1] |
auto[0] |
auto[1] |
345720 |
1 |
|
|
T22 |
20816 |
|
T26 |
1 |
|
T27 |
6533 |
| auto[1] |
auto[1] |
auto[0] |
2347713 |
1 |
|
|
T22 |
141490 |
|
T26 |
100 |
|
T27 |
47729 |
| auto[1] |
auto[1] |
auto[1] |
345069 |
1 |
|
|
T22 |
20420 |
|
T26 |
6 |
|
T27 |
6556 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |