Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
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T766 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1311466637 Mar 17 03:01:58 PM PDT 24 Mar 17 03:01:59 PM PDT 24 15177145 ps
T46 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.21577998 Mar 17 03:02:15 PM PDT 24 Mar 17 03:02:16 PM PDT 24 127369939 ps
T767 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1811626950 Mar 17 03:02:02 PM PDT 24 Mar 17 03:02:04 PM PDT 24 81932185 ps
T768 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1389957620 Mar 17 03:02:09 PM PDT 24 Mar 17 03:02:12 PM PDT 24 202151885 ps
T769 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1809669342 Mar 17 03:02:05 PM PDT 24 Mar 17 03:02:08 PM PDT 24 1019649297 ps
T770 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2785257075 Mar 17 03:01:52 PM PDT 24 Mar 17 03:01:54 PM PDT 24 539200970 ps
T771 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3969087529 Mar 17 03:02:23 PM PDT 24 Mar 17 03:02:24 PM PDT 24 16454170 ps
T772 /workspace/coverage/cover_reg_top/22.gpio_intr_test.697674418 Mar 17 03:02:26 PM PDT 24 Mar 17 03:02:28 PM PDT 24 30588348 ps
T773 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3567748125 Mar 17 03:02:28 PM PDT 24 Mar 17 03:02:31 PM PDT 24 13161919 ps
T51 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1344236577 Mar 17 03:02:08 PM PDT 24 Mar 17 03:02:09 PM PDT 24 171598036 ps
T774 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.4110411400 Mar 17 03:02:24 PM PDT 24 Mar 17 03:02:27 PM PDT 24 30437925 ps
T775 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2182590822 Mar 17 03:02:27 PM PDT 24 Mar 17 03:02:30 PM PDT 24 38865236 ps
T776 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2255983421 Mar 17 03:02:17 PM PDT 24 Mar 17 03:02:17 PM PDT 24 12793305 ps
T98 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1607718378 Mar 17 03:02:09 PM PDT 24 Mar 17 03:02:10 PM PDT 24 41559793 ps
T87 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.921567444 Mar 17 03:02:06 PM PDT 24 Mar 17 03:02:07 PM PDT 24 17175981 ps
T777 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3853563126 Mar 17 03:01:53 PM PDT 24 Mar 17 03:01:55 PM PDT 24 519894806 ps
T778 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.202165399 Mar 17 03:02:08 PM PDT 24 Mar 17 03:02:09 PM PDT 24 38405459 ps
T45 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1373221098 Mar 17 03:01:57 PM PDT 24 Mar 17 03:01:58 PM PDT 24 81062066 ps
T779 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2526909528 Mar 17 03:02:29 PM PDT 24 Mar 17 03:02:32 PM PDT 24 16682569 ps
T780 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.840173847 Mar 17 03:01:57 PM PDT 24 Mar 17 03:01:59 PM PDT 24 382848695 ps
T781 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1405082192 Mar 17 03:02:29 PM PDT 24 Mar 17 03:02:32 PM PDT 24 51372031 ps
T88 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2306063879 Mar 17 03:02:04 PM PDT 24 Mar 17 03:02:05 PM PDT 24 22402939 ps
T105 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1452130215 Mar 17 03:02:09 PM PDT 24 Mar 17 03:02:11 PM PDT 24 136245019 ps
T782 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2633011439 Mar 17 03:01:53 PM PDT 24 Mar 17 03:01:56 PM PDT 24 219027187 ps
T783 /workspace/coverage/cover_reg_top/26.gpio_intr_test.709401988 Mar 17 03:02:24 PM PDT 24 Mar 17 03:02:26 PM PDT 24 78705730 ps
T784 /workspace/coverage/cover_reg_top/48.gpio_intr_test.4038892542 Mar 17 03:02:30 PM PDT 24 Mar 17 03:02:32 PM PDT 24 17224312 ps
T47 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4135181913 Mar 17 03:02:06 PM PDT 24 Mar 17 03:02:08 PM PDT 24 227187179 ps
T99 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1586107978 Mar 17 03:02:09 PM PDT 24 Mar 17 03:02:10 PM PDT 24 30427619 ps
T785 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2267174521 Mar 17 03:02:05 PM PDT 24 Mar 17 03:02:05 PM PDT 24 13303438 ps
T49 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.20806235 Mar 17 03:02:06 PM PDT 24 Mar 17 03:02:08 PM PDT 24 1664889497 ps
T786 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2763623144 Mar 17 03:02:09 PM PDT 24 Mar 17 03:02:10 PM PDT 24 28326422 ps
T787 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1426290008 Mar 17 03:01:57 PM PDT 24 Mar 17 03:01:58 PM PDT 24 15026699 ps
T788 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.475805476 Mar 17 03:02:08 PM PDT 24 Mar 17 03:02:09 PM PDT 24 124931184 ps
T789 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2294098340 Mar 17 03:02:30 PM PDT 24 Mar 17 03:02:32 PM PDT 24 21488584 ps
T50 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.226681467 Mar 17 03:02:08 PM PDT 24 Mar 17 03:02:10 PM PDT 24 42441192 ps
T790 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3899302635 Mar 17 03:01:56 PM PDT 24 Mar 17 03:01:57 PM PDT 24 33469026 ps
T791 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1810702461 Mar 17 03:02:13 PM PDT 24 Mar 17 03:02:15 PM PDT 24 478626850 ps
T792 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1386725119 Mar 17 03:02:11 PM PDT 24 Mar 17 03:02:12 PM PDT 24 16808179 ps
T793 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1673947210 Mar 17 03:02:32 PM PDT 24 Mar 17 03:02:33 PM PDT 24 47294383 ps
T794 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.892067491 Mar 17 03:02:19 PM PDT 24 Mar 17 03:02:20 PM PDT 24 55007252 ps
T795 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1841755590 Mar 17 03:02:02 PM PDT 24 Mar 17 03:02:04 PM PDT 24 65836637 ps
T796 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3559065488 Mar 17 03:02:03 PM PDT 24 Mar 17 03:02:04 PM PDT 24 39667250 ps
T103 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2603035400 Mar 17 03:02:29 PM PDT 24 Mar 17 03:02:32 PM PDT 24 83162350 ps
T797 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2433000048 Mar 17 03:01:51 PM PDT 24 Mar 17 03:01:53 PM PDT 24 38573703 ps
T798 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1925160640 Mar 17 03:01:53 PM PDT 24 Mar 17 03:01:55 PM PDT 24 33453863 ps
T799 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.852538473 Mar 17 03:02:04 PM PDT 24 Mar 17 03:02:05 PM PDT 24 441453652 ps
T800 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.903770394 Mar 17 03:01:57 PM PDT 24 Mar 17 03:01:57 PM PDT 24 18069696 ps
T104 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.657041926 Mar 17 03:01:57 PM PDT 24 Mar 17 03:01:58 PM PDT 24 643891660 ps
T801 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1201841824 Mar 17 03:02:26 PM PDT 24 Mar 17 03:02:28 PM PDT 24 88031100 ps
T89 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3877213967 Mar 17 03:02:02 PM PDT 24 Mar 17 03:02:03 PM PDT 24 31913642 ps
T802 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1023649378 Mar 17 03:02:07 PM PDT 24 Mar 17 03:02:09 PM PDT 24 165943889 ps
T803 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3673428553 Mar 17 03:02:11 PM PDT 24 Mar 17 03:02:12 PM PDT 24 179540160 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3283435884 Mar 17 03:01:53 PM PDT 24 Mar 17 03:01:54 PM PDT 24 23530186 ps
T805 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2330050329 Mar 17 03:02:30 PM PDT 24 Mar 17 03:02:32 PM PDT 24 15543001 ps
T806 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2702328431 Mar 17 03:01:59 PM PDT 24 Mar 17 03:02:01 PM PDT 24 14750896 ps
T807 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2693322893 Mar 17 03:02:04 PM PDT 24 Mar 17 03:02:06 PM PDT 24 30948524 ps
T808 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4011722571 Mar 17 03:02:15 PM PDT 24 Mar 17 03:02:18 PM PDT 24 820838072 ps
T809 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2402092293 Mar 17 03:02:18 PM PDT 24 Mar 17 03:02:20 PM PDT 24 320906097 ps
T810 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1977575260 Mar 17 03:02:27 PM PDT 24 Mar 17 03:02:30 PM PDT 24 19955530 ps
T811 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3080894471 Mar 17 03:02:09 PM PDT 24 Mar 17 03:02:10 PM PDT 24 33810019 ps
T812 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3146399200 Mar 17 03:01:53 PM PDT 24 Mar 17 03:01:56 PM PDT 24 112654405 ps
T813 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2596217058 Mar 17 03:02:06 PM PDT 24 Mar 17 03:02:06 PM PDT 24 14731629 ps
T814 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.541612494 Mar 17 03:02:17 PM PDT 24 Mar 17 03:02:18 PM PDT 24 34677274 ps
T815 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1917835487 Mar 17 03:02:29 PM PDT 24 Mar 17 03:02:32 PM PDT 24 41560964 ps
T816 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2190757364 Mar 17 03:02:19 PM PDT 24 Mar 17 03:02:20 PM PDT 24 81160252 ps
T817 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3620019171 Mar 17 03:02:13 PM PDT 24 Mar 17 03:02:14 PM PDT 24 92512219 ps
T818 /workspace/coverage/cover_reg_top/12.gpio_intr_test.932541378 Mar 17 03:02:10 PM PDT 24 Mar 17 03:02:11 PM PDT 24 30272493 ps
T819 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2397606723 Mar 17 03:02:03 PM PDT 24 Mar 17 03:02:04 PM PDT 24 11985347 ps
T820 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2278926287 Mar 17 03:02:29 PM PDT 24 Mar 17 03:02:31 PM PDT 24 23435090 ps
T821 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3112939824 Mar 17 03:01:53 PM PDT 24 Mar 17 03:01:54 PM PDT 24 428373828 ps
T822 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2321453035 Mar 17 03:02:13 PM PDT 24 Mar 17 03:02:15 PM PDT 24 135693252 ps
T823 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2293724981 Mar 17 03:02:30 PM PDT 24 Mar 17 03:02:32 PM PDT 24 15696256 ps
T824 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2779354566 Mar 17 03:01:58 PM PDT 24 Mar 17 03:01:59 PM PDT 24 108443373 ps
T825 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2798116912 Mar 17 03:02:30 PM PDT 24 Mar 17 03:02:32 PM PDT 24 16093581 ps
T826 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2922978054 Mar 17 03:02:05 PM PDT 24 Mar 17 03:02:07 PM PDT 24 88910089 ps
T827 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.735055271 Mar 17 03:02:25 PM PDT 24 Mar 17 03:02:27 PM PDT 24 76026891 ps
T90 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2883776514 Mar 17 03:01:53 PM PDT 24 Mar 17 03:01:55 PM PDT 24 136421674 ps
T828 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3067097482 Mar 17 03:02:17 PM PDT 24 Mar 17 03:02:18 PM PDT 24 127414445 ps
T829 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.56534534 Mar 17 03:02:24 PM PDT 24 Mar 17 03:02:25 PM PDT 24 502240931 ps
T830 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3112899579 Mar 17 03:02:04 PM PDT 24 Mar 17 03:02:05 PM PDT 24 39617262 ps
T831 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1182478237 Mar 17 03:02:30 PM PDT 24 Mar 17 03:02:32 PM PDT 24 34574557 ps
T832 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3269975830 Mar 17 03:01:51 PM PDT 24 Mar 17 03:01:53 PM PDT 24 37869191 ps
T833 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2950230674 Mar 17 03:02:12 PM PDT 24 Mar 17 03:02:12 PM PDT 24 31026110 ps
T834 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3251766076 Mar 17 03:02:15 PM PDT 24 Mar 17 03:02:15 PM PDT 24 44066725 ps
T835 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2017749820 Mar 17 03:01:52 PM PDT 24 Mar 17 03:01:54 PM PDT 24 103310058 ps
T836 /workspace/coverage/cover_reg_top/4.gpio_intr_test.154394130 Mar 17 03:02:02 PM PDT 24 Mar 17 03:02:03 PM PDT 24 41202190 ps
T837 /workspace/coverage/cover_reg_top/39.gpio_intr_test.716564325 Mar 17 03:02:33 PM PDT 24 Mar 17 03:02:34 PM PDT 24 30496801 ps
T838 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1917465125 Mar 17 03:02:03 PM PDT 24 Mar 17 03:02:04 PM PDT 24 26093196 ps
T839 /workspace/coverage/cover_reg_top/28.gpio_intr_test.4178759458 Mar 17 03:02:31 PM PDT 24 Mar 17 03:02:32 PM PDT 24 15253460 ps
T840 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1536570496 Mar 17 03:02:13 PM PDT 24 Mar 17 03:02:14 PM PDT 24 20414682 ps
T841 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712569138 Mar 17 01:46:47 PM PDT 24 Mar 17 01:46:49 PM PDT 24 85761287 ps
T842 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3917084901 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:43 PM PDT 24 92868154 ps
T843 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.869084143 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:43 PM PDT 24 54072042 ps
T844 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2177664893 Mar 17 01:46:34 PM PDT 24 Mar 17 01:46:35 PM PDT 24 79886809 ps
T845 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.529257029 Mar 17 01:46:42 PM PDT 24 Mar 17 01:46:46 PM PDT 24 207002414 ps
T846 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.479854972 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:43 PM PDT 24 333630557 ps
T847 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.11315512 Mar 17 01:46:49 PM PDT 24 Mar 17 01:46:50 PM PDT 24 51148044 ps
T848 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2597610203 Mar 17 01:46:42 PM PDT 24 Mar 17 01:46:45 PM PDT 24 146634815 ps
T849 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3577883941 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:42 PM PDT 24 33717635 ps
T850 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1647610941 Mar 17 01:46:42 PM PDT 24 Mar 17 01:46:46 PM PDT 24 42785077 ps
T851 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3808334473 Mar 17 01:46:45 PM PDT 24 Mar 17 01:46:47 PM PDT 24 165854670 ps
T852 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3276347818 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:46 PM PDT 24 55665528 ps
T853 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.474229347 Mar 17 01:46:48 PM PDT 24 Mar 17 01:46:50 PM PDT 24 376649857 ps
T854 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1000150015 Mar 17 01:46:51 PM PDT 24 Mar 17 01:46:52 PM PDT 24 136932218 ps
T855 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3202735054 Mar 17 01:46:52 PM PDT 24 Mar 17 01:46:54 PM PDT 24 78853832 ps
T856 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1515714837 Mar 17 01:46:54 PM PDT 24 Mar 17 01:46:55 PM PDT 24 259385823 ps
T857 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3608630351 Mar 17 01:46:48 PM PDT 24 Mar 17 01:46:49 PM PDT 24 261416074 ps
T858 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.117900747 Mar 17 01:46:47 PM PDT 24 Mar 17 01:46:49 PM PDT 24 533481384 ps
T859 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1438592284 Mar 17 01:46:51 PM PDT 24 Mar 17 01:46:53 PM PDT 24 166471551 ps
T860 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.259387173 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:47 PM PDT 24 211288302 ps
T861 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2270196443 Mar 17 01:46:54 PM PDT 24 Mar 17 01:46:56 PM PDT 24 41687628 ps
T862 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.349313028 Mar 17 01:46:51 PM PDT 24 Mar 17 01:46:53 PM PDT 24 56471874 ps
T863 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.210572962 Mar 17 01:46:46 PM PDT 24 Mar 17 01:46:48 PM PDT 24 27169619 ps
T864 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.379937000 Mar 17 01:46:35 PM PDT 24 Mar 17 01:46:37 PM PDT 24 96841945 ps
T865 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1276326640 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:42 PM PDT 24 252884413 ps
T866 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.483731478 Mar 17 01:46:55 PM PDT 24 Mar 17 01:46:56 PM PDT 24 77668194 ps
T867 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1056005070 Mar 17 01:46:49 PM PDT 24 Mar 17 01:46:50 PM PDT 24 118175452 ps
T868 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513593451 Mar 17 01:46:49 PM PDT 24 Mar 17 01:46:50 PM PDT 24 467327045 ps
T869 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2543376533 Mar 17 01:46:37 PM PDT 24 Mar 17 01:46:39 PM PDT 24 271859147 ps
T870 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.837950670 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:43 PM PDT 24 449347581 ps
T871 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1777611854 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:43 PM PDT 24 307698637 ps
T872 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1102023192 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:41 PM PDT 24 37219071 ps
T873 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2258996908 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:46 PM PDT 24 63412516 ps
T874 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4167347132 Mar 17 01:46:45 PM PDT 24 Mar 17 01:46:48 PM PDT 24 47372047 ps
T875 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3456075294 Mar 17 01:46:56 PM PDT 24 Mar 17 01:46:57 PM PDT 24 107955980 ps
T876 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1207693998 Mar 17 01:46:43 PM PDT 24 Mar 17 01:46:46 PM PDT 24 93406508 ps
T877 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.428344255 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:37 PM PDT 24 192322392 ps
T878 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.282386592 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:47 PM PDT 24 62097350 ps
T879 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3054072130 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:46 PM PDT 24 62960779 ps
T880 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.579109273 Mar 17 01:46:46 PM PDT 24 Mar 17 01:46:48 PM PDT 24 48017281 ps
T881 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1555746023 Mar 17 01:46:43 PM PDT 24 Mar 17 01:46:46 PM PDT 24 81554300 ps
T882 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3373475987 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:44 PM PDT 24 63664384 ps
T883 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1108268043 Mar 17 01:46:35 PM PDT 24 Mar 17 01:46:36 PM PDT 24 136045255 ps
T884 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1028949219 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:40 PM PDT 24 1201647228 ps
T885 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2835839592 Mar 17 01:46:43 PM PDT 24 Mar 17 01:46:46 PM PDT 24 28618963 ps
T886 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3669978859 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:42 PM PDT 24 520000373 ps
T887 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2739571498 Mar 17 01:46:43 PM PDT 24 Mar 17 01:46:46 PM PDT 24 371633615 ps
T888 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3592934793 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:44 PM PDT 24 119252878 ps
T889 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2913702004 Mar 17 01:46:50 PM PDT 24 Mar 17 01:46:51 PM PDT 24 39135235 ps
T890 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.750721020 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:43 PM PDT 24 44512664 ps
T891 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2365826588 Mar 17 01:46:54 PM PDT 24 Mar 17 01:46:55 PM PDT 24 158495110 ps
T892 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2989025004 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:43 PM PDT 24 312171440 ps
T893 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2186060384 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:43 PM PDT 24 336283682 ps
T894 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1991790570 Mar 17 01:46:50 PM PDT 24 Mar 17 01:46:51 PM PDT 24 57205053 ps
T895 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1459239988 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:46 PM PDT 24 63912221 ps
T896 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2274248831 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:38 PM PDT 24 40842666 ps
T897 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999119364 Mar 17 01:46:45 PM PDT 24 Mar 17 01:46:48 PM PDT 24 32934862 ps
T898 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1793623649 Mar 17 01:46:50 PM PDT 24 Mar 17 01:46:51 PM PDT 24 95082767 ps
T899 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3733111380 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:42 PM PDT 24 58163982 ps
T900 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2069736617 Mar 17 01:46:45 PM PDT 24 Mar 17 01:46:47 PM PDT 24 69457247 ps
T901 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1905864889 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:40 PM PDT 24 45744363 ps
T902 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1757923280 Mar 17 01:46:50 PM PDT 24 Mar 17 01:46:51 PM PDT 24 208011511 ps
T903 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1565983236 Mar 17 01:46:49 PM PDT 24 Mar 17 01:46:50 PM PDT 24 57260117 ps
T904 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3353087682 Mar 17 01:46:47 PM PDT 24 Mar 17 01:46:49 PM PDT 24 34379113 ps
T905 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2214206074 Mar 17 01:46:45 PM PDT 24 Mar 17 01:46:47 PM PDT 24 30028362 ps
T906 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2145542954 Mar 17 01:46:35 PM PDT 24 Mar 17 01:46:36 PM PDT 24 41457845 ps
T907 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.765117152 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:43 PM PDT 24 192394237 ps
T908 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1630689847 Mar 17 01:46:42 PM PDT 24 Mar 17 01:46:45 PM PDT 24 145095080 ps
T909 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3922486945 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:46 PM PDT 24 78836592 ps
T910 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3445006735 Mar 17 01:46:51 PM PDT 24 Mar 17 01:46:53 PM PDT 24 44976885 ps
T911 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.281258299 Mar 17 01:46:56 PM PDT 24 Mar 17 01:46:58 PM PDT 24 165761073 ps
T912 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.289424260 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:43 PM PDT 24 223390006 ps
T913 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2343158710 Mar 17 01:46:48 PM PDT 24 Mar 17 01:46:49 PM PDT 24 166089771 ps
T914 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3298554415 Mar 17 01:46:43 PM PDT 24 Mar 17 01:46:45 PM PDT 24 77955370 ps
T915 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1148267337 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:47 PM PDT 24 367088569 ps
T916 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3391588821 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:46 PM PDT 24 313373938 ps
T917 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1188645552 Mar 17 01:46:42 PM PDT 24 Mar 17 01:46:45 PM PDT 24 38354444 ps
T918 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4118531047 Mar 17 01:46:47 PM PDT 24 Mar 17 01:46:49 PM PDT 24 275587869 ps
T919 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3851025096 Mar 17 01:46:44 PM PDT 24 Mar 17 01:46:47 PM PDT 24 321590798 ps
T920 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224886154 Mar 17 01:46:42 PM PDT 24 Mar 17 01:46:45 PM PDT 24 56264594 ps
T921 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.57441798 Mar 17 01:46:50 PM PDT 24 Mar 17 01:46:51 PM PDT 24 37622131 ps
T922 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1662736753 Mar 17 01:46:46 PM PDT 24 Mar 17 01:46:48 PM PDT 24 203874870 ps
T923 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2949151321 Mar 17 01:46:47 PM PDT 24 Mar 17 01:46:48 PM PDT 24 25798019 ps
T924 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1901837160 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:44 PM PDT 24 39971491 ps
T925 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3706903283 Mar 17 01:46:46 PM PDT 24 Mar 17 01:46:49 PM PDT 24 111148952 ps
T926 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4214567694 Mar 17 01:46:42 PM PDT 24 Mar 17 01:46:46 PM PDT 24 718550196 ps
T927 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4029204217 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:43 PM PDT 24 94836561 ps
T928 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4212503151 Mar 17 01:46:50 PM PDT 24 Mar 17 01:46:51 PM PDT 24 135606130 ps
T929 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865098376 Mar 17 01:46:45 PM PDT 24 Mar 17 01:46:48 PM PDT 24 47188950 ps
T930 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3591827986 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:38 PM PDT 24 55457029 ps
T931 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1149794598 Mar 17 01:46:50 PM PDT 24 Mar 17 01:46:52 PM PDT 24 223041018 ps
T932 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4123793093 Mar 17 01:46:48 PM PDT 24 Mar 17 01:46:49 PM PDT 24 33684752 ps
T933 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3166346797 Mar 17 01:46:37 PM PDT 24 Mar 17 01:46:38 PM PDT 24 113355498 ps
T934 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.85018539 Mar 17 01:46:46 PM PDT 24 Mar 17 01:46:48 PM PDT 24 50080628 ps
T935 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2680423405 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:44 PM PDT 24 54821674 ps
T936 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1803302497 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:44 PM PDT 24 694388407 ps
T937 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.457499275 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:43 PM PDT 24 89979110 ps
T938 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2372544035 Mar 17 01:46:52 PM PDT 24 Mar 17 01:46:55 PM PDT 24 107461558 ps
T939 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1266706906 Mar 17 01:46:37 PM PDT 24 Mar 17 01:46:39 PM PDT 24 94590843 ps
T940 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4165531435 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:43 PM PDT 24 162485429 ps

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1408106063
Short name T27
Test name
Test status
Simulation time 30857325423 ps
CPU time 547.25 seconds
Started Mar 17 02:51:17 PM PDT 24
Finished Mar 17 03:00:25 PM PDT 24
Peak memory 198188 kb
Host smart-6ea86663-c5d0-4ad8-869e-2a4549464b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1408106063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1408106063
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1624876337
Short name T106
Test name
Test status
Simulation time 85126800 ps
CPU time 0.98 seconds
Started Mar 17 02:52:34 PM PDT 24
Finished Mar 17 02:52:35 PM PDT 24
Peak memory 195940 kb
Host smart-32d7c308-e0a3-47d5-bf04-ac814811a585
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624876337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1624876337
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_alert_test.4204886244
Short name T30
Test name
Test status
Simulation time 25377416 ps
CPU time 0.6 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 194164 kb
Host smart-5f0ab6e6-0336-423c-9430-b6afde37aebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204886244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.4204886244
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.87110720
Short name T38
Test name
Test status
Simulation time 495102096 ps
CPU time 1.5 seconds
Started Mar 17 03:02:18 PM PDT 24
Finished Mar 17 03:02:20 PM PDT 24
Peak memory 198008 kb
Host smart-4a3d2c90-6130-44c0-92be-d587105b5959
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87110720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.gpio_tl_intg_err.87110720
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.4062725103
Short name T2
Test name
Test status
Simulation time 2293489174 ps
CPU time 6.59 seconds
Started Mar 17 02:51:12 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 198028 kb
Host smart-f8e98ee2-7b53-4fb6-8465-7f5a6de3e931
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062725103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.4062725103
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.66226194
Short name T83
Test name
Test status
Simulation time 14173524 ps
CPU time 0.58 seconds
Started Mar 17 03:01:59 PM PDT 24
Finished Mar 17 03:02:01 PM PDT 24
Peak memory 193320 kb
Host smart-3ca9dba1-6da8-4748-822d-9e617c5f3dea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66226194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_c
sr_rw.66226194
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1675306976
Short name T42
Test name
Test status
Simulation time 242639523 ps
CPU time 0.89 seconds
Started Mar 17 02:51:10 PM PDT 24
Finished Mar 17 02:51:11 PM PDT 24
Peak memory 213792 kb
Host smart-9173fa03-cc3c-4b8f-b55c-d7c65f221db4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675306976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1675306976
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2210792095
Short name T79
Test name
Test status
Simulation time 18679443 ps
CPU time 0.76 seconds
Started Mar 17 03:02:05 PM PDT 24
Finished Mar 17 03:02:05 PM PDT 24
Peak memory 196480 kb
Host smart-e69b691c-93fb-4cf7-94de-ab37d85817ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210792095 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2210792095
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4135181913
Short name T47
Test name
Test status
Simulation time 227187179 ps
CPU time 1.45 seconds
Started Mar 17 03:02:06 PM PDT 24
Finished Mar 17 03:02:08 PM PDT 24
Peak memory 198112 kb
Host smart-a788ae40-0040-498b-bbc5-9fb6a4061886
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135181913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.4135181913
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.657041926
Short name T104
Test name
Test status
Simulation time 643891660 ps
CPU time 1.2 seconds
Started Mar 17 03:01:57 PM PDT 24
Finished Mar 17 03:01:58 PM PDT 24
Peak memory 198016 kb
Host smart-7dc66dab-1a7a-4e70-8aa1-718a4670b3eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657041926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.657041926
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.554043852
Short name T204
Test name
Test status
Simulation time 133857448 ps
CPU time 1.59 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 198148 kb
Host smart-007101b2-8e3b-4c67-bc75-159ba3a7aef4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554043852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.554043852
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3877213967
Short name T89
Test name
Test status
Simulation time 31913642 ps
CPU time 0.9 seconds
Started Mar 17 03:02:02 PM PDT 24
Finished Mar 17 03:02:03 PM PDT 24
Peak memory 195824 kb
Host smart-e06721dd-ed10-461a-b010-9c41dc2f9bde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877213967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3877213967
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2785257075
Short name T770
Test name
Test status
Simulation time 539200970 ps
CPU time 1.51 seconds
Started Mar 17 03:01:52 PM PDT 24
Finished Mar 17 03:01:54 PM PDT 24
Peak memory 196832 kb
Host smart-65a7667e-732e-4309-9236-6a96d98d6af4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785257075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2785257075
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2231311636
Short name T82
Test name
Test status
Simulation time 14729286 ps
CPU time 0.66 seconds
Started Mar 17 03:01:55 PM PDT 24
Finished Mar 17 03:01:57 PM PDT 24
Peak memory 195328 kb
Host smart-18c25698-cb81-4fc6-a06a-2c419ca6c093
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231311636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2231311636
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3269975830
Short name T832
Test name
Test status
Simulation time 37869191 ps
CPU time 0.71 seconds
Started Mar 17 03:01:51 PM PDT 24
Finished Mar 17 03:01:53 PM PDT 24
Peak memory 197648 kb
Host smart-0592fa3f-0b82-43d2-b71e-84e08f42b12d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269975830 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3269975830
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2251371755
Short name T80
Test name
Test status
Simulation time 101665697 ps
CPU time 0.59 seconds
Started Mar 17 03:01:59 PM PDT 24
Finished Mar 17 03:02:00 PM PDT 24
Peak memory 194736 kb
Host smart-042d7e06-14b9-4d14-b37f-fc6eb17deac6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251371755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2251371755
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1935115419
Short name T727
Test name
Test status
Simulation time 11783284 ps
CPU time 0.58 seconds
Started Mar 17 03:01:54 PM PDT 24
Finished Mar 17 03:01:56 PM PDT 24
Peak memory 194344 kb
Host smart-edcd525d-ce8b-4534-96b8-c488362081fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935115419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1935115419
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3283435884
Short name T804
Test name
Test status
Simulation time 23530186 ps
CPU time 0.71 seconds
Started Mar 17 03:01:53 PM PDT 24
Finished Mar 17 03:01:54 PM PDT 24
Peak memory 195144 kb
Host smart-8a0571e5-d113-43da-86bf-64be58677cc5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283435884 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3283435884
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3146399200
Short name T812
Test name
Test status
Simulation time 112654405 ps
CPU time 2.5 seconds
Started Mar 17 03:01:53 PM PDT 24
Finished Mar 17 03:01:56 PM PDT 24
Peak memory 198152 kb
Host smart-93d15c67-cb13-44cf-a9a1-b11306f59dee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146399200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3146399200
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2633011439
Short name T782
Test name
Test status
Simulation time 219027187 ps
CPU time 1.19 seconds
Started Mar 17 03:01:53 PM PDT 24
Finished Mar 17 03:01:56 PM PDT 24
Peak memory 197960 kb
Host smart-a661a90d-b314-4e29-b3c4-93b6949a823c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633011439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2633011439
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.921567444
Short name T87
Test name
Test status
Simulation time 17175981 ps
CPU time 0.76 seconds
Started Mar 17 03:02:06 PM PDT 24
Finished Mar 17 03:02:07 PM PDT 24
Peak memory 195752 kb
Host smart-41d7048c-80f2-45ff-a84a-ff81e4cc901d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921567444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.921567444
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2883776514
Short name T90
Test name
Test status
Simulation time 136421674 ps
CPU time 1.58 seconds
Started Mar 17 03:01:53 PM PDT 24
Finished Mar 17 03:01:55 PM PDT 24
Peak memory 197112 kb
Host smart-af61d6f6-39e8-427f-9024-46cf37227e41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883776514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2883776514
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4115650059
Short name T77
Test name
Test status
Simulation time 67283199 ps
CPU time 0.62 seconds
Started Mar 17 03:01:54 PM PDT 24
Finished Mar 17 03:01:55 PM PDT 24
Peak memory 194756 kb
Host smart-d5b36f71-cc36-4b82-8f49-e6ee3f56c7bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115650059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.4115650059
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.709469155
Short name T751
Test name
Test status
Simulation time 59223593 ps
CPU time 0.89 seconds
Started Mar 17 03:02:00 PM PDT 24
Finished Mar 17 03:02:01 PM PDT 24
Peak memory 198060 kb
Host smart-95345740-9622-4386-81d1-853b86fa22bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709469155 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.709469155
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4036302397
Short name T752
Test name
Test status
Simulation time 23170600 ps
CPU time 0.6 seconds
Started Mar 17 03:01:59 PM PDT 24
Finished Mar 17 03:02:01 PM PDT 24
Peak memory 195420 kb
Host smart-a1172324-c17e-447b-876f-efa36ba64cf5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036302397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4036302397
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1925160640
Short name T798
Test name
Test status
Simulation time 33453863 ps
CPU time 0.62 seconds
Started Mar 17 03:01:53 PM PDT 24
Finished Mar 17 03:01:55 PM PDT 24
Peak memory 194412 kb
Host smart-ed288ee2-fd22-4a1e-9fd9-1a37f00376ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925160640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1925160640
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3112939824
Short name T821
Test name
Test status
Simulation time 428373828 ps
CPU time 0.85 seconds
Started Mar 17 03:01:53 PM PDT 24
Finished Mar 17 03:01:54 PM PDT 24
Peak memory 196356 kb
Host smart-fd807687-751f-49e8-b866-53c1300cd4c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112939824 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3112939824
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3853563126
Short name T777
Test name
Test status
Simulation time 519894806 ps
CPU time 2.31 seconds
Started Mar 17 03:01:53 PM PDT 24
Finished Mar 17 03:01:55 PM PDT 24
Peak memory 198008 kb
Host smart-84811d98-9121-4a24-a54d-0bfd77a1a1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853563126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3853563126
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1587265206
Short name T40
Test name
Test status
Simulation time 143949957 ps
CPU time 1.38 seconds
Started Mar 17 03:01:51 PM PDT 24
Finished Mar 17 03:01:53 PM PDT 24
Peak memory 198088 kb
Host smart-8f884a7f-eece-4b45-a344-41306171855a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587265206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1587265206
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.202165399
Short name T778
Test name
Test status
Simulation time 38405459 ps
CPU time 1.02 seconds
Started Mar 17 03:02:08 PM PDT 24
Finished Mar 17 03:02:09 PM PDT 24
Peak memory 198032 kb
Host smart-21dd6825-80d5-4acd-bc3e-dc987f169c66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202165399 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.202165399
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1386725119
Short name T792
Test name
Test status
Simulation time 16808179 ps
CPU time 0.65 seconds
Started Mar 17 03:02:11 PM PDT 24
Finished Mar 17 03:02:12 PM PDT 24
Peak memory 195552 kb
Host smart-8fc4537a-3767-46a3-b3a8-0fcf739f7f7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386725119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1386725119
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.191448963
Short name T758
Test name
Test status
Simulation time 49091071 ps
CPU time 0.66 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 194436 kb
Host smart-85a999af-cc26-4aee-a3e3-d417186d06ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191448963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.191448963
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1586107978
Short name T99
Test name
Test status
Simulation time 30427619 ps
CPU time 0.77 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 196896 kb
Host smart-2a24b0c1-73ae-4c47-a8ec-a8d34813e9e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586107978 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1586107978
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1400145476
Short name T739
Test name
Test status
Simulation time 302103526 ps
CPU time 1.59 seconds
Started Mar 17 03:02:07 PM PDT 24
Finished Mar 17 03:02:09 PM PDT 24
Peak memory 198008 kb
Host smart-6c85da84-4f3e-45a3-927f-be0c9ab9766e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400145476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1400145476
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.226681467
Short name T50
Test name
Test status
Simulation time 42441192 ps
CPU time 0.91 seconds
Started Mar 17 03:02:08 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 197972 kb
Host smart-b81657c2-e528-4a1c-97d6-cadb7670de41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226681467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.226681467
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2629263455
Short name T736
Test name
Test status
Simulation time 40873750 ps
CPU time 1.03 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:11 PM PDT 24
Peak memory 198024 kb
Host smart-54b58e53-74f8-48cc-b956-ecfee0ddb7dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629263455 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2629263455
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.277991848
Short name T765
Test name
Test status
Simulation time 14693543 ps
CPU time 0.63 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 194880 kb
Host smart-4c5c9355-9ce8-49ae-afc8-0daf142e0b4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277991848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.277991848
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.4116643750
Short name T726
Test name
Test status
Simulation time 52679919 ps
CPU time 0.62 seconds
Started Mar 17 03:02:11 PM PDT 24
Finished Mar 17 03:02:11 PM PDT 24
Peak memory 193760 kb
Host smart-eea0e1a1-8fec-4302-a4f9-aa7dc976c3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116643750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.4116643750
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1023649378
Short name T802
Test name
Test status
Simulation time 165943889 ps
CPU time 0.73 seconds
Started Mar 17 03:02:07 PM PDT 24
Finished Mar 17 03:02:09 PM PDT 24
Peak memory 194900 kb
Host smart-cc9a1636-e6e2-404d-979d-b462737ab985
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023649378 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1023649378
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3152601556
Short name T757
Test name
Test status
Simulation time 93213315 ps
CPU time 2.31 seconds
Started Mar 17 03:02:07 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 198036 kb
Host smart-2089b226-5922-4f0b-a74e-597180823326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152601556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3152601556
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1344236577
Short name T51
Test name
Test status
Simulation time 171598036 ps
CPU time 0.85 seconds
Started Mar 17 03:02:08 PM PDT 24
Finished Mar 17 03:02:09 PM PDT 24
Peak memory 197252 kb
Host smart-9bedb535-ef2a-49a0-bd3b-9e2df5bb155b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344236577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1344236577
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3653517210
Short name T747
Test name
Test status
Simulation time 33966027 ps
CPU time 0.93 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:11 PM PDT 24
Peak memory 197976 kb
Host smart-fc58f285-acd6-4c84-bfae-64c5425c721f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653517210 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3653517210
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1562948810
Short name T744
Test name
Test status
Simulation time 16086556 ps
CPU time 0.58 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 194696 kb
Host smart-aca510b8-74bc-49d0-9c4a-cc92dbfe028b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562948810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1562948810
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.932541378
Short name T818
Test name
Test status
Simulation time 30272493 ps
CPU time 0.67 seconds
Started Mar 17 03:02:10 PM PDT 24
Finished Mar 17 03:02:11 PM PDT 24
Peak memory 194372 kb
Host smart-eca96edc-2ac2-4ffa-aa6d-544cf55e409d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932541378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.932541378
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2763623144
Short name T786
Test name
Test status
Simulation time 28326422 ps
CPU time 0.74 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 196136 kb
Host smart-1d39a90a-e642-4a5f-9563-4e27e7735dde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763623144 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2763623144
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1389957620
Short name T768
Test name
Test status
Simulation time 202151885 ps
CPU time 2.32 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:12 PM PDT 24
Peak memory 198104 kb
Host smart-0ac9dec6-2a51-4c3e-ac81-e7620fe5499c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389957620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1389957620
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1452130215
Short name T105
Test name
Test status
Simulation time 136245019 ps
CPU time 1.25 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:11 PM PDT 24
Peak memory 198012 kb
Host smart-5fc4d869-eb7c-4ada-a7f9-36bc50d449ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452130215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1452130215
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2642907120
Short name T748
Test name
Test status
Simulation time 26616015 ps
CPU time 1.32 seconds
Started Mar 17 03:02:16 PM PDT 24
Finished Mar 17 03:02:17 PM PDT 24
Peak memory 198164 kb
Host smart-aa695d4f-1830-470f-84fb-b17d8ae48e9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642907120 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2642907120
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2375548661
Short name T84
Test name
Test status
Simulation time 46654815 ps
CPU time 0.66 seconds
Started Mar 17 03:02:15 PM PDT 24
Finished Mar 17 03:02:15 PM PDT 24
Peak memory 194760 kb
Host smart-48613479-c8f4-4e70-8992-36d5ffea304a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375548661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2375548661
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3695231120
Short name T725
Test name
Test status
Simulation time 46397851 ps
CPU time 0.6 seconds
Started Mar 17 03:02:12 PM PDT 24
Finished Mar 17 03:02:13 PM PDT 24
Peak memory 194304 kb
Host smart-0311827d-1fd4-4f64-ac3c-d9f444d85d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695231120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3695231120
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2696610610
Short name T95
Test name
Test status
Simulation time 17473817 ps
CPU time 0.85 seconds
Started Mar 17 03:02:11 PM PDT 24
Finished Mar 17 03:02:12 PM PDT 24
Peak memory 196220 kb
Host smart-72bd8dc0-9126-491b-8559-4ba8fe7e4e29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696610610 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2696610610
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1810702461
Short name T791
Test name
Test status
Simulation time 478626850 ps
CPU time 1.58 seconds
Started Mar 17 03:02:13 PM PDT 24
Finished Mar 17 03:02:15 PM PDT 24
Peak memory 198028 kb
Host smart-eb584f5d-8ab5-4228-9d7a-8941571e96a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810702461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1810702461
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.21577998
Short name T46
Test name
Test status
Simulation time 127369939 ps
CPU time 1.53 seconds
Started Mar 17 03:02:15 PM PDT 24
Finished Mar 17 03:02:16 PM PDT 24
Peak memory 197844 kb
Host smart-667bb0e3-9fcb-4d17-90a0-eeb85b981bcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21577998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.gpio_tl_intg_err.21577998
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2777561526
Short name T755
Test name
Test status
Simulation time 43979469 ps
CPU time 1 seconds
Started Mar 17 03:02:12 PM PDT 24
Finished Mar 17 03:02:13 PM PDT 24
Peak memory 198040 kb
Host smart-eb40de42-f211-469b-a716-1595f6fe084c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777561526 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2777561526
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3673428553
Short name T803
Test name
Test status
Simulation time 179540160 ps
CPU time 0.63 seconds
Started Mar 17 03:02:11 PM PDT 24
Finished Mar 17 03:02:12 PM PDT 24
Peak memory 194736 kb
Host smart-18d519a5-0514-4248-9fb8-74b6b269815d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673428553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3673428553
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1536570496
Short name T840
Test name
Test status
Simulation time 20414682 ps
CPU time 0.61 seconds
Started Mar 17 03:02:13 PM PDT 24
Finished Mar 17 03:02:14 PM PDT 24
Peak memory 194384 kb
Host smart-6158fc69-99bd-4b20-a745-d41861cc80d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536570496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1536570496
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2233370670
Short name T92
Test name
Test status
Simulation time 44561248 ps
CPU time 0.82 seconds
Started Mar 17 03:02:10 PM PDT 24
Finished Mar 17 03:02:11 PM PDT 24
Peak memory 197160 kb
Host smart-299582fd-29f6-4b65-90e7-c966c79cc50a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233370670 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2233370670
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2321453035
Short name T822
Test name
Test status
Simulation time 135693252 ps
CPU time 2.16 seconds
Started Mar 17 03:02:13 PM PDT 24
Finished Mar 17 03:02:15 PM PDT 24
Peak memory 198044 kb
Host smart-6511301f-928d-42f8-a619-716fc43ca3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321453035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2321453035
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.240289709
Short name T39
Test name
Test status
Simulation time 146954443 ps
CPU time 1.12 seconds
Started Mar 17 03:02:16 PM PDT 24
Finished Mar 17 03:02:17 PM PDT 24
Peak memory 198044 kb
Host smart-b0726d22-8327-4973-b8e4-68847312d621
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240289709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.240289709
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3080394885
Short name T743
Test name
Test status
Simulation time 54862332 ps
CPU time 1.5 seconds
Started Mar 17 03:02:16 PM PDT 24
Finished Mar 17 03:02:17 PM PDT 24
Peak memory 198044 kb
Host smart-3d5040e2-e4aa-4cf8-98bf-5c539bc37b04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080394885 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3080394885
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2738894387
Short name T85
Test name
Test status
Simulation time 24712429 ps
CPU time 0.62 seconds
Started Mar 17 03:02:13 PM PDT 24
Finished Mar 17 03:02:14 PM PDT 24
Peak memory 194896 kb
Host smart-0dd0a61a-a8d9-4628-9fec-d2a76fcc0379
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738894387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2738894387
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2950230674
Short name T833
Test name
Test status
Simulation time 31026110 ps
CPU time 0.59 seconds
Started Mar 17 03:02:12 PM PDT 24
Finished Mar 17 03:02:12 PM PDT 24
Peak memory 193632 kb
Host smart-6303ea26-1ff3-4b71-b63e-67e10b3154d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950230674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2950230674
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3687380560
Short name T96
Test name
Test status
Simulation time 13130430 ps
CPU time 0.72 seconds
Started Mar 17 03:02:12 PM PDT 24
Finished Mar 17 03:02:13 PM PDT 24
Peak memory 195768 kb
Host smart-052bea6d-d9e8-4ead-9fb4-c36751d6aeef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687380560 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3687380560
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4011722571
Short name T808
Test name
Test status
Simulation time 820838072 ps
CPU time 2.28 seconds
Started Mar 17 03:02:15 PM PDT 24
Finished Mar 17 03:02:18 PM PDT 24
Peak memory 198008 kb
Host smart-da3be57f-5426-499f-9978-dfeff0439de9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011722571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.4011722571
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3620019171
Short name T817
Test name
Test status
Simulation time 92512219 ps
CPU time 0.89 seconds
Started Mar 17 03:02:13 PM PDT 24
Finished Mar 17 03:02:14 PM PDT 24
Peak memory 197316 kb
Host smart-1517bd49-efe8-433e-b9ee-d87845cd8693
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620019171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3620019171
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2601759690
Short name T738
Test name
Test status
Simulation time 33713756 ps
CPU time 1.56 seconds
Started Mar 17 03:02:21 PM PDT 24
Finished Mar 17 03:02:23 PM PDT 24
Peak memory 198144 kb
Host smart-c077318a-907e-4845-bfcc-ce4025f4e709
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601759690 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2601759690
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3251766076
Short name T834
Test name
Test status
Simulation time 44066725 ps
CPU time 0.62 seconds
Started Mar 17 03:02:15 PM PDT 24
Finished Mar 17 03:02:15 PM PDT 24
Peak memory 194636 kb
Host smart-deef1e7d-d1df-4e42-896a-91094a65f015
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251766076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3251766076
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2604283085
Short name T753
Test name
Test status
Simulation time 32855642 ps
CPU time 0.6 seconds
Started Mar 17 03:02:19 PM PDT 24
Finished Mar 17 03:02:19 PM PDT 24
Peak memory 193840 kb
Host smart-1f79c453-b9de-4349-9c6a-86f929df381d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604283085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2604283085
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2190757364
Short name T816
Test name
Test status
Simulation time 81160252 ps
CPU time 0.7 seconds
Started Mar 17 03:02:19 PM PDT 24
Finished Mar 17 03:02:20 PM PDT 24
Peak memory 194980 kb
Host smart-09b062f6-656c-42a1-9c88-070754a7cb61
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190757364 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2190757364
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1892693192
Short name T737
Test name
Test status
Simulation time 1411141230 ps
CPU time 2.62 seconds
Started Mar 17 03:02:18 PM PDT 24
Finished Mar 17 03:02:20 PM PDT 24
Peak memory 198004 kb
Host smart-414492d2-effa-4a28-b801-5e44bfb55fda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892693192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1892693192
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.892067491
Short name T794
Test name
Test status
Simulation time 55007252 ps
CPU time 1.41 seconds
Started Mar 17 03:02:19 PM PDT 24
Finished Mar 17 03:02:20 PM PDT 24
Peak memory 198024 kb
Host smart-81f7c626-5f77-4c71-88d2-c1d4c4950600
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892067491 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.892067491
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3512422177
Short name T86
Test name
Test status
Simulation time 48615506 ps
CPU time 0.63 seconds
Started Mar 17 03:02:18 PM PDT 24
Finished Mar 17 03:02:19 PM PDT 24
Peak memory 194832 kb
Host smart-62f425c1-d201-4959-8202-81199f7367b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512422177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3512422177
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2255983421
Short name T776
Test name
Test status
Simulation time 12793305 ps
CPU time 0.58 seconds
Started Mar 17 03:02:17 PM PDT 24
Finished Mar 17 03:02:17 PM PDT 24
Peak memory 193656 kb
Host smart-2d21872b-8ff9-4439-9d66-09ad68e4f164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255983421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2255983421
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.541612494
Short name T814
Test name
Test status
Simulation time 34677274 ps
CPU time 0.83 seconds
Started Mar 17 03:02:17 PM PDT 24
Finished Mar 17 03:02:18 PM PDT 24
Peak memory 196288 kb
Host smart-e34a1a45-a1de-4d95-8526-0861b641109a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541612494 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.541612494
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2402092293
Short name T809
Test name
Test status
Simulation time 320906097 ps
CPU time 1.98 seconds
Started Mar 17 03:02:18 PM PDT 24
Finished Mar 17 03:02:20 PM PDT 24
Peak memory 198024 kb
Host smart-a67f7561-6313-44cf-a3c9-3f9ab1776d80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402092293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2402092293
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3067097482
Short name T828
Test name
Test status
Simulation time 127414445 ps
CPU time 1.44 seconds
Started Mar 17 03:02:17 PM PDT 24
Finished Mar 17 03:02:18 PM PDT 24
Peak memory 197996 kb
Host smart-8d01d35d-7ea1-407d-a687-711164a4d9c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067097482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3067097482
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.4110411400
Short name T774
Test name
Test status
Simulation time 30437925 ps
CPU time 1.47 seconds
Started Mar 17 03:02:24 PM PDT 24
Finished Mar 17 03:02:27 PM PDT 24
Peak memory 198100 kb
Host smart-2104d44e-5c76-45b1-9599-05f5fda2728f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110411400 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.4110411400
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2513730261
Short name T102
Test name
Test status
Simulation time 68407115 ps
CPU time 0.63 seconds
Started Mar 17 03:02:22 PM PDT 24
Finished Mar 17 03:02:24 PM PDT 24
Peak memory 195336 kb
Host smart-8c51bccd-eb3d-4755-80ad-7866c5059d37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513730261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2513730261
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1753519394
Short name T733
Test name
Test status
Simulation time 13135847 ps
CPU time 0.61 seconds
Started Mar 17 03:02:26 PM PDT 24
Finished Mar 17 03:02:27 PM PDT 24
Peak memory 193732 kb
Host smart-7f57dff7-054d-4f22-93ae-e40a9693d372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753519394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1753519394
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1201841824
Short name T801
Test name
Test status
Simulation time 88031100 ps
CPU time 0.71 seconds
Started Mar 17 03:02:26 PM PDT 24
Finished Mar 17 03:02:28 PM PDT 24
Peak memory 195684 kb
Host smart-897f442b-355f-4aee-877d-ab099c1727a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201841824 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1201841824
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.735055271
Short name T827
Test name
Test status
Simulation time 76026891 ps
CPU time 1.58 seconds
Started Mar 17 03:02:25 PM PDT 24
Finished Mar 17 03:02:27 PM PDT 24
Peak memory 198020 kb
Host smart-6c29496e-a4cd-458d-90c9-1000270f8a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735055271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.735055271
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2603035400
Short name T103
Test name
Test status
Simulation time 83162350 ps
CPU time 0.91 seconds
Started Mar 17 03:02:29 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 197320 kb
Host smart-3be42312-384c-4545-b575-5b0cd8886d19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603035400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2603035400
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2055987837
Short name T764
Test name
Test status
Simulation time 111814394 ps
CPU time 0.81 seconds
Started Mar 17 03:02:24 PM PDT 24
Finished Mar 17 03:02:26 PM PDT 24
Peak memory 197964 kb
Host smart-3fef6c26-d1bd-49f7-a49d-22f0e0ac6e5c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055987837 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2055987837
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1405082192
Short name T781
Test name
Test status
Simulation time 51372031 ps
CPU time 0.64 seconds
Started Mar 17 03:02:29 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 194720 kb
Host smart-003abf0f-fbc5-4128-92ec-78805ceca074
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405082192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1405082192
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3969087529
Short name T771
Test name
Test status
Simulation time 16454170 ps
CPU time 0.6 seconds
Started Mar 17 03:02:23 PM PDT 24
Finished Mar 17 03:02:24 PM PDT 24
Peak memory 193632 kb
Host smart-a170c5eb-0350-41ac-a257-20c8c50b70fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969087529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3969087529
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3695908577
Short name T94
Test name
Test status
Simulation time 61423449 ps
CPU time 0.84 seconds
Started Mar 17 03:02:26 PM PDT 24
Finished Mar 17 03:02:28 PM PDT 24
Peak memory 196464 kb
Host smart-6e3bfef6-255a-4ada-9d34-d62597c7cbc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695908577 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3695908577
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.56534534
Short name T829
Test name
Test status
Simulation time 502240931 ps
CPU time 1.7 seconds
Started Mar 17 03:02:24 PM PDT 24
Finished Mar 17 03:02:25 PM PDT 24
Peak memory 198068 kb
Host smart-b5448e21-25b1-4d9d-a148-f633adfa8c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56534534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.56534534
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1917835487
Short name T815
Test name
Test status
Simulation time 41560964 ps
CPU time 0.9 seconds
Started Mar 17 03:02:29 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 197180 kb
Host smart-096eb45b-1523-4746-abd5-fb1d9866e90b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917835487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1917835487
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2433000048
Short name T797
Test name
Test status
Simulation time 38573703 ps
CPU time 0.85 seconds
Started Mar 17 03:01:51 PM PDT 24
Finished Mar 17 03:01:53 PM PDT 24
Peak memory 196824 kb
Host smart-df8b961c-780c-438b-857f-cd4e26210011
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433000048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2433000048
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2183121500
Short name T101
Test name
Test status
Simulation time 994357486 ps
CPU time 2.48 seconds
Started Mar 17 03:01:59 PM PDT 24
Finished Mar 17 03:02:02 PM PDT 24
Peak memory 196980 kb
Host smart-6c0835c3-0c6e-40a1-a115-07a64c496543
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183121500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2183121500
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3899302635
Short name T790
Test name
Test status
Simulation time 33469026 ps
CPU time 0.66 seconds
Started Mar 17 03:01:56 PM PDT 24
Finished Mar 17 03:01:57 PM PDT 24
Peak memory 195460 kb
Host smart-16abd94e-2354-4335-9ec7-0a7e72718a4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899302635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3899302635
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.443642488
Short name T722
Test name
Test status
Simulation time 18030073 ps
CPU time 0.67 seconds
Started Mar 17 03:01:53 PM PDT 24
Finished Mar 17 03:01:54 PM PDT 24
Peak memory 196884 kb
Host smart-a0c57bbe-b689-4d70-b1dc-81bae39138f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443642488 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.443642488
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2702328431
Short name T806
Test name
Test status
Simulation time 14750896 ps
CPU time 0.64 seconds
Started Mar 17 03:01:59 PM PDT 24
Finished Mar 17 03:02:01 PM PDT 24
Peak memory 193700 kb
Host smart-745ca729-b133-490a-b00d-8eb6ac91f9c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702328431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2702328431
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2017749820
Short name T835
Test name
Test status
Simulation time 103310058 ps
CPU time 0.85 seconds
Started Mar 17 03:01:52 PM PDT 24
Finished Mar 17 03:01:54 PM PDT 24
Peak memory 197180 kb
Host smart-b5d5d02e-15d2-46c6-91a0-d2a0441771c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017749820 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2017749820
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2779354566
Short name T824
Test name
Test status
Simulation time 108443373 ps
CPU time 1.2 seconds
Started Mar 17 03:01:58 PM PDT 24
Finished Mar 17 03:01:59 PM PDT 24
Peak memory 198032 kb
Host smart-3f435e00-a7a7-4983-a120-dee8b9eea7fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779354566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2779354566
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2770938300
Short name T719
Test name
Test status
Simulation time 16817583 ps
CPU time 0.66 seconds
Started Mar 17 03:02:25 PM PDT 24
Finished Mar 17 03:02:27 PM PDT 24
Peak memory 193828 kb
Host smart-a9dc2ca4-5add-4858-8252-25010223d0ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770938300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2770938300
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2567470362
Short name T760
Test name
Test status
Simulation time 11815518 ps
CPU time 0.62 seconds
Started Mar 17 03:02:23 PM PDT 24
Finished Mar 17 03:02:24 PM PDT 24
Peak memory 193688 kb
Host smart-88c94230-7e5b-4738-88fc-454ac6f594fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567470362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2567470362
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.697674418
Short name T772
Test name
Test status
Simulation time 30588348 ps
CPU time 0.63 seconds
Started Mar 17 03:02:26 PM PDT 24
Finished Mar 17 03:02:28 PM PDT 24
Peak memory 194316 kb
Host smart-4e8752c1-06c8-4387-8a2f-ed3a746f10e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697674418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.697674418
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3560267519
Short name T749
Test name
Test status
Simulation time 51039020 ps
CPU time 0.58 seconds
Started Mar 17 03:02:26 PM PDT 24
Finished Mar 17 03:02:28 PM PDT 24
Peak memory 193684 kb
Host smart-fea5ddb7-dcdf-43fa-992f-f132946258e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560267519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3560267519
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1399630479
Short name T730
Test name
Test status
Simulation time 78934606 ps
CPU time 0.63 seconds
Started Mar 17 03:02:29 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 194392 kb
Host smart-fb7892e2-0c24-42f3-b8db-14e50637ff1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399630479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1399630479
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3567748125
Short name T773
Test name
Test status
Simulation time 13161919 ps
CPU time 0.65 seconds
Started Mar 17 03:02:28 PM PDT 24
Finished Mar 17 03:02:31 PM PDT 24
Peak memory 193728 kb
Host smart-3918119a-eae9-4ead-9a94-a0b28ec7ea86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567748125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3567748125
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.709401988
Short name T783
Test name
Test status
Simulation time 78705730 ps
CPU time 0.61 seconds
Started Mar 17 03:02:24 PM PDT 24
Finished Mar 17 03:02:26 PM PDT 24
Peak memory 193640 kb
Host smart-00f5feaf-f6c8-41a2-a4d2-fa217a50b1ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709401988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.709401988
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2278926287
Short name T820
Test name
Test status
Simulation time 23435090 ps
CPU time 0.61 seconds
Started Mar 17 03:02:29 PM PDT 24
Finished Mar 17 03:02:31 PM PDT 24
Peak memory 193804 kb
Host smart-033c7a96-d7e1-4c51-b5a9-2158fba08a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278926287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2278926287
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4178759458
Short name T839
Test name
Test status
Simulation time 15253460 ps
CPU time 0.59 seconds
Started Mar 17 03:02:31 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193720 kb
Host smart-7a59493b-045d-456f-8617-8fd273e47684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178759458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4178759458
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3467559534
Short name T763
Test name
Test status
Simulation time 170260317 ps
CPU time 0.6 seconds
Started Mar 17 03:02:31 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193640 kb
Host smart-353ed8a2-6b08-4640-828f-3baa8bc9f2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467559534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3467559534
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2947434991
Short name T78
Test name
Test status
Simulation time 19151484 ps
CPU time 0.84 seconds
Started Mar 17 03:01:57 PM PDT 24
Finished Mar 17 03:01:58 PM PDT 24
Peak memory 196704 kb
Host smart-e2646cac-58de-435f-9b48-a4b7b33758c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947434991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2947434991
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1841755590
Short name T795
Test name
Test status
Simulation time 65836637 ps
CPU time 1.44 seconds
Started Mar 17 03:02:02 PM PDT 24
Finished Mar 17 03:02:04 PM PDT 24
Peak memory 197888 kb
Host smart-362b7aed-a1c9-4f15-8ae1-7ee6397fe08a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841755590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1841755590
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.903770394
Short name T800
Test name
Test status
Simulation time 18069696 ps
CPU time 0.67 seconds
Started Mar 17 03:01:57 PM PDT 24
Finished Mar 17 03:01:57 PM PDT 24
Peak memory 194916 kb
Host smart-cfca004b-48be-4e7b-8fdf-b27c7f160488
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903770394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.903770394
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3378375119
Short name T732
Test name
Test status
Simulation time 23959874 ps
CPU time 0.74 seconds
Started Mar 17 03:01:57 PM PDT 24
Finished Mar 17 03:01:58 PM PDT 24
Peak memory 197644 kb
Host smart-09f837ee-fc13-4b1a-8d8d-98a3bee7dcad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378375119 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3378375119
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1281525142
Short name T81
Test name
Test status
Simulation time 40563855 ps
CPU time 0.6 seconds
Started Mar 17 03:02:06 PM PDT 24
Finished Mar 17 03:02:07 PM PDT 24
Peak memory 194588 kb
Host smart-c0712648-2856-44c7-95f9-16ff7607d50f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281525142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1281525142
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3578058286
Short name T741
Test name
Test status
Simulation time 50963624 ps
CPU time 0.61 seconds
Started Mar 17 03:01:58 PM PDT 24
Finished Mar 17 03:01:59 PM PDT 24
Peak memory 193704 kb
Host smart-bb986ef6-150c-4b44-9798-cde4c4492655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578058286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3578058286
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1156467072
Short name T97
Test name
Test status
Simulation time 25852268 ps
CPU time 0.77 seconds
Started Mar 17 03:02:03 PM PDT 24
Finished Mar 17 03:02:04 PM PDT 24
Peak memory 196256 kb
Host smart-c09155bc-b8e5-4a21-8088-a376dc5b1789
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156467072 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1156467072
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.840173847
Short name T780
Test name
Test status
Simulation time 382848695 ps
CPU time 2.08 seconds
Started Mar 17 03:01:57 PM PDT 24
Finished Mar 17 03:01:59 PM PDT 24
Peak memory 198120 kb
Host smart-6afb7094-df4e-4bb2-a361-443725a9d4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840173847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.840173847
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1363824275
Short name T762
Test name
Test status
Simulation time 12988177 ps
CPU time 0.61 seconds
Started Mar 17 03:02:27 PM PDT 24
Finished Mar 17 03:02:30 PM PDT 24
Peak memory 193616 kb
Host smart-5f2205f7-bd66-41b2-af2d-cf0510162042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363824275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1363824275
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3052497728
Short name T759
Test name
Test status
Simulation time 28501574 ps
CPU time 0.55 seconds
Started Mar 17 03:02:28 PM PDT 24
Finished Mar 17 03:02:31 PM PDT 24
Peak memory 193620 kb
Host smart-9d2839b1-02dc-4bb6-9dcf-5a845e05f6ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052497728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3052497728
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2798116912
Short name T825
Test name
Test status
Simulation time 16093581 ps
CPU time 0.58 seconds
Started Mar 17 03:02:30 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193692 kb
Host smart-2991112e-0e93-4f48-8b54-e31083e1658f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798116912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2798116912
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.723402019
Short name T718
Test name
Test status
Simulation time 14080685 ps
CPU time 0.6 seconds
Started Mar 17 03:02:29 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193652 kb
Host smart-f8eb9537-95de-4860-8704-2f2c6808d429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723402019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.723402019
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2293724981
Short name T823
Test name
Test status
Simulation time 15696256 ps
CPU time 0.62 seconds
Started Mar 17 03:02:30 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193752 kb
Host smart-bdb35f91-e11b-4bd2-9b66-1f087b13d798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293724981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2293724981
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2330050329
Short name T805
Test name
Test status
Simulation time 15543001 ps
CPU time 0.59 seconds
Started Mar 17 03:02:30 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 194344 kb
Host smart-9a686e37-ece8-4a2b-bfe0-30f34bdd884a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330050329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2330050329
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2182590822
Short name T775
Test name
Test status
Simulation time 38865236 ps
CPU time 0.58 seconds
Started Mar 17 03:02:27 PM PDT 24
Finished Mar 17 03:02:30 PM PDT 24
Peak memory 193680 kb
Host smart-cbcdcb5f-f50b-445b-8e5e-35fe149cd484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182590822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2182590822
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1662245093
Short name T740
Test name
Test status
Simulation time 33631215 ps
CPU time 0.62 seconds
Started Mar 17 03:02:33 PM PDT 24
Finished Mar 17 03:02:34 PM PDT 24
Peak memory 193788 kb
Host smart-33817cc4-7013-4e35-a60e-e011119d3685
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662245093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1662245093
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2881892379
Short name T728
Test name
Test status
Simulation time 14571668 ps
CPU time 0.59 seconds
Started Mar 17 03:02:29 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193712 kb
Host smart-bf3bfa14-94b0-45fd-a08c-a8b780c3d99a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881892379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2881892379
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.716564325
Short name T837
Test name
Test status
Simulation time 30496801 ps
CPU time 0.61 seconds
Started Mar 17 03:02:33 PM PDT 24
Finished Mar 17 03:02:34 PM PDT 24
Peak memory 193696 kb
Host smart-8f362443-e12b-47a7-9646-803ec970fc97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716564325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.716564325
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1867842507
Short name T76
Test name
Test status
Simulation time 95032265 ps
CPU time 0.74 seconds
Started Mar 17 03:02:03 PM PDT 24
Finished Mar 17 03:02:04 PM PDT 24
Peak memory 196712 kb
Host smart-b4e79108-98e7-4d7b-99f6-06799d0f99ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867842507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1867842507
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1378536705
Short name T721
Test name
Test status
Simulation time 178842357 ps
CPU time 1.49 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:11 PM PDT 24
Peak memory 196212 kb
Host smart-95cc7edc-f550-4d15-b41d-6519a18881c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378536705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1378536705
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2306063879
Short name T88
Test name
Test status
Simulation time 22402939 ps
CPU time 0.7 seconds
Started Mar 17 03:02:04 PM PDT 24
Finished Mar 17 03:02:05 PM PDT 24
Peak memory 195572 kb
Host smart-5965dbdc-dadc-406f-95ac-a4750bb884f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306063879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2306063879
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3080894471
Short name T811
Test name
Test status
Simulation time 33810019 ps
CPU time 0.7 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 197508 kb
Host smart-f75a920a-5ce8-45b0-b3b9-85fc814a9e03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080894471 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3080894471
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2397606723
Short name T819
Test name
Test status
Simulation time 11985347 ps
CPU time 0.56 seconds
Started Mar 17 03:02:03 PM PDT 24
Finished Mar 17 03:02:04 PM PDT 24
Peak memory 193360 kb
Host smart-4421fb26-f987-4012-8b45-992f98f0ae18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397606723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2397606723
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.154394130
Short name T836
Test name
Test status
Simulation time 41202190 ps
CPU time 0.58 seconds
Started Mar 17 03:02:02 PM PDT 24
Finished Mar 17 03:02:03 PM PDT 24
Peak memory 193588 kb
Host smart-e7d0d849-7b52-45ed-854f-e46e37d3a5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154394130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.154394130
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4166497951
Short name T91
Test name
Test status
Simulation time 83815909 ps
CPU time 0.91 seconds
Started Mar 17 03:01:59 PM PDT 24
Finished Mar 17 03:02:00 PM PDT 24
Peak memory 196400 kb
Host smart-787f9441-efa2-4676-99f8-37613971e202
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166497951 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4166497951
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1811626950
Short name T767
Test name
Test status
Simulation time 81932185 ps
CPU time 1.13 seconds
Started Mar 17 03:02:02 PM PDT 24
Finished Mar 17 03:02:04 PM PDT 24
Peak memory 197880 kb
Host smart-7c3614db-e8cb-42a6-acb4-d0c3daade4f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811626950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1811626950
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1373221098
Short name T45
Test name
Test status
Simulation time 81062066 ps
CPU time 1.13 seconds
Started Mar 17 03:01:57 PM PDT 24
Finished Mar 17 03:01:58 PM PDT 24
Peak memory 197988 kb
Host smart-f9f56dfe-7df6-4572-80b9-6f8e6fb6da02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373221098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1373221098
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1182478237
Short name T831
Test name
Test status
Simulation time 34574557 ps
CPU time 0.57 seconds
Started Mar 17 03:02:30 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 194340 kb
Host smart-1eaff89e-59a0-443d-90ea-c27065b60acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182478237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1182478237
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.716862195
Short name T754
Test name
Test status
Simulation time 35536335 ps
CPU time 0.57 seconds
Started Mar 17 03:02:29 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193620 kb
Host smart-ab8196e5-af34-4bf2-a9ca-52151e8ef44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716862195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.716862195
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3382545837
Short name T720
Test name
Test status
Simulation time 20655414 ps
CPU time 0.61 seconds
Started Mar 17 03:02:31 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 194380 kb
Host smart-e0a105d8-713d-49e4-b126-f543f220ded7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382545837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3382545837
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3133128641
Short name T735
Test name
Test status
Simulation time 16369848 ps
CPU time 0.62 seconds
Started Mar 17 03:02:27 PM PDT 24
Finished Mar 17 03:02:29 PM PDT 24
Peak memory 193728 kb
Host smart-03588283-3eb5-45a7-859c-dd47c59bbc74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133128641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3133128641
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1830530143
Short name T734
Test name
Test status
Simulation time 14749996 ps
CPU time 0.56 seconds
Started Mar 17 03:02:32 PM PDT 24
Finished Mar 17 03:02:33 PM PDT 24
Peak memory 193668 kb
Host smart-55d0be4b-d72c-4bf7-b08b-9829c5e9a618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830530143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1830530143
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1673947210
Short name T793
Test name
Test status
Simulation time 47294383 ps
CPU time 0.58 seconds
Started Mar 17 03:02:32 PM PDT 24
Finished Mar 17 03:02:33 PM PDT 24
Peak memory 194368 kb
Host smart-ce8b7ff6-17ee-4015-8956-410b7495ea48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673947210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1673947210
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1977575260
Short name T810
Test name
Test status
Simulation time 19955530 ps
CPU time 0.55 seconds
Started Mar 17 03:02:27 PM PDT 24
Finished Mar 17 03:02:30 PM PDT 24
Peak memory 193652 kb
Host smart-3e6e738e-338e-4916-ab58-787878b233e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977575260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1977575260
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2526909528
Short name T779
Test name
Test status
Simulation time 16682569 ps
CPU time 0.59 seconds
Started Mar 17 03:02:29 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193732 kb
Host smart-1152b9c2-ed0b-48d6-b3e4-ab4582b104e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526909528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2526909528
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.4038892542
Short name T784
Test name
Test status
Simulation time 17224312 ps
CPU time 0.63 seconds
Started Mar 17 03:02:30 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193760 kb
Host smart-b3c9e387-e0cb-4899-bc97-da5608109645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038892542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4038892542
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2294098340
Short name T789
Test name
Test status
Simulation time 21488584 ps
CPU time 0.58 seconds
Started Mar 17 03:02:30 PM PDT 24
Finished Mar 17 03:02:32 PM PDT 24
Peak memory 193668 kb
Host smart-5f653e84-ef6b-4533-b8b5-b04086cc95b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294098340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2294098340
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.956604176
Short name T723
Test name
Test status
Simulation time 57086937 ps
CPU time 0.85 seconds
Started Mar 17 03:02:06 PM PDT 24
Finished Mar 17 03:02:07 PM PDT 24
Peak memory 198060 kb
Host smart-48c31c03-a737-42b7-85e2-b9529a0d1add
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956604176 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.956604176
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1426290008
Short name T787
Test name
Test status
Simulation time 15026699 ps
CPU time 0.59 seconds
Started Mar 17 03:01:57 PM PDT 24
Finished Mar 17 03:01:58 PM PDT 24
Peak memory 193240 kb
Host smart-bf3bac00-41b3-4f6f-8567-b8e34ca45874
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426290008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1426290008
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1311466637
Short name T766
Test name
Test status
Simulation time 15177145 ps
CPU time 0.57 seconds
Started Mar 17 03:01:58 PM PDT 24
Finished Mar 17 03:01:59 PM PDT 24
Peak memory 193672 kb
Host smart-ff284256-baf9-4102-8b4a-4cdfa0ddc259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311466637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1311466637
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.121282638
Short name T93
Test name
Test status
Simulation time 70986473 ps
CPU time 0.87 seconds
Started Mar 17 03:01:57 PM PDT 24
Finished Mar 17 03:01:58 PM PDT 24
Peak memory 196580 kb
Host smart-96be3db5-6187-4b87-ad09-be730bcb9e81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121282638 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.121282638
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2525967039
Short name T742
Test name
Test status
Simulation time 590706488 ps
CPU time 2.96 seconds
Started Mar 17 03:01:58 PM PDT 24
Finished Mar 17 03:02:02 PM PDT 24
Peak memory 197980 kb
Host smart-857d6ab1-5c7d-4739-abf8-5fdefbb15270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525967039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2525967039
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.20806235
Short name T49
Test name
Test status
Simulation time 1664889497 ps
CPU time 1.47 seconds
Started Mar 17 03:02:06 PM PDT 24
Finished Mar 17 03:02:08 PM PDT 24
Peak memory 198116 kb
Host smart-a057aacd-ec80-4dec-b796-fa399d91cd7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20806235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.gpio_tl_intg_err.20806235
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2840821711
Short name T746
Test name
Test status
Simulation time 71667630 ps
CPU time 0.71 seconds
Started Mar 17 03:02:04 PM PDT 24
Finished Mar 17 03:02:05 PM PDT 24
Peak memory 197100 kb
Host smart-fa23e324-ec6f-45d8-81cc-cf9fae9d2c7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840821711 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2840821711
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2596217058
Short name T813
Test name
Test status
Simulation time 14731629 ps
CPU time 0.62 seconds
Started Mar 17 03:02:06 PM PDT 24
Finished Mar 17 03:02:06 PM PDT 24
Peak memory 194428 kb
Host smart-5823b23d-695c-4f62-9887-c5936678b369
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596217058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2596217058
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3559065488
Short name T796
Test name
Test status
Simulation time 39667250 ps
CPU time 0.59 seconds
Started Mar 17 03:02:03 PM PDT 24
Finished Mar 17 03:02:04 PM PDT 24
Peak memory 194328 kb
Host smart-bb03bf11-c995-464d-9897-05c7c9e3f293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559065488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3559065488
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1809669342
Short name T769
Test name
Test status
Simulation time 1019649297 ps
CPU time 3.49 seconds
Started Mar 17 03:02:05 PM PDT 24
Finished Mar 17 03:02:08 PM PDT 24
Peak memory 198040 kb
Host smart-1c5699c3-ac54-482a-ad15-4917bac9b8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809669342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1809669342
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1392530820
Short name T48
Test name
Test status
Simulation time 107061908 ps
CPU time 0.95 seconds
Started Mar 17 03:02:05 PM PDT 24
Finished Mar 17 03:02:06 PM PDT 24
Peak memory 197284 kb
Host smart-5c168e6c-23de-48e5-b65c-b22db91700bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392530820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1392530820
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2693322893
Short name T807
Test name
Test status
Simulation time 30948524 ps
CPU time 1.2 seconds
Started Mar 17 03:02:04 PM PDT 24
Finished Mar 17 03:02:06 PM PDT 24
Peak memory 198100 kb
Host smart-dd3973c3-99ac-464c-a794-fed01d45a6f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693322893 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2693322893
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1917465125
Short name T838
Test name
Test status
Simulation time 26093196 ps
CPU time 0.61 seconds
Started Mar 17 03:02:03 PM PDT 24
Finished Mar 17 03:02:04 PM PDT 24
Peak memory 194844 kb
Host smart-286eda23-89bf-4584-8c1e-ed22e50be8d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917465125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1917465125
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3112899579
Short name T830
Test name
Test status
Simulation time 39617262 ps
CPU time 0.59 seconds
Started Mar 17 03:02:04 PM PDT 24
Finished Mar 17 03:02:05 PM PDT 24
Peak memory 193672 kb
Host smart-5107041f-6d47-42af-957d-f2ae0c2ca26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112899579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3112899579
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2267174521
Short name T785
Test name
Test status
Simulation time 13303438 ps
CPU time 0.61 seconds
Started Mar 17 03:02:05 PM PDT 24
Finished Mar 17 03:02:05 PM PDT 24
Peak memory 195392 kb
Host smart-ece97ee2-cabe-4f07-bfee-8273f3245223
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267174521 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2267174521
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4072542004
Short name T750
Test name
Test status
Simulation time 336444722 ps
CPU time 1.89 seconds
Started Mar 17 03:02:04 PM PDT 24
Finished Mar 17 03:02:06 PM PDT 24
Peak memory 198004 kb
Host smart-8b1dab2b-9a9a-4829-8c70-e58ae3c8aef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072542004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.4072542004
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2922978054
Short name T826
Test name
Test status
Simulation time 88910089 ps
CPU time 1.14 seconds
Started Mar 17 03:02:05 PM PDT 24
Finished Mar 17 03:02:07 PM PDT 24
Peak memory 197700 kb
Host smart-e46aa641-1850-4fdf-b9b2-2cfd9105c3c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922978054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2922978054
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3989293133
Short name T756
Test name
Test status
Simulation time 66750973 ps
CPU time 1.54 seconds
Started Mar 17 03:02:02 PM PDT 24
Finished Mar 17 03:02:04 PM PDT 24
Peak memory 198080 kb
Host smart-1a154e4e-6838-4538-85e1-469fab23b0fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989293133 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3989293133
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2386377389
Short name T761
Test name
Test status
Simulation time 24492629 ps
CPU time 0.62 seconds
Started Mar 17 03:02:04 PM PDT 24
Finished Mar 17 03:02:05 PM PDT 24
Peak memory 194920 kb
Host smart-cc8446e8-6103-47fe-a201-9aaa1ffdf5fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386377389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2386377389
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2281086524
Short name T717
Test name
Test status
Simulation time 48581645 ps
CPU time 0.61 seconds
Started Mar 17 03:02:04 PM PDT 24
Finished Mar 17 03:02:05 PM PDT 24
Peak memory 193636 kb
Host smart-a2ed9ba3-681a-4745-97f6-6eb5483b6413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281086524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2281086524
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.852538473
Short name T799
Test name
Test status
Simulation time 441453652 ps
CPU time 0.83 seconds
Started Mar 17 03:02:04 PM PDT 24
Finished Mar 17 03:02:05 PM PDT 24
Peak memory 197128 kb
Host smart-e9423829-7ccc-4d1d-adbf-142552aef7da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852538473 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.852538473
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1801510651
Short name T729
Test name
Test status
Simulation time 97986946 ps
CPU time 1.48 seconds
Started Mar 17 03:02:04 PM PDT 24
Finished Mar 17 03:02:06 PM PDT 24
Peak memory 197972 kb
Host smart-a1b46f6c-d983-4775-b625-6002fe04dc87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801510651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1801510651
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.542082598
Short name T37
Test name
Test status
Simulation time 175333792 ps
CPU time 0.91 seconds
Started Mar 17 03:02:03 PM PDT 24
Finished Mar 17 03:02:04 PM PDT 24
Peak memory 197052 kb
Host smart-6644f7c7-7045-4d8e-afdf-475b28d51d45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542082598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.542082598
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4116801491
Short name T724
Test name
Test status
Simulation time 30979718 ps
CPU time 0.82 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:11 PM PDT 24
Peak memory 198048 kb
Host smart-06d3d82e-c9fb-45d0-b571-f3fd285d5712
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116801491 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.4116801491
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1902598978
Short name T731
Test name
Test status
Simulation time 15463738 ps
CPU time 0.59 seconds
Started Mar 17 03:02:11 PM PDT 24
Finished Mar 17 03:02:11 PM PDT 24
Peak memory 193356 kb
Host smart-3d268516-d851-46ae-b88f-622759d1914b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902598978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1902598978
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2527830586
Short name T745
Test name
Test status
Simulation time 47292365 ps
CPU time 0.58 seconds
Started Mar 17 03:02:11 PM PDT 24
Finished Mar 17 03:02:12 PM PDT 24
Peak memory 194324 kb
Host smart-9e6467ab-3480-43a1-8d4e-1b54b9d0141e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527830586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2527830586
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1607718378
Short name T98
Test name
Test status
Simulation time 41559793 ps
CPU time 0.65 seconds
Started Mar 17 03:02:09 PM PDT 24
Finished Mar 17 03:02:10 PM PDT 24
Peak memory 195812 kb
Host smart-d56c69ca-0c56-48c4-9cf1-f21cddc470b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607718378 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1607718378
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1937967211
Short name T716
Test name
Test status
Simulation time 107772550 ps
CPU time 1.05 seconds
Started Mar 17 03:02:08 PM PDT 24
Finished Mar 17 03:02:09 PM PDT 24
Peak memory 197932 kb
Host smart-0a0119f9-1605-4734-b319-793cd666f0e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937967211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1937967211
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.475805476
Short name T788
Test name
Test status
Simulation time 124931184 ps
CPU time 1.1 seconds
Started Mar 17 03:02:08 PM PDT 24
Finished Mar 17 03:02:09 PM PDT 24
Peak memory 198072 kb
Host smart-37ab4303-c3d0-4a1f-af5c-a9998821af10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475805476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.475805476
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.877673416
Short name T44
Test name
Test status
Simulation time 61054356 ps
CPU time 0.59 seconds
Started Mar 17 02:51:18 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 194140 kb
Host smart-6e98667b-b50d-4723-a696-6110d9a45a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877673416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.877673416
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.237281101
Short name T500
Test name
Test status
Simulation time 23450657 ps
CPU time 0.67 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:11 PM PDT 24
Peak memory 194128 kb
Host smart-9dc69470-839e-4eca-8e6e-191911161e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237281101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.237281101
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2412742570
Short name T308
Test name
Test status
Simulation time 7829734312 ps
CPU time 25.5 seconds
Started Mar 17 02:51:13 PM PDT 24
Finished Mar 17 02:51:39 PM PDT 24
Peak memory 197060 kb
Host smart-b54288d2-86a6-422e-8fe0-f9854e65c7d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412742570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2412742570
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2663504147
Short name T391
Test name
Test status
Simulation time 151363256 ps
CPU time 0.79 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:12 PM PDT 24
Peak memory 196640 kb
Host smart-1c15c1ac-3432-409e-9764-8e28fc4f42cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663504147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2663504147
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1204402241
Short name T475
Test name
Test status
Simulation time 168493760 ps
CPU time 1.2 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:12 PM PDT 24
Peak memory 196592 kb
Host smart-e8cdf1ae-10eb-4c61-8a4a-a7c3fb8724c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204402241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1204402241
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2466919689
Short name T273
Test name
Test status
Simulation time 163076367 ps
CPU time 3.16 seconds
Started Mar 17 02:51:15 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 198036 kb
Host smart-0a337bd6-b36f-4ce8-8d01-69313a76cac1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466919689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2466919689
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2314951863
Short name T256
Test name
Test status
Simulation time 510687701 ps
CPU time 1.24 seconds
Started Mar 17 02:51:14 PM PDT 24
Finished Mar 17 02:51:15 PM PDT 24
Peak memory 195588 kb
Host smart-c09c39ea-f1da-441e-9754-c29f87c0d624
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314951863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2314951863
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2805876795
Short name T149
Test name
Test status
Simulation time 107644306 ps
CPU time 1.1 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:12 PM PDT 24
Peak memory 195920 kb
Host smart-4c976a7c-8354-488e-b580-72e4e6e9ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805876795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2805876795
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1191729167
Short name T595
Test name
Test status
Simulation time 69095274 ps
CPU time 0.97 seconds
Started Mar 17 02:51:20 PM PDT 24
Finished Mar 17 02:51:21 PM PDT 24
Peak memory 196560 kb
Host smart-268749cc-2ec3-4272-8f0b-f8b3529856a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191729167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1191729167
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_smoke.1835336992
Short name T232
Test name
Test status
Simulation time 117222560 ps
CPU time 0.88 seconds
Started Mar 17 02:51:16 PM PDT 24
Finished Mar 17 02:51:17 PM PDT 24
Peak memory 195448 kb
Host smart-3b9eba3b-832a-4f77-8800-6a7bab319a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835336992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1835336992
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.4155402743
Short name T397
Test name
Test status
Simulation time 208624222 ps
CPU time 1.38 seconds
Started Mar 17 02:51:14 PM PDT 24
Finished Mar 17 02:51:15 PM PDT 24
Peak memory 196720 kb
Host smart-da4839c7-1a81-4870-a034-b3f824ca04a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155402743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.4155402743
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.698766715
Short name T111
Test name
Test status
Simulation time 12407919604 ps
CPU time 18.38 seconds
Started Mar 17 02:51:15 PM PDT 24
Finished Mar 17 02:51:34 PM PDT 24
Peak memory 198176 kb
Host smart-fb5f0ce5-0ae2-4653-a4b9-1d507ed41240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698766715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.698766715
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.600989611
Short name T542
Test name
Test status
Simulation time 89966721 ps
CPU time 0.57 seconds
Started Mar 17 02:51:17 PM PDT 24
Finished Mar 17 02:51:18 PM PDT 24
Peak memory 194624 kb
Host smart-2122ca68-8594-4ded-b099-6d4762064b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600989611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.600989611
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1112899902
Short name T490
Test name
Test status
Simulation time 48021338 ps
CPU time 0.65 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:11 PM PDT 24
Peak memory 193952 kb
Host smart-b57db112-b736-472f-859e-069a3482fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112899902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1112899902
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.692375224
Short name T686
Test name
Test status
Simulation time 4813346533 ps
CPU time 23.34 seconds
Started Mar 17 02:51:20 PM PDT 24
Finished Mar 17 02:51:48 PM PDT 24
Peak memory 196632 kb
Host smart-ff53b328-ff3c-4c46-9561-9607ac2730e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692375224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.692375224
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.611008378
Short name T344
Test name
Test status
Simulation time 159085562 ps
CPU time 0.8 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:22 PM PDT 24
Peak memory 195488 kb
Host smart-64735e20-b7cd-4699-9615-850994e5f74c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611008378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.611008378
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3575014141
Short name T341
Test name
Test status
Simulation time 321203472 ps
CPU time 1.4 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 195800 kb
Host smart-f7670d5c-023b-4cf8-a9b8-590f2ffa511d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575014141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3575014141
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.905814360
Short name T486
Test name
Test status
Simulation time 77408197 ps
CPU time 2.38 seconds
Started Mar 17 02:51:28 PM PDT 24
Finished Mar 17 02:51:31 PM PDT 24
Peak memory 197328 kb
Host smart-3487921d-863e-4c39-a03c-a0fef902670c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905814360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.905814360
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.111689935
Short name T338
Test name
Test status
Simulation time 82769389 ps
CPU time 2.55 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:24 PM PDT 24
Peak memory 197184 kb
Host smart-d1b03f7b-d1f5-4c7f-b7c8-46bca122ff38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111689935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.111689935
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.974203951
Short name T583
Test name
Test status
Simulation time 101715450 ps
CPU time 1.18 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:12 PM PDT 24
Peak memory 196116 kb
Host smart-422528ce-6feb-4620-a98a-96b62a21f434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974203951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.974203951
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.541694428
Short name T357
Test name
Test status
Simulation time 517202398 ps
CPU time 1.17 seconds
Started Mar 17 02:51:13 PM PDT 24
Finished Mar 17 02:51:14 PM PDT 24
Peak memory 196960 kb
Host smart-05beea4b-46eb-4a31-ac07-bcd054a4993a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541694428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.541694428
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3261865690
Short name T12
Test name
Test status
Simulation time 380992523 ps
CPU time 4.65 seconds
Started Mar 17 02:51:14 PM PDT 24
Finished Mar 17 02:51:18 PM PDT 24
Peak memory 197960 kb
Host smart-f9d76482-f52a-4fa1-8056-c177e8b7a6bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261865690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3261865690
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2021821804
Short name T43
Test name
Test status
Simulation time 61062062 ps
CPU time 0.89 seconds
Started Mar 17 02:51:12 PM PDT 24
Finished Mar 17 02:51:13 PM PDT 24
Peak memory 213844 kb
Host smart-5bc2ac42-e9bc-433a-bde5-477447326700
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021821804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2021821804
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3333685187
Short name T454
Test name
Test status
Simulation time 59324657 ps
CPU time 0.98 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:12 PM PDT 24
Peak memory 195800 kb
Host smart-85d3fe79-6f9a-4684-a101-3954171b6a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333685187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3333685187
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.4073587370
Short name T605
Test name
Test status
Simulation time 359592158 ps
CPU time 1.49 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:12 PM PDT 24
Peak memory 197976 kb
Host smart-b657f6af-b52d-495d-be48-dc47ed2ebdf4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073587370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.4073587370
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2351092007
Short name T212
Test name
Test status
Simulation time 11854281062 ps
CPU time 78.41 seconds
Started Mar 17 02:51:14 PM PDT 24
Finished Mar 17 02:52:32 PM PDT 24
Peak memory 198136 kb
Host smart-e0446bd2-d11c-4d8d-81bf-c6c1e99c99f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351092007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2351092007
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.4197170540
Short name T170
Test name
Test status
Simulation time 22982942 ps
CPU time 0.57 seconds
Started Mar 17 02:51:50 PM PDT 24
Finished Mar 17 02:51:51 PM PDT 24
Peak memory 194148 kb
Host smart-a132521b-ca5d-4072-8580-d5f11ecc0ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197170540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.4197170540
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1064092449
Short name T13
Test name
Test status
Simulation time 35628855 ps
CPU time 0.87 seconds
Started Mar 17 02:51:38 PM PDT 24
Finished Mar 17 02:51:38 PM PDT 24
Peak memory 195420 kb
Host smart-7aace395-c8b1-4bbd-976f-2e0baf49ca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064092449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1064092449
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.711578290
Short name T462
Test name
Test status
Simulation time 434581303 ps
CPU time 9.27 seconds
Started Mar 17 02:51:41 PM PDT 24
Finished Mar 17 02:51:50 PM PDT 24
Peak memory 196876 kb
Host smart-e3c437b4-af76-4785-9644-542693ad4e8e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711578290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.711578290
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.240336603
Short name T422
Test name
Test status
Simulation time 561413490 ps
CPU time 0.87 seconds
Started Mar 17 02:51:37 PM PDT 24
Finished Mar 17 02:51:38 PM PDT 24
Peak memory 197180 kb
Host smart-39630957-2831-4ab3-a00d-b214bb2fbb85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240336603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.240336603
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3467650351
Short name T141
Test name
Test status
Simulation time 145691408 ps
CPU time 0.86 seconds
Started Mar 17 02:51:41 PM PDT 24
Finished Mar 17 02:51:42 PM PDT 24
Peak memory 195528 kb
Host smart-c4e79995-34ba-4b63-835b-bbf1639424f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467650351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3467650351
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1920771199
Short name T645
Test name
Test status
Simulation time 463298803 ps
CPU time 2.49 seconds
Started Mar 17 02:51:30 PM PDT 24
Finished Mar 17 02:51:33 PM PDT 24
Peak memory 198008 kb
Host smart-13d0bc07-e9ba-48a7-91b3-1074090e33ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920771199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1920771199
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2032183731
Short name T664
Test name
Test status
Simulation time 448895645 ps
CPU time 3.75 seconds
Started Mar 17 02:51:43 PM PDT 24
Finished Mar 17 02:51:46 PM PDT 24
Peak memory 197192 kb
Host smart-560bcc92-521f-4a2a-b15a-e2074ef36f39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032183731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2032183731
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.61199049
Short name T378
Test name
Test status
Simulation time 38780078 ps
CPU time 0.65 seconds
Started Mar 17 02:51:38 PM PDT 24
Finished Mar 17 02:51:39 PM PDT 24
Peak memory 194264 kb
Host smart-91e78265-cfab-4b73-80e0-eb0ea5cf1e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61199049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.61199049
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1100603807
Short name T18
Test name
Test status
Simulation time 96630555 ps
CPU time 0.75 seconds
Started Mar 17 02:51:35 PM PDT 24
Finished Mar 17 02:51:36 PM PDT 24
Peak memory 196236 kb
Host smart-7f0928eb-9f98-40b2-8a0b-db816e727970
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100603807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1100603807
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.199911095
Short name T9
Test name
Test status
Simulation time 3357469048 ps
CPU time 6.92 seconds
Started Mar 17 02:51:41 PM PDT 24
Finished Mar 17 02:51:48 PM PDT 24
Peak memory 198040 kb
Host smart-1c4da020-c821-4071-bdc0-9abc031d436e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199911095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.199911095
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2610213470
Short name T140
Test name
Test status
Simulation time 93046637 ps
CPU time 1.11 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 195516 kb
Host smart-8c9cc678-450e-48d3-a228-9e5e7c19aa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610213470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2610213470
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3641491958
Short name T69
Test name
Test status
Simulation time 416182490 ps
CPU time 1.26 seconds
Started Mar 17 02:51:37 PM PDT 24
Finished Mar 17 02:51:38 PM PDT 24
Peak memory 195800 kb
Host smart-0c386f84-38f9-443e-aee8-438b0dde5435
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641491958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3641491958
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2911374232
Short name T71
Test name
Test status
Simulation time 11235401904 ps
CPU time 90.52 seconds
Started Mar 17 02:51:41 PM PDT 24
Finished Mar 17 02:53:12 PM PDT 24
Peak memory 198148 kb
Host smart-5b823fcf-8478-4619-9475-9e501d505dd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911374232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2911374232
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1683544367
Short name T393
Test name
Test status
Simulation time 499038934736 ps
CPU time 1376.8 seconds
Started Mar 17 02:51:49 PM PDT 24
Finished Mar 17 03:14:46 PM PDT 24
Peak memory 206444 kb
Host smart-f7a1d7fc-0ba0-4d17-82a2-8a43f5b4ca6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1683544367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1683544367
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1674104637
Short name T616
Test name
Test status
Simulation time 60135668 ps
CPU time 0.64 seconds
Started Mar 17 02:51:42 PM PDT 24
Finished Mar 17 02:51:43 PM PDT 24
Peak memory 194104 kb
Host smart-704820da-a13e-4c4d-9d5e-dd3abeb6bbee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674104637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1674104637
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1071888217
Short name T303
Test name
Test status
Simulation time 137265791 ps
CPU time 0.84 seconds
Started Mar 17 02:51:42 PM PDT 24
Finished Mar 17 02:51:43 PM PDT 24
Peak memory 195968 kb
Host smart-a6ee876f-2f87-4b95-b300-9ce9219387d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071888217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1071888217
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2957849002
Short name T195
Test name
Test status
Simulation time 940099275 ps
CPU time 6.9 seconds
Started Mar 17 02:51:50 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 196764 kb
Host smart-de006185-65b3-449d-9efe-f0c7dd762567
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957849002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2957849002
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2309205500
Short name T404
Test name
Test status
Simulation time 60963737 ps
CPU time 0.91 seconds
Started Mar 17 02:51:56 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 196120 kb
Host smart-c07fa8d2-feeb-48d6-8963-d3d18c313ec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309205500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2309205500
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.4132368363
Short name T447
Test name
Test status
Simulation time 232760172 ps
CPU time 1.23 seconds
Started Mar 17 02:51:42 PM PDT 24
Finished Mar 17 02:51:43 PM PDT 24
Peak memory 195960 kb
Host smart-ee3a8acb-b736-4dbd-a7ec-f706952da892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132368363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.4132368363
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4230471443
Short name T219
Test name
Test status
Simulation time 181131803 ps
CPU time 1.24 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 196820 kb
Host smart-a196c63c-e5cf-4a69-b3d6-cecac6bc74ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230471443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4230471443
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.238437110
Short name T115
Test name
Test status
Simulation time 513135433 ps
CPU time 1.81 seconds
Started Mar 17 02:51:41 PM PDT 24
Finished Mar 17 02:51:43 PM PDT 24
Peak memory 195900 kb
Host smart-b4150d38-e606-473b-81f7-29c23bf3383f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238437110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
238437110
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2121084414
Short name T247
Test name
Test status
Simulation time 224935489 ps
CPU time 1.3 seconds
Started Mar 17 02:51:55 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 196976 kb
Host smart-b51dafd2-938f-4c73-af31-e81eae94370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121084414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2121084414
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1344900888
Short name T21
Test name
Test status
Simulation time 58743823 ps
CPU time 1.35 seconds
Started Mar 17 02:51:56 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 196972 kb
Host smart-69364f36-bb72-43dc-aeb2-d46f8a483a74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344900888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1344900888
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1669107315
Short name T380
Test name
Test status
Simulation time 140475712 ps
CPU time 2.23 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 198004 kb
Host smart-94266489-25e8-4803-b8db-fd9638624e9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669107315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1669107315
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1607314780
Short name T290
Test name
Test status
Simulation time 50865743 ps
CPU time 1.04 seconds
Started Mar 17 02:51:42 PM PDT 24
Finished Mar 17 02:51:43 PM PDT 24
Peak memory 196320 kb
Host smart-29792d7c-3c72-4768-9261-a61a8d3a49d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607314780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1607314780
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3264854605
Short name T17
Test name
Test status
Simulation time 199961710 ps
CPU time 1 seconds
Started Mar 17 02:51:42 PM PDT 24
Finished Mar 17 02:51:43 PM PDT 24
Peak memory 195556 kb
Host smart-b13a34bb-efb6-42fe-9a26-c6583ec10b37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264854605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3264854605
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3667647285
Short name T138
Test name
Test status
Simulation time 50348838171 ps
CPU time 182.78 seconds
Started Mar 17 02:51:49 PM PDT 24
Finished Mar 17 02:54:52 PM PDT 24
Peak memory 198168 kb
Host smart-95174ac8-cfe4-4ada-8eeb-ed6532b3e330
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667647285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3667647285
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.290265615
Short name T484
Test name
Test status
Simulation time 561251419627 ps
CPU time 679.07 seconds
Started Mar 17 02:51:51 PM PDT 24
Finished Mar 17 03:03:11 PM PDT 24
Peak memory 198272 kb
Host smart-c36bfcfd-c9cb-4472-9740-aa3a9e5e434e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=290265615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.290265615
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2847096473
Short name T560
Test name
Test status
Simulation time 10762427 ps
CPU time 0.56 seconds
Started Mar 17 02:51:55 PM PDT 24
Finished Mar 17 02:51:56 PM PDT 24
Peak memory 193924 kb
Host smart-334f31b5-212a-4665-bd6e-43aaa5c75348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847096473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2847096473
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.4111261356
Short name T684
Test name
Test status
Simulation time 31422945 ps
CPU time 0.68 seconds
Started Mar 17 02:51:38 PM PDT 24
Finished Mar 17 02:51:39 PM PDT 24
Peak memory 194076 kb
Host smart-70b7190c-079a-47ea-8126-28cd8e0376bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111261356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.4111261356
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1568780386
Short name T299
Test name
Test status
Simulation time 1055813417 ps
CPU time 11.56 seconds
Started Mar 17 02:51:44 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 195548 kb
Host smart-2a118f6d-5ebb-4ac2-a7bb-eb77f7cd200d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568780386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1568780386
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.956432414
Short name T563
Test name
Test status
Simulation time 114771739 ps
CPU time 0.77 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 194736 kb
Host smart-e421b2e1-1eb4-4552-87f9-ff3e8d6a27c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956432414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.956432414
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3312785256
Short name T289
Test name
Test status
Simulation time 36136510 ps
CPU time 0.81 seconds
Started Mar 17 02:51:50 PM PDT 24
Finished Mar 17 02:51:52 PM PDT 24
Peak memory 195436 kb
Host smart-a89a3459-e20d-4742-8b7f-894eb84e64b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312785256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3312785256
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3410498862
Short name T311
Test name
Test status
Simulation time 313490062 ps
CPU time 3.23 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 198048 kb
Host smart-2e3defcc-502a-4576-885a-8e335865ee20
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410498862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3410498862
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1740532310
Short name T210
Test name
Test status
Simulation time 72586505 ps
CPU time 2.42 seconds
Started Mar 17 02:51:42 PM PDT 24
Finished Mar 17 02:51:44 PM PDT 24
Peak memory 196948 kb
Host smart-747ca673-4fce-4ac9-9d2d-6afb1ac7af1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740532310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1740532310
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1189075118
Short name T277
Test name
Test status
Simulation time 37708910 ps
CPU time 0.78 seconds
Started Mar 17 02:51:49 PM PDT 24
Finished Mar 17 02:51:50 PM PDT 24
Peak memory 196500 kb
Host smart-6611e8f0-6106-4e49-ac75-7d9850d49cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189075118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1189075118
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3557296495
Short name T401
Test name
Test status
Simulation time 270381555 ps
CPU time 1.29 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:56 PM PDT 24
Peak memory 196964 kb
Host smart-03d5e496-fd20-420d-a9eb-04026bdc9755
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557296495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3557296495
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2995675669
Short name T189
Test name
Test status
Simulation time 320881361 ps
CPU time 4.35 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 197932 kb
Host smart-0bf6ef26-a6da-4171-a5ec-8ef9d07f48a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995675669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2995675669
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1883764323
Short name T695
Test name
Test status
Simulation time 69201398 ps
CPU time 1.22 seconds
Started Mar 17 02:51:39 PM PDT 24
Finished Mar 17 02:51:41 PM PDT 24
Peak memory 195756 kb
Host smart-ee793b60-951d-4c80-b7f1-de219efb1113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883764323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1883764323
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.4292141442
Short name T440
Test name
Test status
Simulation time 173837833 ps
CPU time 1.36 seconds
Started Mar 17 02:51:39 PM PDT 24
Finished Mar 17 02:51:40 PM PDT 24
Peak memory 196660 kb
Host smart-8b47b589-3528-46ee-be26-1be17a72de08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292141442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.4292141442
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4259094821
Short name T412
Test name
Test status
Simulation time 7480051011 ps
CPU time 87.02 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:53:15 PM PDT 24
Peak memory 198176 kb
Host smart-5cc23ba6-0d3b-4856-b187-9db000b79b40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259094821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4259094821
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2978888783
Short name T588
Test name
Test status
Simulation time 38411840 ps
CPU time 0.57 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:51:54 PM PDT 24
Peak memory 193936 kb
Host smart-717188d2-a77e-4a4e-b336-16d34e546c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978888783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2978888783
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3804073723
Short name T342
Test name
Test status
Simulation time 20566109 ps
CPU time 0.68 seconds
Started Mar 17 02:51:41 PM PDT 24
Finished Mar 17 02:51:42 PM PDT 24
Peak memory 194156 kb
Host smart-6eaff6a5-5255-465a-97c3-16f2f929b616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804073723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3804073723
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2276857228
Short name T525
Test name
Test status
Simulation time 589421539 ps
CPU time 25.63 seconds
Started Mar 17 02:51:41 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 196900 kb
Host smart-12772b56-acd0-4508-9654-61d21f5e4872
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276857228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2276857228
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1586826175
Short name T610
Test name
Test status
Simulation time 101775624 ps
CPU time 0.82 seconds
Started Mar 17 02:51:43 PM PDT 24
Finished Mar 17 02:51:44 PM PDT 24
Peak memory 196640 kb
Host smart-79d3e705-3d45-4865-a954-2763f4703ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586826175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1586826175
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3512572975
Short name T271
Test name
Test status
Simulation time 342651553 ps
CPU time 1.6 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:51:49 PM PDT 24
Peak memory 198068 kb
Host smart-9c17b519-413b-4309-a998-a9c1fe9a0948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512572975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3512572975
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.4137662149
Short name T531
Test name
Test status
Simulation time 51905208 ps
CPU time 1.66 seconds
Started Mar 17 02:51:44 PM PDT 24
Finished Mar 17 02:51:46 PM PDT 24
Peak memory 195760 kb
Host smart-877c81bd-21e5-4aaf-b449-9696c42051c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137662149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.4137662149
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3808942290
Short name T703
Test name
Test status
Simulation time 31633511 ps
CPU time 0.84 seconds
Started Mar 17 02:51:43 PM PDT 24
Finished Mar 17 02:51:44 PM PDT 24
Peak memory 197188 kb
Host smart-306cb0b6-9786-403b-9718-2efe1a37b9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808942290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3808942290
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2818486609
Short name T355
Test name
Test status
Simulation time 69442230 ps
CPU time 0.78 seconds
Started Mar 17 02:51:44 PM PDT 24
Finished Mar 17 02:51:44 PM PDT 24
Peak memory 195456 kb
Host smart-b9121ea1-e751-4fcd-b086-5042569fbcb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818486609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2818486609
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4178214837
Short name T698
Test name
Test status
Simulation time 376823277 ps
CPU time 6.39 seconds
Started Mar 17 02:51:42 PM PDT 24
Finished Mar 17 02:51:49 PM PDT 24
Peak memory 198028 kb
Host smart-28f442b9-b410-47a5-849d-34d7176bab8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178214837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4178214837
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3610991828
Short name T688
Test name
Test status
Simulation time 72031891 ps
CPU time 0.76 seconds
Started Mar 17 02:51:43 PM PDT 24
Finished Mar 17 02:51:44 PM PDT 24
Peak memory 195980 kb
Host smart-e3819a45-4faa-4b73-81ea-a4787328c061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610991828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3610991828
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.752907761
Short name T415
Test name
Test status
Simulation time 35387986 ps
CPU time 0.94 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:56 PM PDT 24
Peak memory 196276 kb
Host smart-5a4fc937-b59a-4be4-8522-410b4a2a61f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752907761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.752907761
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1513867694
Short name T463
Test name
Test status
Simulation time 28430260684 ps
CPU time 90.69 seconds
Started Mar 17 02:51:49 PM PDT 24
Finished Mar 17 02:53:20 PM PDT 24
Peak memory 198184 kb
Host smart-4bad2c0b-4182-48f8-8d06-49796048f278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513867694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1513867694
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2348821922
Short name T283
Test name
Test status
Simulation time 12513105 ps
CPU time 0.6 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 194636 kb
Host smart-e699d099-8ba3-4534-9770-95d17ed509cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348821922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2348821922
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2002330495
Short name T627
Test name
Test status
Simulation time 276744890 ps
CPU time 0.95 seconds
Started Mar 17 02:51:55 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 196584 kb
Host smart-4172b2df-2d2f-4417-9794-899721ce3362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002330495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2002330495
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1686805302
Short name T73
Test name
Test status
Simulation time 207628363 ps
CPU time 7.14 seconds
Started Mar 17 02:51:43 PM PDT 24
Finished Mar 17 02:51:51 PM PDT 24
Peak memory 196884 kb
Host smart-793f5869-4844-44dd-8d00-66fcf375d8ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686805302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1686805302
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.272915207
Short name T679
Test name
Test status
Simulation time 139081651 ps
CPU time 0.96 seconds
Started Mar 17 02:51:49 PM PDT 24
Finished Mar 17 02:51:50 PM PDT 24
Peak memory 197168 kb
Host smart-1a91c6f3-b859-410c-8aa7-9c59412831bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272915207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.272915207
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4013941993
Short name T609
Test name
Test status
Simulation time 80673545 ps
CPU time 0.73 seconds
Started Mar 17 02:51:48 PM PDT 24
Finished Mar 17 02:51:49 PM PDT 24
Peak memory 194352 kb
Host smart-ed8e278c-cfe0-4423-8d6a-c774b2092cc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013941993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4013941993
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3758241993
Short name T620
Test name
Test status
Simulation time 349217226 ps
CPU time 3.45 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:59 PM PDT 24
Peak memory 198052 kb
Host smart-b24bcb58-9348-470d-883c-ae74d61b8da1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758241993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3758241993
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.72370857
Short name T279
Test name
Test status
Simulation time 560885048 ps
CPU time 3.96 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:51:52 PM PDT 24
Peak memory 195828 kb
Host smart-d94303b6-f98f-4c67-9e60-de4282202418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72370857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.72370857
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2066677227
Short name T581
Test name
Test status
Simulation time 24202344 ps
CPU time 0.98 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:51:48 PM PDT 24
Peak memory 195976 kb
Host smart-d970b32a-e4b7-4db3-9a1e-ae410b854b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066677227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2066677227
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3496912390
Short name T691
Test name
Test status
Simulation time 89830910 ps
CPU time 0.84 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:51:48 PM PDT 24
Peak memory 195444 kb
Host smart-185f8c38-c1f7-4066-9c6c-8991c802fda2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496912390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3496912390
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2324233014
Short name T387
Test name
Test status
Simulation time 1049214763 ps
CPU time 3.84 seconds
Started Mar 17 02:51:48 PM PDT 24
Finished Mar 17 02:51:52 PM PDT 24
Peak memory 197940 kb
Host smart-a282d72f-2154-4674-9eaa-00832866d002
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324233014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2324233014
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.876420275
Short name T665
Test name
Test status
Simulation time 26877550 ps
CPU time 0.79 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 196164 kb
Host smart-bb4431ce-0074-4e7b-8482-9b1423d958f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876420275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.876420275
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3383685085
Short name T75
Test name
Test status
Simulation time 51887209 ps
CPU time 1.04 seconds
Started Mar 17 02:51:50 PM PDT 24
Finished Mar 17 02:51:52 PM PDT 24
Peak memory 196464 kb
Host smart-809ca888-4885-42c2-bf3e-b13ae894230b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383685085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3383685085
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2087583434
Short name T494
Test name
Test status
Simulation time 49339578254 ps
CPU time 103.72 seconds
Started Mar 17 02:51:46 PM PDT 24
Finished Mar 17 02:53:30 PM PDT 24
Peak memory 198196 kb
Host smart-ddb4dfcc-4b49-41db-b4f4-253a52b40d00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087583434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2087583434
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1852472541
Short name T638
Test name
Test status
Simulation time 50678334 ps
CPU time 0.59 seconds
Started Mar 17 02:51:51 PM PDT 24
Finished Mar 17 02:51:53 PM PDT 24
Peak memory 194092 kb
Host smart-f209781b-1d31-430d-950c-6189acfc090f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852472541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1852472541
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2344353287
Short name T379
Test name
Test status
Simulation time 83758835 ps
CPU time 0.62 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 193924 kb
Host smart-152f2ca8-faae-4340-bbf5-636a36d807f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344353287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2344353287
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1218848139
Short name T469
Test name
Test status
Simulation time 236816292 ps
CPU time 11.69 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 195488 kb
Host smart-0c6b29f9-6abe-40ac-b3e7-fde073019ca7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218848139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1218848139
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2890110040
Short name T216
Test name
Test status
Simulation time 292002542 ps
CPU time 1.09 seconds
Started Mar 17 02:51:51 PM PDT 24
Finished Mar 17 02:51:54 PM PDT 24
Peak memory 196844 kb
Host smart-2f899096-c8bf-4556-8c0e-41ea3daf5d6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890110040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2890110040
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.444047109
Short name T392
Test name
Test status
Simulation time 44649378 ps
CPU time 1.16 seconds
Started Mar 17 02:51:59 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 196168 kb
Host smart-d4ebec8a-41d1-4d69-bd4b-da8de4e43cb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444047109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.444047109
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2203936165
Short name T369
Test name
Test status
Simulation time 387830206 ps
CPU time 1.59 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:56 PM PDT 24
Peak memory 198072 kb
Host smart-dcffc7e9-7c83-4023-8f73-1d57d36634ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203936165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2203936165
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1295888550
Short name T194
Test name
Test status
Simulation time 163469088 ps
CPU time 3.04 seconds
Started Mar 17 02:51:48 PM PDT 24
Finished Mar 17 02:51:51 PM PDT 24
Peak memory 197208 kb
Host smart-6bd023d5-f8c6-4681-8965-4ebacec90b3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295888550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1295888550
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3614690216
Short name T390
Test name
Test status
Simulation time 96592355 ps
CPU time 1.17 seconds
Started Mar 17 02:51:57 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 196784 kb
Host smart-f61546bb-d01a-40b2-a301-7975b35e7a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614690216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3614690216
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2608918063
Short name T294
Test name
Test status
Simulation time 16623696 ps
CPU time 0.71 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 195360 kb
Host smart-c0ae7086-3a76-47d6-aec0-81584abed85f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608918063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2608918063
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2272810791
Short name T524
Test name
Test status
Simulation time 109842688 ps
CPU time 2.9 seconds
Started Mar 17 02:51:50 PM PDT 24
Finished Mar 17 02:51:53 PM PDT 24
Peak memory 197988 kb
Host smart-68a0e328-48ed-4aa7-88b9-95b21cf30ee5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272810791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2272810791
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2572341411
Short name T472
Test name
Test status
Simulation time 30906705 ps
CPU time 0.96 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:51:48 PM PDT 24
Peak memory 195508 kb
Host smart-71d7d910-d7c6-4450-9c27-2c45850a23c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572341411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2572341411
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1537433840
Short name T644
Test name
Test status
Simulation time 165505525 ps
CPU time 1.16 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:51:49 PM PDT 24
Peak memory 195540 kb
Host smart-5e21966f-bf7f-40d0-b4ba-397a99955a8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537433840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1537433840
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.4266623407
Short name T188
Test name
Test status
Simulation time 750314190 ps
CPU time 19.17 seconds
Started Mar 17 02:52:05 PM PDT 24
Finished Mar 17 02:52:25 PM PDT 24
Peak memory 198116 kb
Host smart-452ad730-11e9-4c4a-b482-a88300f15943
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266623407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4266623407
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2507569906
Short name T467
Test name
Test status
Simulation time 12086151 ps
CPU time 0.6 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:51:48 PM PDT 24
Peak memory 193952 kb
Host smart-597a77f1-c623-473f-a7c4-612d25e60f7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507569906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2507569906
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2766332552
Short name T585
Test name
Test status
Simulation time 454550433 ps
CPU time 0.97 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:51:54 PM PDT 24
Peak memory 196564 kb
Host smart-95964633-7ceb-4155-a402-3154e9c1f173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766332552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2766332552
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3180439356
Short name T618
Test name
Test status
Simulation time 722026086 ps
CPU time 23.87 seconds
Started Mar 17 02:51:50 PM PDT 24
Finished Mar 17 02:52:15 PM PDT 24
Peak memory 195680 kb
Host smart-35a8311e-d12f-48ec-817a-451332883012
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180439356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3180439356
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2438192980
Short name T631
Test name
Test status
Simulation time 97435647 ps
CPU time 1.1 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 196628 kb
Host smart-2fbb75c8-e409-4705-924b-4412bfab7d6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438192980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2438192980
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1551082970
Short name T26
Test name
Test status
Simulation time 147281188 ps
CPU time 1.19 seconds
Started Mar 17 02:51:51 PM PDT 24
Finished Mar 17 02:51:53 PM PDT 24
Peak memory 196524 kb
Host smart-47c32489-9f1c-42fb-ba5f-a62a88deb30a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551082970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1551082970
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2803787442
Short name T205
Test name
Test status
Simulation time 706465020 ps
CPU time 1.96 seconds
Started Mar 17 02:52:05 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 198052 kb
Host smart-cf7c4abd-d822-4635-91c4-4d9baf09530c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803787442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2803787442
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2688778530
Short name T110
Test name
Test status
Simulation time 168213799 ps
CPU time 3.38 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:08 PM PDT 24
Peak memory 197152 kb
Host smart-57eb5e7f-4723-4996-b12e-04daace45352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688778530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2688778530
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.4228833802
Short name T117
Test name
Test status
Simulation time 444450632 ps
CPU time 1.26 seconds
Started Mar 17 02:51:56 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 197032 kb
Host smart-aa1daa13-bcf1-427d-bc95-c0ae5dd96f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228833802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.4228833802
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3139611943
Short name T452
Test name
Test status
Simulation time 147588645 ps
CPU time 1.01 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:51:59 PM PDT 24
Peak memory 196788 kb
Host smart-177b5536-f5c8-4c2e-adfc-d0e9030a14e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139611943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3139611943
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2444702008
Short name T14
Test name
Test status
Simulation time 64210732 ps
CPU time 1.58 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 197968 kb
Host smart-908a52ed-bd42-43a3-a352-4922c0d82a7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444702008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2444702008
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2298662056
Short name T597
Test name
Test status
Simulation time 66136064 ps
CPU time 1.38 seconds
Started Mar 17 02:51:56 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 197972 kb
Host smart-c66ad18a-58a7-4dac-ab3e-68a3510b1ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298662056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2298662056
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1608420227
Short name T389
Test name
Test status
Simulation time 190395766 ps
CPU time 1.07 seconds
Started Mar 17 02:51:57 PM PDT 24
Finished Mar 17 02:51:59 PM PDT 24
Peak memory 196544 kb
Host smart-5dcb1af9-47d8-4d0a-8560-29d003bb5a6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608420227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1608420227
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.777373905
Short name T276
Test name
Test status
Simulation time 1292478628 ps
CPU time 34.68 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:52:27 PM PDT 24
Peak memory 198084 kb
Host smart-d8837bd1-8ac9-4ab5-b74d-4659de817276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777373905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.777373905
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2877673699
Short name T100
Test name
Test status
Simulation time 47287147918 ps
CPU time 1411.99 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 03:15:27 PM PDT 24
Peak memory 198204 kb
Host smart-12cee0a9-9ca6-4672-ac83-97e042b6dcc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2877673699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2877673699
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.261351374
Short name T151
Test name
Test status
Simulation time 75024741 ps
CPU time 0.63 seconds
Started Mar 17 02:51:55 PM PDT 24
Finished Mar 17 02:51:56 PM PDT 24
Peak memory 194856 kb
Host smart-eb8e1031-8fa5-4ad5-b082-bc2d125f4f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261351374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.261351374
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1312698564
Short name T236
Test name
Test status
Simulation time 49067740 ps
CPU time 0.73 seconds
Started Mar 17 02:51:48 PM PDT 24
Finished Mar 17 02:51:49 PM PDT 24
Peak memory 194212 kb
Host smart-f40383e3-4991-4312-aed2-e6b6718e2dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312698564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1312698564
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2384465678
Short name T144
Test name
Test status
Simulation time 1550291835 ps
CPU time 20.36 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:52:08 PM PDT 24
Peak memory 196844 kb
Host smart-54b49915-5c13-483f-9b7a-2a25d00b9f25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384465678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2384465678
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1424702612
Short name T322
Test name
Test status
Simulation time 35512795 ps
CPU time 0.73 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 194672 kb
Host smart-8407e859-d389-4e18-a663-250d36104d1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424702612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1424702612
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1206600992
Short name T533
Test name
Test status
Simulation time 89010571 ps
CPU time 1.3 seconds
Started Mar 17 02:51:56 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 196072 kb
Host smart-a4392ced-bf95-4ba9-92cf-789176dbfbfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206600992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1206600992
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.751225277
Short name T446
Test name
Test status
Simulation time 245410016 ps
CPU time 2.63 seconds
Started Mar 17 02:51:48 PM PDT 24
Finished Mar 17 02:51:50 PM PDT 24
Peak memory 198144 kb
Host smart-bac9f71d-7c0f-4890-b701-8f832b94cf24
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751225277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.751225277
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.59517003
Short name T32
Test name
Test status
Simulation time 60978207 ps
CPU time 1.86 seconds
Started Mar 17 02:51:50 PM PDT 24
Finished Mar 17 02:51:52 PM PDT 24
Peak memory 196048 kb
Host smart-b0e378cb-5cba-452e-a865-25ee63166e59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59517003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.59517003
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3014796034
Short name T120
Test name
Test status
Simulation time 59997518 ps
CPU time 0.79 seconds
Started Mar 17 02:51:48 PM PDT 24
Finished Mar 17 02:51:49 PM PDT 24
Peak memory 196216 kb
Host smart-77a0a2ea-f748-442e-9af4-7ca6a9537b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014796034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3014796034
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1553719360
Short name T444
Test name
Test status
Simulation time 77608566 ps
CPU time 1.09 seconds
Started Mar 17 02:51:48 PM PDT 24
Finished Mar 17 02:51:50 PM PDT 24
Peak memory 195804 kb
Host smart-91135020-2a8c-4b5d-a4ba-6f862ecdde10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553719360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1553719360
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.628094932
Short name T116
Test name
Test status
Simulation time 335369549 ps
CPU time 5.56 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:08 PM PDT 24
Peak memory 197984 kb
Host smart-9f58585a-28eb-4d34-b08c-313301c68055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628094932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.628094932
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2963403820
Short name T432
Test name
Test status
Simulation time 496348134 ps
CPU time 1.21 seconds
Started Mar 17 02:51:49 PM PDT 24
Finished Mar 17 02:51:50 PM PDT 24
Peak memory 196324 kb
Host smart-15c3b334-9cf5-4f20-9fc3-fa4b7604629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963403820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2963403820
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1086666518
Short name T282
Test name
Test status
Simulation time 439772633 ps
CPU time 1.18 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:51:54 PM PDT 24
Peak memory 195864 kb
Host smart-81a0d9bf-8bba-4878-9bd6-53e0de82443f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086666518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1086666518
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2329648277
Short name T198
Test name
Test status
Simulation time 29838114671 ps
CPU time 211.86 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:55:27 PM PDT 24
Peak memory 198204 kb
Host smart-f4f2e3ac-67e9-4f66-9bf9-97e5283f65b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329648277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2329648277
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.953088012
Short name T230
Test name
Test status
Simulation time 13522353 ps
CPU time 0.58 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 194596 kb
Host smart-24b0a638-1944-4fec-9f49-6f736dd79d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953088012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.953088012
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.301053446
Short name T268
Test name
Test status
Simulation time 163567275 ps
CPU time 0.77 seconds
Started Mar 17 02:51:50 PM PDT 24
Finished Mar 17 02:51:50 PM PDT 24
Peak memory 195316 kb
Host smart-875f3524-38d0-4899-ba18-53d8ba7eb880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301053446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.301053446
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1268527907
Short name T701
Test name
Test status
Simulation time 1682091251 ps
CPU time 9.53 seconds
Started Mar 17 02:51:56 PM PDT 24
Finished Mar 17 02:52:06 PM PDT 24
Peak memory 196772 kb
Host smart-8b0a4688-5e2b-461b-87ed-da83dc5c8e36
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268527907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1268527907
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.4055283996
Short name T497
Test name
Test status
Simulation time 27850579 ps
CPU time 0.63 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:51:54 PM PDT 24
Peak memory 194316 kb
Host smart-dc54b3af-5c0e-4107-bcde-10dd6ae42a5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055283996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.4055283996
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1088551096
Short name T345
Test name
Test status
Simulation time 1035567919 ps
CPU time 1.33 seconds
Started Mar 17 02:51:48 PM PDT 24
Finished Mar 17 02:51:50 PM PDT 24
Peak memory 197044 kb
Host smart-c88b4854-9d0d-44e2-a79c-80e614cf1b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088551096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1088551096
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3247967654
Short name T540
Test name
Test status
Simulation time 123577755 ps
CPU time 3.44 seconds
Started Mar 17 02:51:59 PM PDT 24
Finished Mar 17 02:52:03 PM PDT 24
Peak memory 198060 kb
Host smart-e5c64e55-b6f6-415d-ac3d-4a9849640daa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247967654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3247967654
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1660795908
Short name T569
Test name
Test status
Simulation time 177289273 ps
CPU time 1.47 seconds
Started Mar 17 02:51:46 PM PDT 24
Finished Mar 17 02:51:48 PM PDT 24
Peak memory 195768 kb
Host smart-01849c03-c0a8-4d8b-8c77-957bddf9cd21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660795908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1660795908
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2809982671
Short name T520
Test name
Test status
Simulation time 132736076 ps
CPU time 0.92 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:56 PM PDT 24
Peak memory 196520 kb
Host smart-1cc768e5-4cd4-43e0-b75f-6ebdb4b04c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809982671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2809982671
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.759483582
Short name T647
Test name
Test status
Simulation time 30954051 ps
CPU time 1.1 seconds
Started Mar 17 02:51:49 PM PDT 24
Finished Mar 17 02:51:50 PM PDT 24
Peak memory 196764 kb
Host smart-0b855c28-bf35-4851-99ec-510c101fe5aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759483582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.759483582
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1217866239
Short name T409
Test name
Test status
Simulation time 165759509 ps
CPU time 2.34 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 197936 kb
Host smart-4d60586b-2198-456d-9a3c-e80624e84480
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217866239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1217866239
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1653715445
Short name T178
Test name
Test status
Simulation time 658414692 ps
CPU time 1.5 seconds
Started Mar 17 02:51:47 PM PDT 24
Finished Mar 17 02:51:49 PM PDT 24
Peak memory 195536 kb
Host smart-328905d3-964f-445d-9c58-6f13e35f6d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653715445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1653715445
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2009155178
Short name T310
Test name
Test status
Simulation time 30524425 ps
CPU time 0.97 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 195672 kb
Host smart-ddbbb1b5-edb9-4397-9d62-e422b8de88a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009155178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2009155178
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3656869099
Short name T1
Test name
Test status
Simulation time 24665839991 ps
CPU time 134.39 seconds
Started Mar 17 02:51:55 PM PDT 24
Finished Mar 17 02:54:10 PM PDT 24
Peak memory 198180 kb
Host smart-3c799756-97ea-4032-8e63-c5e0dbb0a6ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656869099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3656869099
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1528136949
Short name T312
Test name
Test status
Simulation time 114105849 ps
CPU time 0.56 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:56 PM PDT 24
Peak memory 193928 kb
Host smart-61a6408e-b866-4416-95f3-b4badc9bc05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528136949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1528136949
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.870910033
Short name T530
Test name
Test status
Simulation time 21419585 ps
CPU time 0.73 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:51:59 PM PDT 24
Peak memory 195216 kb
Host smart-69d1f102-45be-4a03-8bfc-71afc5c323a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870910033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.870910033
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.782263808
Short name T174
Test name
Test status
Simulation time 453694097 ps
CPU time 22.08 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:25 PM PDT 24
Peak memory 196904 kb
Host smart-209ea3c4-c850-4967-9c16-ea58e9e07c29
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782263808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.782263808
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2711093356
Short name T449
Test name
Test status
Simulation time 25041352 ps
CPU time 0.72 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 195196 kb
Host smart-db40eb28-4a01-49e9-9230-b092e8e3316a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711093356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2711093356
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1655705336
Short name T603
Test name
Test status
Simulation time 284217078 ps
CPU time 0.98 seconds
Started Mar 17 02:51:59 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 196812 kb
Host smart-65bfcc53-58d2-46cc-b74e-1b8c34bfa712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655705336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1655705336
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1643179959
Short name T400
Test name
Test status
Simulation time 277272351 ps
CPU time 3.25 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 198060 kb
Host smart-eab4a908-a023-4f7b-ac8d-b9299cec3030
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643179959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1643179959
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1890235142
Short name T224
Test name
Test status
Simulation time 1078324253 ps
CPU time 2.96 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 197148 kb
Host smart-99e215bb-c8fb-4cfa-ac65-4bb2ffb84a8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890235142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1890235142
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.693927045
Short name T241
Test name
Test status
Simulation time 60557893 ps
CPU time 1.07 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:51:59 PM PDT 24
Peak memory 195788 kb
Host smart-88a8025a-7f25-4906-ab50-65030170b2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693927045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.693927045
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1992620974
Short name T200
Test name
Test status
Simulation time 93132542 ps
CPU time 0.9 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:51:54 PM PDT 24
Peak memory 195620 kb
Host smart-811587f4-7411-4432-a2f5-d3829a04c091
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992620974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1992620974
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2271957445
Short name T159
Test name
Test status
Simulation time 317601663 ps
CPU time 3.48 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 197984 kb
Host smart-6a91a66e-a057-4bab-884b-375cf53c19c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271957445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2271957445
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2465394360
Short name T629
Test name
Test status
Simulation time 212930090 ps
CPU time 0.94 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 196208 kb
Host smart-d424c323-4d64-4341-a6d7-d946244345e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465394360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2465394360
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.299404600
Short name T564
Test name
Test status
Simulation time 220130516 ps
CPU time 1.41 seconds
Started Mar 17 02:51:52 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 197964 kb
Host smart-e7813fac-d1f0-4276-b59f-baef58edd5cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299404600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.299404600
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3043877865
Short name T619
Test name
Test status
Simulation time 261626804607 ps
CPU time 147.83 seconds
Started Mar 17 02:51:51 PM PDT 24
Finished Mar 17 02:54:19 PM PDT 24
Peak memory 198132 kb
Host smart-06f4bb8f-0167-4d15-9b06-bfb464d2d8b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043877865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3043877865
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.4037011027
Short name T545
Test name
Test status
Simulation time 33049069457 ps
CPU time 887.84 seconds
Started Mar 17 02:51:57 PM PDT 24
Finished Mar 17 03:06:45 PM PDT 24
Peak memory 198220 kb
Host smart-cc909e82-51cc-463b-8833-d0aebc886724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4037011027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.4037011027
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3259955395
Short name T438
Test name
Test status
Simulation time 63599207 ps
CPU time 0.55 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:12 PM PDT 24
Peak memory 193960 kb
Host smart-55de48f6-c738-4efc-8f08-e72934d27b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259955395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3259955395
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1367126489
Short name T193
Test name
Test status
Simulation time 27650042 ps
CPU time 0.74 seconds
Started Mar 17 02:51:19 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 195212 kb
Host smart-5042f7f1-e9a3-49d2-b09f-f4669562975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367126489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1367126489
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2381095216
Short name T676
Test name
Test status
Simulation time 478671134 ps
CPU time 24.78 seconds
Started Mar 17 02:51:15 PM PDT 24
Finished Mar 17 02:51:40 PM PDT 24
Peak memory 197100 kb
Host smart-fe240d74-a9a8-4795-ab2c-3ccb86983c3e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381095216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2381095216
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3631410415
Short name T31
Test name
Test status
Simulation time 65101991 ps
CPU time 0.99 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:22 PM PDT 24
Peak memory 196640 kb
Host smart-1f2d065e-c1dd-49ad-a7db-894f5c048f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631410415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3631410415
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2019947635
Short name T186
Test name
Test status
Simulation time 158935313 ps
CPU time 1.25 seconds
Started Mar 17 02:51:18 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 197060 kb
Host smart-69a813fb-4c3f-45c5-9a0b-7c97e4b389eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019947635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2019947635
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2067482248
Short name T179
Test name
Test status
Simulation time 32118641 ps
CPU time 1.38 seconds
Started Mar 17 02:51:19 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 196656 kb
Host smart-07293f1e-f7b1-4fa4-a0d3-91cc5bd9927b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067482248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2067482248
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.478720064
Short name T365
Test name
Test status
Simulation time 96045422 ps
CPU time 0.92 seconds
Started Mar 17 02:51:12 PM PDT 24
Finished Mar 17 02:51:13 PM PDT 24
Peak memory 196564 kb
Host smart-97ef6c8e-a9b4-42af-a113-8cd1aedf4d52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478720064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.478720064
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3336965039
Short name T340
Test name
Test status
Simulation time 49148950 ps
CPU time 1.04 seconds
Started Mar 17 02:51:14 PM PDT 24
Finished Mar 17 02:51:15 PM PDT 24
Peak memory 196052 kb
Host smart-a25696eb-ade1-428a-9756-d716ef403e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336965039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3336965039
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.676694375
Short name T445
Test name
Test status
Simulation time 57607023 ps
CPU time 0.73 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:22 PM PDT 24
Peak memory 194964 kb
Host smart-e775a1e9-af51-43b8-8f7d-33c1b4aca0d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676694375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.676694375
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1733490890
Short name T584
Test name
Test status
Simulation time 76331033 ps
CPU time 1.21 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:13 PM PDT 24
Peak memory 198000 kb
Host smart-3e1a1399-fb04-44be-b716-08e597d8ee4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733490890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1733490890
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3986977378
Short name T52
Test name
Test status
Simulation time 61782796 ps
CPU time 0.87 seconds
Started Mar 17 02:51:20 PM PDT 24
Finished Mar 17 02:51:21 PM PDT 24
Peak memory 213872 kb
Host smart-4acd87e5-ec02-496e-8dd1-c0bcf3ae7019
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986977378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3986977378
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3038602020
Short name T461
Test name
Test status
Simulation time 60225754 ps
CPU time 1.1 seconds
Started Mar 17 02:51:15 PM PDT 24
Finished Mar 17 02:51:16 PM PDT 24
Peak memory 195584 kb
Host smart-e39d474f-f6d7-4e47-899a-6e8aff57281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038602020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3038602020
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3250544166
Short name T334
Test name
Test status
Simulation time 100057505 ps
CPU time 1.47 seconds
Started Mar 17 02:51:17 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 196688 kb
Host smart-b0b8761c-0361-4e63-99e6-7a2d63abc0aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250544166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3250544166
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3561709114
Short name T496
Test name
Test status
Simulation time 5995879962 ps
CPU time 44.62 seconds
Started Mar 17 02:51:13 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 198116 kb
Host smart-fda9c5dc-8234-4549-8822-a3f561acaa19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561709114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3561709114
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.3955746206
Short name T65
Test name
Test status
Simulation time 64113629795 ps
CPU time 1700.44 seconds
Started Mar 17 02:51:15 PM PDT 24
Finished Mar 17 03:19:36 PM PDT 24
Peak memory 198228 kb
Host smart-0d5c5c82-934f-4f58-8c3d-dfa49e06b832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3955746206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.3955746206
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1996624844
Short name T548
Test name
Test status
Simulation time 26627524 ps
CPU time 0.62 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 193892 kb
Host smart-295ba9d8-0e2a-4645-a8f8-f8127747372f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996624844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1996624844
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.729109521
Short name T480
Test name
Test status
Simulation time 133483210 ps
CPU time 0.75 seconds
Started Mar 17 02:51:57 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 194156 kb
Host smart-3b914244-ba11-4c42-8023-add018e1db19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729109521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.729109521
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2836360959
Short name T667
Test name
Test status
Simulation time 2236457046 ps
CPU time 23.07 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:27 PM PDT 24
Peak memory 196928 kb
Host smart-582d1449-34ed-457e-b847-0062a0302391
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836360959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2836360959
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.697208295
Short name T473
Test name
Test status
Simulation time 45903518 ps
CPU time 0.7 seconds
Started Mar 17 02:51:55 PM PDT 24
Finished Mar 17 02:51:56 PM PDT 24
Peak memory 194728 kb
Host smart-a51431a8-29c6-4e1d-af31-7b910b907619
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697208295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.697208295
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2931699164
Short name T335
Test name
Test status
Simulation time 169619124 ps
CPU time 1.13 seconds
Started Mar 17 02:51:59 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 195952 kb
Host smart-c894e78e-04a9-47fd-8d27-ad329a04d03e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931699164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2931699164
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2627415043
Short name T187
Test name
Test status
Simulation time 85473974 ps
CPU time 0.98 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 196276 kb
Host smart-0079935a-7750-4f2a-a1c9-6957ba75a2ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627415043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2627415043
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2748343429
Short name T72
Test name
Test status
Simulation time 661237007 ps
CPU time 2.61 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:06 PM PDT 24
Peak memory 197144 kb
Host smart-f96f9118-aa16-4de4-953a-8ab8e1c1cfbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748343429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2748343429
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.905710126
Short name T578
Test name
Test status
Simulation time 39960542 ps
CPU time 0.99 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:03 PM PDT 24
Peak memory 195880 kb
Host smart-6ddb25b4-611c-44fd-84a5-5d4f2b75d9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905710126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.905710126
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3336628746
Short name T407
Test name
Test status
Simulation time 132874522 ps
CPU time 1.25 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 196980 kb
Host smart-3acdf38f-9fc6-4359-bc01-73e2f339bd3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336628746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3336628746
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.720097980
Short name T337
Test name
Test status
Simulation time 305978236 ps
CPU time 4.26 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 197880 kb
Host smart-f9cdd6bc-47c5-4826-987e-46905df2df21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720097980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.720097980
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.4130822058
Short name T333
Test name
Test status
Simulation time 148097302 ps
CPU time 1.18 seconds
Started Mar 17 02:51:59 PM PDT 24
Finished Mar 17 02:52:00 PM PDT 24
Peak memory 196556 kb
Host smart-347be2c7-46a6-43e9-a8aa-ba4d6a61c395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130822058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.4130822058
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1810809682
Short name T168
Test name
Test status
Simulation time 153424016 ps
CPU time 1.15 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 196580 kb
Host smart-55c3618a-9ac2-473d-8fc5-b529f9eaf897
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810809682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1810809682
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.770766668
Short name T7
Test name
Test status
Simulation time 78651840931 ps
CPU time 207.43 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:55:23 PM PDT 24
Peak memory 198196 kb
Host smart-cefcebb9-daa2-463a-9d37-09d594708078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770766668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.770766668
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.542416204
Short name T464
Test name
Test status
Simulation time 39057017528 ps
CPU time 1053.55 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 03:09:29 PM PDT 24
Peak memory 198244 kb
Host smart-f118cfde-4c72-42ec-8467-3f23b46eecd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=542416204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.542416204
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2188626662
Short name T602
Test name
Test status
Simulation time 55613815 ps
CPU time 0.57 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:08 PM PDT 24
Peak memory 194940 kb
Host smart-d8902a80-8c7f-4ae7-8c94-034559f03884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188626662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2188626662
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1085532638
Short name T659
Test name
Test status
Simulation time 48667762 ps
CPU time 0.71 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:51:59 PM PDT 24
Peak memory 194188 kb
Host smart-01b8c5e4-4204-4fcb-8be7-c7e8d0107e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085532638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1085532638
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.273856463
Short name T573
Test name
Test status
Simulation time 1675063908 ps
CPU time 13.73 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:20 PM PDT 24
Peak memory 197984 kb
Host smart-7a6b0cd5-ebc2-47c8-91d5-403b5bcb1974
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273856463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.273856463
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.546569894
Short name T654
Test name
Test status
Simulation time 277390024 ps
CPU time 0.86 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 195880 kb
Host smart-38ce6aae-ff05-412d-9a60-201ffe1b1dc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546569894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.546569894
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2696474349
Short name T477
Test name
Test status
Simulation time 77070702 ps
CPU time 1.39 seconds
Started Mar 17 02:51:55 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 197172 kb
Host smart-135c0140-c594-4352-866e-4e05c2490cfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696474349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2696474349
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4132201341
Short name T537
Test name
Test status
Simulation time 296608770 ps
CPU time 2.82 seconds
Started Mar 17 02:51:57 PM PDT 24
Finished Mar 17 02:52:00 PM PDT 24
Peak memory 198060 kb
Host smart-7bf734da-90bd-4f94-853f-b8eed58cda32
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132201341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4132201341
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2919804767
Short name T55
Test name
Test status
Simulation time 437710781 ps
CPU time 2.12 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 198068 kb
Host smart-383fd68d-547e-495b-8568-f60c3dde95c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919804767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2919804767
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2143554411
Short name T624
Test name
Test status
Simulation time 62808020 ps
CPU time 0.8 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 195516 kb
Host smart-10521f76-32a8-4838-8168-9f52a982eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143554411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2143554411
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2681583073
Short name T637
Test name
Test status
Simulation time 43482204 ps
CPU time 0.89 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 196060 kb
Host smart-f9911c9a-9c8e-45be-ba7e-4c60b6476fb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681583073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2681583073
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1726734120
Short name T386
Test name
Test status
Simulation time 358046497 ps
CPU time 6.09 seconds
Started Mar 17 02:51:54 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 198012 kb
Host smart-57dc7730-4732-42a0-923b-dba2b04b9621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726734120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1726734120
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.362069151
Short name T398
Test name
Test status
Simulation time 146664606 ps
CPU time 1.38 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 198020 kb
Host smart-9b51dbc0-a3e2-41a7-9e9c-31546a6813cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362069151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.362069151
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2154951405
Short name T305
Test name
Test status
Simulation time 75742959 ps
CPU time 1.18 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:51:59 PM PDT 24
Peak memory 195736 kb
Host smart-b8be9a75-e6ef-47f6-8732-36683ab1aef9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154951405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2154951405
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3545765923
Short name T184
Test name
Test status
Simulation time 2524735532 ps
CPU time 74.7 seconds
Started Mar 17 02:51:56 PM PDT 24
Finished Mar 17 02:53:11 PM PDT 24
Peak memory 198200 kb
Host smart-d539400d-89ab-4c21-87f8-d548f8ccdde7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545765923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3545765923
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3616308936
Short name T641
Test name
Test status
Simulation time 67557256020 ps
CPU time 1171.23 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 03:11:31 PM PDT 24
Peak memory 198208 kb
Host smart-9f7fdf8e-b5c9-4da0-aab7-a9e2bcca54c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3616308936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3616308936
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.42284070
Short name T527
Test name
Test status
Simulation time 14702434 ps
CPU time 0.64 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 195012 kb
Host smart-22128607-2ab0-4ba1-a870-8a3f34523bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42284070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.42284070
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2332482919
Short name T248
Test name
Test status
Simulation time 42427722 ps
CPU time 0.67 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 194168 kb
Host smart-1820fe80-f7df-448b-9841-3ff43dc37cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332482919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2332482919
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.182815352
Short name T304
Test name
Test status
Simulation time 882590379 ps
CPU time 23.18 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:24 PM PDT 24
Peak memory 197064 kb
Host smart-53cef1c1-da40-4b31-86c2-7433981cb0c2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182815352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.182815352
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.757812278
Short name T336
Test name
Test status
Simulation time 120255792 ps
CPU time 0.86 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 196700 kb
Host smart-73837db3-0d13-4936-bb36-6365419995fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757812278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.757812278
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3430294625
Short name T255
Test name
Test status
Simulation time 81601013 ps
CPU time 1.42 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:06 PM PDT 24
Peak memory 197152 kb
Host smart-929223f8-0b81-4a39-86ed-926a49b37f9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430294625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3430294625
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1427603496
Short name T57
Test name
Test status
Simulation time 101483278 ps
CPU time 2.18 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:03 PM PDT 24
Peak memory 198060 kb
Host smart-3574d8cf-bd70-44b7-bf04-a359f5b75d3e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427603496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1427603496
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3756923254
Short name T709
Test name
Test status
Simulation time 357759357 ps
CPU time 2.59 seconds
Started Mar 17 02:52:24 PM PDT 24
Finished Mar 17 02:52:31 PM PDT 24
Peak memory 196472 kb
Host smart-a7a0bfe4-4d51-4d1c-86d2-f9185825ce64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756923254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3756923254
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3899073922
Short name T518
Test name
Test status
Simulation time 19727675 ps
CPU time 0.67 seconds
Started Mar 17 02:51:53 PM PDT 24
Finished Mar 17 02:51:55 PM PDT 24
Peak memory 195012 kb
Host smart-2e2b6b1b-93ca-402a-b535-475c38884fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899073922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3899073922
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.4245482997
Short name T556
Test name
Test status
Simulation time 87764215 ps
CPU time 0.71 seconds
Started Mar 17 02:51:56 PM PDT 24
Finished Mar 17 02:51:57 PM PDT 24
Peak memory 195344 kb
Host smart-0ae43169-4dfc-4ad2-b9e9-c75e74cb2ec7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245482997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.4245482997
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3298844490
Short name T634
Test name
Test status
Simulation time 581317231 ps
CPU time 5.44 seconds
Started Mar 17 02:51:59 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 198032 kb
Host smart-7cce94ae-902a-4ae4-a018-2ee3330a22c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298844490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3298844490
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.766794085
Short name T251
Test name
Test status
Simulation time 97669448 ps
CPU time 1.12 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 195728 kb
Host smart-42d01189-7089-4327-862f-ff1c8ad24e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766794085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.766794085
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3465931506
Short name T707
Test name
Test status
Simulation time 302229992 ps
CPU time 1.22 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:51:59 PM PDT 24
Peak memory 196484 kb
Host smart-e5ff64cf-406a-4dbd-9100-ab3b34300652
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465931506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3465931506
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1598596895
Short name T714
Test name
Test status
Simulation time 59991537619 ps
CPU time 177.47 seconds
Started Mar 17 02:52:09 PM PDT 24
Finished Mar 17 02:55:11 PM PDT 24
Peak memory 198120 kb
Host smart-b8d072e7-ef73-41c7-bef2-98bdffcf4606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598596895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1598596895
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3092326892
Short name T683
Test name
Test status
Simulation time 23188690 ps
CPU time 0.58 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 194128 kb
Host smart-39cb3e5f-c04a-478b-ac29-ebfe09cd5da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092326892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3092326892
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.412134076
Short name T579
Test name
Test status
Simulation time 67986958 ps
CPU time 0.78 seconds
Started Mar 17 02:52:18 PM PDT 24
Finished Mar 17 02:52:20 PM PDT 24
Peak memory 195432 kb
Host smart-4c4c974d-724c-41d4-ad31-89c7c044e034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412134076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.412134076
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.285080577
Short name T191
Test name
Test status
Simulation time 12436781394 ps
CPU time 26.71 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:28 PM PDT 24
Peak memory 195920 kb
Host smart-eaa59a1a-b4b2-4cf9-82d5-a96c3fafee1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285080577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.285080577
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1687430764
Short name T164
Test name
Test status
Simulation time 27024377 ps
CPU time 0.72 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 194768 kb
Host smart-1ccd31ea-0270-42ae-9277-8a6b4800b0e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687430764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1687430764
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3875651127
Short name T197
Test name
Test status
Simulation time 80683569 ps
CPU time 1.24 seconds
Started Mar 17 02:51:57 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 196164 kb
Host smart-0710995d-0619-4844-84d4-e47770c46fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875651127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3875651127
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.4001075206
Short name T699
Test name
Test status
Simulation time 89907891 ps
CPU time 3.3 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 198060 kb
Host smart-b024802b-b7ec-4519-9908-19d5dff10e90
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001075206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.4001075206
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3252049252
Short name T272
Test name
Test status
Simulation time 79567791 ps
CPU time 2.35 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 195832 kb
Host smart-7a4358f4-e4da-4b35-9c39-dfb40edf42c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252049252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3252049252
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3612362357
Short name T505
Test name
Test status
Simulation time 18671600 ps
CPU time 0.78 seconds
Started Mar 17 02:52:11 PM PDT 24
Finished Mar 17 02:52:13 PM PDT 24
Peak memory 196272 kb
Host smart-c7424830-b1f1-4b53-a1f1-1089e86dd09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612362357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3612362357
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3038053464
Short name T23
Test name
Test status
Simulation time 28791640 ps
CPU time 0.66 seconds
Started Mar 17 02:52:11 PM PDT 24
Finished Mar 17 02:52:12 PM PDT 24
Peak memory 194380 kb
Host smart-7c2beea0-3120-4eba-88bf-7751c2e8a797
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038053464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3038053464
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3688858260
Short name T33
Test name
Test status
Simulation time 364348704 ps
CPU time 5.91 seconds
Started Mar 17 02:52:12 PM PDT 24
Finished Mar 17 02:52:18 PM PDT 24
Peak memory 197956 kb
Host smart-22b17e08-164b-4a15-8232-1284c233ea32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688858260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3688858260
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.347548539
Short name T306
Test name
Test status
Simulation time 33367360 ps
CPU time 1.16 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:52:00 PM PDT 24
Peak memory 195860 kb
Host smart-9c6830f5-20dc-4058-9ea7-ff242ba2fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347548539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.347548539
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.694808309
Short name T420
Test name
Test status
Simulation time 250626083 ps
CPU time 0.99 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 196492 kb
Host smart-0a0a5b0a-f251-489f-a313-ff081ea2617f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694808309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.694808309
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1441063116
Short name T359
Test name
Test status
Simulation time 20855511375 ps
CPU time 56.86 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:52:56 PM PDT 24
Peak memory 198180 kb
Host smart-5e68a193-1795-4178-b1b5-e12191f90f24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441063116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1441063116
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1473548393
Short name T528
Test name
Test status
Simulation time 16380772 ps
CPU time 0.56 seconds
Started Mar 17 02:52:20 PM PDT 24
Finished Mar 17 02:52:22 PM PDT 24
Peak memory 193912 kb
Host smart-46ef216c-087f-4fdb-be58-46648400cdaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473548393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1473548393
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1094471878
Short name T416
Test name
Test status
Simulation time 41712103 ps
CPU time 0.65 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 194408 kb
Host smart-7aad5de1-1e5c-4db3-85a1-b65ca9318a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094471878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1094471878
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3409588258
Short name T621
Test name
Test status
Simulation time 1596452556 ps
CPU time 19.97 seconds
Started Mar 17 02:51:59 PM PDT 24
Finished Mar 17 02:52:19 PM PDT 24
Peak memory 196268 kb
Host smart-f912aa02-d92f-4c06-9d7f-8e15e04e171b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409588258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3409588258
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1576253135
Short name T504
Test name
Test status
Simulation time 87435291 ps
CPU time 1.04 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 196648 kb
Host smart-811af6ec-1912-4960-bd7b-0de62fdf23ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576253135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1576253135
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.598248271
Short name T395
Test name
Test status
Simulation time 72710367 ps
CPU time 1.35 seconds
Started Mar 17 02:52:15 PM PDT 24
Finished Mar 17 02:52:16 PM PDT 24
Peak memory 196944 kb
Host smart-72b87895-a502-410d-96fa-22d3da1b26ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598248271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.598248271
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3398961952
Short name T434
Test name
Test status
Simulation time 183092473 ps
CPU time 1.95 seconds
Started Mar 17 02:52:12 PM PDT 24
Finished Mar 17 02:52:14 PM PDT 24
Peak memory 198048 kb
Host smart-5adec133-6b31-461b-9da6-26bc7ff0432a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398961952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3398961952
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2122998709
Short name T596
Test name
Test status
Simulation time 440272418 ps
CPU time 3.21 seconds
Started Mar 17 02:52:09 PM PDT 24
Finished Mar 17 02:52:12 PM PDT 24
Peak memory 197980 kb
Host smart-244e9b36-2898-4763-9a8d-291112e2f929
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122998709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2122998709
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.396607584
Short name T352
Test name
Test status
Simulation time 272500217 ps
CPU time 0.91 seconds
Started Mar 17 02:52:05 PM PDT 24
Finished Mar 17 02:52:06 PM PDT 24
Peak memory 195824 kb
Host smart-3759182d-933b-4eca-8297-50be7efef308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396607584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.396607584
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2035835665
Short name T402
Test name
Test status
Simulation time 97561555 ps
CPU time 1.03 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 196076 kb
Host smart-ab7c8276-2b04-4399-948b-7a8c401a3ac5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035835665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2035835665
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3407063834
Short name T483
Test name
Test status
Simulation time 1093058407 ps
CPU time 4.79 seconds
Started Mar 17 02:52:13 PM PDT 24
Finished Mar 17 02:52:18 PM PDT 24
Peak memory 197932 kb
Host smart-08f5d1e4-1ed3-4ad4-a936-c12f83521afa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407063834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3407063834
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.914888564
Short name T353
Test name
Test status
Simulation time 31102902 ps
CPU time 0.85 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 195220 kb
Host smart-0e0ec67b-ab0a-499d-9062-86f5c76457fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914888564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.914888564
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3814557143
Short name T315
Test name
Test status
Simulation time 61664917 ps
CPU time 1.16 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 196452 kb
Host smart-855d772e-f3b6-4ab4-8383-668abaef11ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814557143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3814557143
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3617072425
Short name T482
Test name
Test status
Simulation time 6384658348 ps
CPU time 186.93 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:55:11 PM PDT 24
Peak memory 198124 kb
Host smart-4dd4b303-0a47-470e-9405-d7ae442ded3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617072425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3617072425
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1352889188
Short name T20
Test name
Test status
Simulation time 16378637319 ps
CPU time 241.91 seconds
Started Mar 17 02:52:09 PM PDT 24
Finished Mar 17 02:56:11 PM PDT 24
Peak memory 198236 kb
Host smart-dcce4158-952d-4806-90ed-cae655cac743
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1352889188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1352889188
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1594445281
Short name T293
Test name
Test status
Simulation time 14875246 ps
CPU time 0.58 seconds
Started Mar 17 02:52:14 PM PDT 24
Finished Mar 17 02:52:15 PM PDT 24
Peak memory 193920 kb
Host smart-a40fc15a-d6f7-44db-8db9-504971ffc6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594445281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1594445281
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2476885619
Short name T24
Test name
Test status
Simulation time 22811919 ps
CPU time 0.81 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:03 PM PDT 24
Peak memory 195216 kb
Host smart-b49b721a-f450-4978-9b31-961255d45083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476885619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2476885619
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1986203463
Short name T439
Test name
Test status
Simulation time 1208104648 ps
CPU time 10.11 seconds
Started Mar 17 02:51:59 PM PDT 24
Finished Mar 17 02:52:09 PM PDT 24
Peak memory 196972 kb
Host smart-1af40b8e-27de-4e1f-9d1a-4bb11982f049
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986203463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1986203463
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3720445931
Short name T674
Test name
Test status
Simulation time 346205209 ps
CPU time 1.11 seconds
Started Mar 17 02:52:12 PM PDT 24
Finished Mar 17 02:52:13 PM PDT 24
Peak memory 196616 kb
Host smart-eea696f4-b1dd-49ef-9bbd-799a64d39e88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720445931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3720445931
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3482707108
Short name T630
Test name
Test status
Simulation time 112574241 ps
CPU time 0.92 seconds
Started Mar 17 02:52:24 PM PDT 24
Finished Mar 17 02:52:25 PM PDT 24
Peak memory 195952 kb
Host smart-1ca1ea25-6a8c-4604-90a5-0167f27a91ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482707108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3482707108
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2956070692
Short name T640
Test name
Test status
Simulation time 264901897 ps
CPU time 2.94 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:06 PM PDT 24
Peak memory 198096 kb
Host smart-2d57bd66-6158-4cd8-a570-5ff4e5fb331f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956070692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2956070692
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4015307045
Short name T350
Test name
Test status
Simulation time 691962131 ps
CPU time 2.64 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 196892 kb
Host smart-1010f87b-63e3-460e-aa72-6900fc0a21f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015307045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4015307045
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1722390684
Short name T225
Test name
Test status
Simulation time 84145472 ps
CPU time 0.75 seconds
Started Mar 17 02:52:20 PM PDT 24
Finished Mar 17 02:52:22 PM PDT 24
Peak memory 196272 kb
Host smart-5bc24e77-a0ee-4520-a6d3-48ca755800d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722390684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1722390684
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3254031950
Short name T234
Test name
Test status
Simulation time 120864373 ps
CPU time 0.94 seconds
Started Mar 17 02:52:18 PM PDT 24
Finished Mar 17 02:52:20 PM PDT 24
Peak memory 196492 kb
Host smart-384059f1-2157-4c2c-9901-60555646d649
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254031950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3254031950
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3107412560
Short name T592
Test name
Test status
Simulation time 1109403272 ps
CPU time 3.36 seconds
Started Mar 17 02:51:58 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 197808 kb
Host smart-55f12ef5-1f9f-483e-8550-0dfe33b72c88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107412560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3107412560
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4229250990
Short name T367
Test name
Test status
Simulation time 39070839 ps
CPU time 1.1 seconds
Started Mar 17 02:52:05 PM PDT 24
Finished Mar 17 02:52:06 PM PDT 24
Peak memory 195792 kb
Host smart-12f60855-cce9-48a1-a6f6-b45ec8b7db94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229250990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4229250990
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.968511174
Short name T361
Test name
Test status
Simulation time 33865070 ps
CPU time 1.11 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:10 PM PDT 24
Peak memory 196484 kb
Host smart-7eb9e937-1f83-4a83-89c7-78ad6256048f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968511174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.968511174
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2701711988
Short name T656
Test name
Test status
Simulation time 95361537704 ps
CPU time 141.67 seconds
Started Mar 17 02:52:13 PM PDT 24
Finished Mar 17 02:54:35 PM PDT 24
Peak memory 198140 kb
Host smart-c6b20418-7a90-4aab-a021-dccf16399497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701711988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2701711988
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3124307932
Short name T295
Test name
Test status
Simulation time 13356340 ps
CPU time 0.59 seconds
Started Mar 17 02:52:13 PM PDT 24
Finished Mar 17 02:52:14 PM PDT 24
Peak memory 193896 kb
Host smart-6978bbfd-bdb8-4f7a-8ef5-21812b79e3db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124307932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3124307932
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2468873880
Short name T594
Test name
Test status
Simulation time 154167723 ps
CPU time 0.75 seconds
Started Mar 17 02:51:59 PM PDT 24
Finished Mar 17 02:52:00 PM PDT 24
Peak memory 195320 kb
Host smart-7f47844c-280e-4756-bce5-88eddad3346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468873880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2468873880
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3397757869
Short name T550
Test name
Test status
Simulation time 2824694212 ps
CPU time 19.39 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:28 PM PDT 24
Peak memory 197172 kb
Host smart-5da8bf67-adaf-45f8-abf6-c48c84030fee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397757869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3397757869
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.771630495
Short name T10
Test name
Test status
Simulation time 1775804017 ps
CPU time 1.09 seconds
Started Mar 17 02:52:00 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 196508 kb
Host smart-8381baa8-3d14-4d19-9aa4-0ddec1c9e128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771630495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.771630495
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1774258516
Short name T118
Test name
Test status
Simulation time 105177707 ps
CPU time 1.08 seconds
Started Mar 17 02:52:12 PM PDT 24
Finished Mar 17 02:52:14 PM PDT 24
Peak memory 195984 kb
Host smart-4eeeed99-a29c-4c83-bb06-1bc51c41fe40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774258516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1774258516
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1647290405
Short name T425
Test name
Test status
Simulation time 34118705 ps
CPU time 1.04 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 196940 kb
Host smart-ed8ec484-51dc-4665-ab0d-9c0c2dbbf24a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647290405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1647290405
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2823744585
Short name T557
Test name
Test status
Simulation time 402784797 ps
CPU time 3.31 seconds
Started Mar 17 02:51:57 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 198052 kb
Host smart-4feee33a-b24c-4ec2-a656-de3e51c7e06c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823744585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2823744585
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1692181177
Short name T214
Test name
Test status
Simulation time 23076534 ps
CPU time 1.08 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:03 PM PDT 24
Peak memory 195936 kb
Host smart-0df91665-9be8-48af-9129-888e95f6ce19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692181177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1692181177
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1242164735
Short name T246
Test name
Test status
Simulation time 160905883 ps
CPU time 1.12 seconds
Started Mar 17 02:52:07 PM PDT 24
Finished Mar 17 02:52:09 PM PDT 24
Peak memory 195868 kb
Host smart-421416b2-fa31-4dd3-b90d-ffba43757b32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242164735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1242164735
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1797265589
Short name T646
Test name
Test status
Simulation time 99726436 ps
CPU time 2.57 seconds
Started Mar 17 02:52:26 PM PDT 24
Finished Mar 17 02:52:29 PM PDT 24
Peak memory 197944 kb
Host smart-55187943-7709-4627-9df8-2944973da89a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797265589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1797265589
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.254138754
Short name T710
Test name
Test status
Simulation time 110024022 ps
CPU time 1.22 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 197972 kb
Host smart-9f3d72e2-372e-4edf-82a0-3d56afed1995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254138754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.254138754
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1848927648
Short name T135
Test name
Test status
Simulation time 73966388 ps
CPU time 1.43 seconds
Started Mar 17 02:52:09 PM PDT 24
Finished Mar 17 02:52:10 PM PDT 24
Peak memory 196864 kb
Host smart-e5e94154-df17-43a9-99c0-b78cb74a58eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848927648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1848927648
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.318113866
Short name T201
Test name
Test status
Simulation time 28339747796 ps
CPU time 183.81 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:55:07 PM PDT 24
Peak memory 198172 kb
Host smart-ca5d8ba4-ca69-4b6f-9776-06c492a2cf42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318113866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.318113866
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2477100008
Short name T433
Test name
Test status
Simulation time 333479316584 ps
CPU time 1816.73 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 03:22:19 PM PDT 24
Peak memory 198232 kb
Host smart-2548961f-c589-40f5-8773-b5631b4abfc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2477100008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2477100008
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2839855924
Short name T128
Test name
Test status
Simulation time 33358516 ps
CPU time 0.58 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:14 PM PDT 24
Peak memory 194636 kb
Host smart-cda73121-62c4-4ab7-9337-f7c0cefcacbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839855924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2839855924
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1805321590
Short name T623
Test name
Test status
Simulation time 42902947 ps
CPU time 0.89 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 196424 kb
Host smart-d082eba2-7db5-4f81-8fc1-881e12ddbe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805321590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1805321590
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1065786434
Short name T382
Test name
Test status
Simulation time 232634824 ps
CPU time 12.9 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:15 PM PDT 24
Peak memory 196676 kb
Host smart-79af6342-f321-4c01-a31c-edc121693bab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065786434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1065786434
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.611707313
Short name T649
Test name
Test status
Simulation time 224511705 ps
CPU time 0.92 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 196744 kb
Host smart-2d755af7-af5e-4444-8113-25271fe45537
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611707313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.611707313
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2516884893
Short name T137
Test name
Test status
Simulation time 332094994 ps
CPU time 1.31 seconds
Started Mar 17 02:52:09 PM PDT 24
Finished Mar 17 02:52:10 PM PDT 24
Peak memory 198084 kb
Host smart-9b9b1bd9-fdfa-41f6-b3d2-ca73ef700e92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516884893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2516884893
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4168646120
Short name T291
Test name
Test status
Simulation time 286639183 ps
CPU time 2.93 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:06 PM PDT 24
Peak memory 198084 kb
Host smart-30985ffd-84c0-4116-9e32-973d0b5dd5b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168646120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4168646120
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1278209018
Short name T662
Test name
Test status
Simulation time 450531178 ps
CPU time 3.48 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:08 PM PDT 24
Peak memory 198044 kb
Host smart-51c644a7-244f-454a-8da4-117a6a9eb98e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278209018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1278209018
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1751200060
Short name T297
Test name
Test status
Simulation time 120791146 ps
CPU time 1.22 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 197396 kb
Host smart-3c5b4329-a106-4bef-b391-cbd4acc08856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751200060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1751200060
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2572903562
Short name T258
Test name
Test status
Simulation time 33615881 ps
CPU time 0.74 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:03 PM PDT 24
Peak memory 195436 kb
Host smart-efb9cc76-eba7-46f4-81b0-6b462bb87784
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572903562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2572903562
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2668571479
Short name T643
Test name
Test status
Simulation time 875647025 ps
CPU time 3.22 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 197796 kb
Host smart-b3ed6aed-a1c3-47c5-983f-f85348075ebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668571479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2668571479
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1847440432
Short name T599
Test name
Test status
Simulation time 231326139 ps
CPU time 1.07 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 196364 kb
Host smart-f8f84847-db32-4dfa-acac-e3156cbed199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847440432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1847440432
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1783806077
Short name T226
Test name
Test status
Simulation time 207976786 ps
CPU time 0.78 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 195232 kb
Host smart-3422297d-1473-4ef6-8202-4527ccaf3050
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783806077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1783806077
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2873104441
Short name T265
Test name
Test status
Simulation time 7229418653 ps
CPU time 24.17 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:28 PM PDT 24
Peak memory 198220 kb
Host smart-5134ae95-d233-42eb-8141-525810fc384f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873104441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2873104441
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3446776882
Short name T608
Test name
Test status
Simulation time 203622941624 ps
CPU time 2229.47 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 03:29:18 PM PDT 24
Peak memory 198264 kb
Host smart-4c763f3b-3d00-43ee-8392-ccb6d6c245f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3446776882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.3446776882
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1925830332
Short name T317
Test name
Test status
Simulation time 14078989 ps
CPU time 0.61 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 194836 kb
Host smart-27c17cd3-cc34-4a9f-b7c6-b9a4b4007112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925830332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1925830332
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3693572274
Short name T301
Test name
Test status
Simulation time 46719747 ps
CPU time 0.84 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 196364 kb
Host smart-fcb109d4-5c56-4f5f-adea-21d5ae14b485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693572274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3693572274
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2137083864
Short name T181
Test name
Test status
Simulation time 351024115 ps
CPU time 8.56 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:14 PM PDT 24
Peak memory 197996 kb
Host smart-2e815655-849e-4b4a-865e-c5c181c7c2a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137083864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2137083864
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3843903629
Short name T139
Test name
Test status
Simulation time 70960657 ps
CPU time 1.04 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:09 PM PDT 24
Peak memory 197284 kb
Host smart-fad60bc4-8846-4331-aab6-03fce0d4d8b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843903629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3843903629
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1427210544
Short name T577
Test name
Test status
Simulation time 164364092 ps
CPU time 1.39 seconds
Started Mar 17 02:52:07 PM PDT 24
Finished Mar 17 02:52:08 PM PDT 24
Peak memory 197264 kb
Host smart-fc9fc219-bceb-456b-9fd9-72deba54526f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427210544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1427210544
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2370378777
Short name T302
Test name
Test status
Simulation time 20554237 ps
CPU time 1.02 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 197112 kb
Host smart-da802871-dca8-41a5-8562-191b5048664e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370378777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2370378777
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4065239095
Short name T215
Test name
Test status
Simulation time 465847632 ps
CPU time 3.17 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:08 PM PDT 24
Peak memory 198132 kb
Host smart-79fba7dd-cb55-47d3-8f44-3d8f05b5f26e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065239095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4065239095
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2319417376
Short name T668
Test name
Test status
Simulation time 268754951 ps
CPU time 1.1 seconds
Started Mar 17 02:52:05 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 196092 kb
Host smart-d9833b56-100e-41af-8792-a94b15428ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319417376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2319417376
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1556300028
Short name T689
Test name
Test status
Simulation time 25812924 ps
CPU time 0.99 seconds
Started Mar 17 02:52:07 PM PDT 24
Finished Mar 17 02:52:09 PM PDT 24
Peak memory 196812 kb
Host smart-1f8e5283-bb90-400d-ad2e-c6214f064343
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556300028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1556300028
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.447675434
Short name T4
Test name
Test status
Simulation time 1171691010 ps
CPU time 3.55 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:11 PM PDT 24
Peak memory 197892 kb
Host smart-75cd93d0-4be2-46ee-9a40-ee23ae37b431
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447675434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.447675434
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2070033910
Short name T697
Test name
Test status
Simulation time 75932665 ps
CPU time 1.24 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 196484 kb
Host smart-0d32fa91-4b64-4567-932b-4d581bd2ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070033910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2070033910
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.835755375
Short name T614
Test name
Test status
Simulation time 446829374 ps
CPU time 1.42 seconds
Started Mar 17 02:52:04 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 196728 kb
Host smart-5cc715a2-8b2d-4b29-8779-41c0d5268456
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835755375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.835755375
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2408873318
Short name T481
Test name
Test status
Simulation time 11730367631 ps
CPU time 145.29 seconds
Started Mar 17 02:52:02 PM PDT 24
Finished Mar 17 02:54:28 PM PDT 24
Peak memory 198140 kb
Host smart-18dd34a7-3a4c-4c39-923b-2d3217b17b4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408873318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2408873318
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2644620053
Short name T260
Test name
Test status
Simulation time 15154068 ps
CPU time 0.57 seconds
Started Mar 17 02:52:10 PM PDT 24
Finished Mar 17 02:52:11 PM PDT 24
Peak memory 193904 kb
Host smart-3024ee94-d474-4620-84f8-45f3b1fa0966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644620053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2644620053
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1615355007
Short name T635
Test name
Test status
Simulation time 53597868 ps
CPU time 0.74 seconds
Started Mar 17 02:52:09 PM PDT 24
Finished Mar 17 02:52:10 PM PDT 24
Peak memory 194152 kb
Host smart-9eba53bc-cfff-4935-9ba3-8877ce6e45e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615355007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1615355007
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3503140962
Short name T156
Test name
Test status
Simulation time 4129833793 ps
CPU time 17 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:25 PM PDT 24
Peak memory 196916 kb
Host smart-e9a5956a-0fd0-42df-b5f2-e9122d2eeacd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503140962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3503140962
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3787207825
Short name T639
Test name
Test status
Simulation time 31330105 ps
CPU time 0.69 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:09 PM PDT 24
Peak memory 195220 kb
Host smart-44f2c569-fc6e-4f3a-941e-bfdb089d17f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787207825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3787207825
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.31599582
Short name T405
Test name
Test status
Simulation time 296880358 ps
CPU time 1.14 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:10 PM PDT 24
Peak memory 196728 kb
Host smart-ac39ddbc-7c04-4b5b-9f49-fd187ac587c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31599582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.31599582
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1912422857
Short name T233
Test name
Test status
Simulation time 58992591 ps
CPU time 2.43 seconds
Started Mar 17 02:52:10 PM PDT 24
Finished Mar 17 02:52:12 PM PDT 24
Peak memory 198104 kb
Host smart-52cd8169-f2e4-45d4-babb-5d67fd335c55
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912422857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1912422857
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1897121802
Short name T240
Test name
Test status
Simulation time 804990636 ps
CPU time 1.66 seconds
Started Mar 17 02:52:07 PM PDT 24
Finished Mar 17 02:52:09 PM PDT 24
Peak memory 196796 kb
Host smart-4e5e7423-ec53-4dce-8309-5e398c2289e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897121802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1897121802
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2771194592
Short name T325
Test name
Test status
Simulation time 57587487 ps
CPU time 1.31 seconds
Started Mar 17 02:52:03 PM PDT 24
Finished Mar 17 02:52:05 PM PDT 24
Peak memory 196992 kb
Host smart-6398789a-51a2-47d8-92f6-049921150e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771194592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2771194592
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3750100464
Short name T705
Test name
Test status
Simulation time 34958592 ps
CPU time 1.33 seconds
Started Mar 17 02:52:01 PM PDT 24
Finished Mar 17 02:52:02 PM PDT 24
Peak memory 197072 kb
Host smart-2db187d5-d114-443e-86e5-c6cb79fde3f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750100464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3750100464
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3569212733
Short name T572
Test name
Test status
Simulation time 1438467984 ps
CPU time 5.89 seconds
Started Mar 17 02:52:05 PM PDT 24
Finished Mar 17 02:52:11 PM PDT 24
Peak memory 197952 kb
Host smart-d144a35e-bf31-43f3-b7a9-40687bca3ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569212733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3569212733
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.891439823
Short name T165
Test name
Test status
Simulation time 33138384 ps
CPU time 0.81 seconds
Started Mar 17 02:52:09 PM PDT 24
Finished Mar 17 02:52:10 PM PDT 24
Peak memory 196148 kb
Host smart-23fd732a-ff10-416f-be72-7d6ccc6ffcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891439823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.891439823
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2592036453
Short name T601
Test name
Test status
Simulation time 376778346 ps
CPU time 1.32 seconds
Started Mar 17 02:52:12 PM PDT 24
Finished Mar 17 02:52:13 PM PDT 24
Peak memory 196904 kb
Host smart-bf141881-bc5f-4268-b2a9-468ea020724a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592036453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2592036453
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3460632989
Short name T3
Test name
Test status
Simulation time 16660992869 ps
CPU time 46.17 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 198148 kb
Host smart-2ce6d7f3-08a8-4ae5-ac50-9d8787d9cdaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460632989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3460632989
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2538142905
Short name T673
Test name
Test status
Simulation time 15113865 ps
CPU time 0.61 seconds
Started Mar 17 02:51:20 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 194208 kb
Host smart-01ef2838-7d9e-4137-9075-00780b558b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538142905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2538142905
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.4009428409
Short name T622
Test name
Test status
Simulation time 134909117 ps
CPU time 0.87 seconds
Started Mar 17 02:51:18 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 197036 kb
Host smart-b04253c2-983d-4269-a9fc-28a903144677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009428409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.4009428409
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3799277620
Short name T704
Test name
Test status
Simulation time 3867681294 ps
CPU time 25.55 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:48 PM PDT 24
Peak memory 198116 kb
Host smart-15515d7c-b191-4c65-b899-acb80edf2d81
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799277620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3799277620
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2487580193
Short name T169
Test name
Test status
Simulation time 61397045 ps
CPU time 0.96 seconds
Started Mar 17 02:51:20 PM PDT 24
Finished Mar 17 02:51:21 PM PDT 24
Peak memory 196392 kb
Host smart-bce489a9-5ba6-4a2b-a631-84ac875a99c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487580193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2487580193
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.749095434
Short name T318
Test name
Test status
Simulation time 28146747 ps
CPU time 0.66 seconds
Started Mar 17 02:51:18 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 194352 kb
Host smart-601add31-146a-4022-850b-9e4b928d647c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749095434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.749095434
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4218921498
Short name T690
Test name
Test status
Simulation time 350359292 ps
CPU time 3.28 seconds
Started Mar 17 02:51:18 PM PDT 24
Finished Mar 17 02:51:21 PM PDT 24
Peak memory 196464 kb
Host smart-18e68fc5-9bec-48f0-8ded-f88c0f18c72c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218921498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4218921498
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1237356282
Short name T175
Test name
Test status
Simulation time 295313487 ps
CPU time 1.86 seconds
Started Mar 17 02:51:19 PM PDT 24
Finished Mar 17 02:51:21 PM PDT 24
Peak memory 196820 kb
Host smart-69291b88-7300-4849-b0a3-fca983b12e4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237356282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1237356282
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3346112122
Short name T512
Test name
Test status
Simulation time 40404834 ps
CPU time 0.99 seconds
Started Mar 17 02:51:20 PM PDT 24
Finished Mar 17 02:51:21 PM PDT 24
Peak memory 195796 kb
Host smart-be89a07e-efef-4086-9dda-e871b02bec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346112122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3346112122
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3852495519
Short name T576
Test name
Test status
Simulation time 221366188 ps
CPU time 1.38 seconds
Started Mar 17 02:51:19 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 196580 kb
Host smart-e2426adb-58a0-414e-961e-e1c44bc5fa0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852495519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3852495519
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3343827191
Short name T254
Test name
Test status
Simulation time 348406536 ps
CPU time 5.39 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:28 PM PDT 24
Peak memory 198220 kb
Host smart-290bab12-2c83-483c-94ca-a6ba17da4040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343827191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3343827191
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3042076500
Short name T41
Test name
Test status
Simulation time 120979171 ps
CPU time 0.79 seconds
Started Mar 17 02:51:19 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 213768 kb
Host smart-74a3fa90-0998-4a49-9075-e8da2062c85e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042076500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3042076500
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.357667778
Short name T562
Test name
Test status
Simulation time 145093142 ps
CPU time 1.44 seconds
Started Mar 17 02:51:11 PM PDT 24
Finished Mar 17 02:51:13 PM PDT 24
Peak memory 197972 kb
Host smart-83795e5a-5093-40b5-a956-fe3b06bc21fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357667778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.357667778
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3294533875
Short name T658
Test name
Test status
Simulation time 85690052 ps
CPU time 1.37 seconds
Started Mar 17 02:51:15 PM PDT 24
Finished Mar 17 02:51:16 PM PDT 24
Peak memory 198004 kb
Host smart-78c21b9e-1281-4fe1-b9b4-b3e8a6a6ebd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294533875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3294533875
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2377274860
Short name T368
Test name
Test status
Simulation time 3846415284 ps
CPU time 90.35 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:52:52 PM PDT 24
Peak memory 198152 kb
Host smart-836b30ad-e22f-4937-84f0-8f77664270d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377274860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2377274860
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2915813612
Short name T253
Test name
Test status
Simulation time 14193616 ps
CPU time 0.56 seconds
Started Mar 17 02:52:10 PM PDT 24
Finished Mar 17 02:52:11 PM PDT 24
Peak memory 194592 kb
Host smart-86f62d89-0875-459b-9a1f-18cd7f681de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915813612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2915813612
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.4070876
Short name T458
Test name
Test status
Simulation time 21244723 ps
CPU time 0.79 seconds
Started Mar 17 02:52:07 PM PDT 24
Finished Mar 17 02:52:08 PM PDT 24
Peak memory 196044 kb
Host smart-4def6c48-bd6f-4e0a-9859-0b9f84050e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.4070876
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1799157759
Short name T122
Test name
Test status
Simulation time 1587310732 ps
CPU time 25.73 seconds
Started Mar 17 02:52:13 PM PDT 24
Finished Mar 17 02:52:39 PM PDT 24
Peak memory 198144 kb
Host smart-58d7c7ee-1a8e-4c02-a78c-05947300305e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799157759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1799157759
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.583734569
Short name T257
Test name
Test status
Simulation time 344898995 ps
CPU time 1.07 seconds
Started Mar 17 02:52:15 PM PDT 24
Finished Mar 17 02:52:16 PM PDT 24
Peak memory 196620 kb
Host smart-e70aac60-541c-42de-869e-aa367ebe9da7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583734569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.583734569
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2807650772
Short name T196
Test name
Test status
Simulation time 38964790 ps
CPU time 0.97 seconds
Started Mar 17 02:52:06 PM PDT 24
Finished Mar 17 02:52:07 PM PDT 24
Peak memory 196128 kb
Host smart-b7fb7ec9-cd41-4007-b578-98f2a17e71f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807650772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2807650772
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1794716992
Short name T202
Test name
Test status
Simulation time 223197263 ps
CPU time 2.37 seconds
Started Mar 17 02:52:13 PM PDT 24
Finished Mar 17 02:52:15 PM PDT 24
Peak memory 198052 kb
Host smart-4f2bd037-81e0-4c30-917d-37e4063b35d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794716992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1794716992
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.563075053
Short name T376
Test name
Test status
Simulation time 73213691 ps
CPU time 2.24 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:11 PM PDT 24
Peak memory 196788 kb
Host smart-cca395ac-a962-4b5d-82f6-8a641f3ca01c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563075053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
563075053
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3778923134
Short name T180
Test name
Test status
Simulation time 41819835 ps
CPU time 0.67 seconds
Started Mar 17 02:52:09 PM PDT 24
Finished Mar 17 02:52:10 PM PDT 24
Peak memory 194312 kb
Host smart-b167961e-1381-4dbd-aa9b-69868b5db255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778923134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3778923134
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1233930782
Short name T713
Test name
Test status
Simulation time 47611576 ps
CPU time 1 seconds
Started Mar 17 02:52:07 PM PDT 24
Finished Mar 17 02:52:09 PM PDT 24
Peak memory 196744 kb
Host smart-6d48f9fd-5604-4520-9f8e-04cda69b0205
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233930782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1233930782
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1519339182
Short name T259
Test name
Test status
Simulation time 482428184 ps
CPU time 4 seconds
Started Mar 17 02:52:12 PM PDT 24
Finished Mar 17 02:52:17 PM PDT 24
Peak memory 198024 kb
Host smart-37b92643-dcf6-4d57-9696-2aa06c9f5f2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519339182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1519339182
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3314898964
Short name T244
Test name
Test status
Simulation time 91609865 ps
CPU time 1.52 seconds
Started Mar 17 02:52:08 PM PDT 24
Finished Mar 17 02:52:10 PM PDT 24
Peak memory 196644 kb
Host smart-a1331aec-2bcd-43e2-aaeb-384c10f33089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314898964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3314898964
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3830398279
Short name T636
Test name
Test status
Simulation time 168463343 ps
CPU time 1.01 seconds
Started Mar 17 02:52:09 PM PDT 24
Finished Mar 17 02:52:10 PM PDT 24
Peak memory 195524 kb
Host smart-fe2d287f-f8a7-4efc-aecf-3aff225c134b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830398279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3830398279
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3338928250
Short name T509
Test name
Test status
Simulation time 6413548073 ps
CPU time 89.13 seconds
Started Mar 17 02:52:25 PM PDT 24
Finished Mar 17 02:53:55 PM PDT 24
Peak memory 198200 kb
Host smart-2702fa99-90b5-41fa-a38a-c51e73b3ccf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338928250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3338928250
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2542453700
Short name T61
Test name
Test status
Simulation time 133618594470 ps
CPU time 2097.76 seconds
Started Mar 17 02:52:24 PM PDT 24
Finished Mar 17 03:27:23 PM PDT 24
Peak memory 198200 kb
Host smart-4937bf0d-d609-4dd5-9b13-746fc7aa124e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2542453700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2542453700
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3312531190
Short name T696
Test name
Test status
Simulation time 55879036 ps
CPU time 0.61 seconds
Started Mar 17 02:52:17 PM PDT 24
Finished Mar 17 02:52:19 PM PDT 24
Peak memory 193932 kb
Host smart-0efcbe0a-2f7e-4a8f-847c-599dd52279a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312531190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3312531190
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2502204939
Short name T266
Test name
Test status
Simulation time 186819847 ps
CPU time 0.8 seconds
Started Mar 17 02:52:11 PM PDT 24
Finished Mar 17 02:52:12 PM PDT 24
Peak memory 195984 kb
Host smart-5591df11-134b-4688-bc87-44fed1745785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502204939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2502204939
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.314992543
Short name T74
Test name
Test status
Simulation time 471521703 ps
CPU time 6.5 seconds
Started Mar 17 02:52:13 PM PDT 24
Finished Mar 17 02:52:20 PM PDT 24
Peak memory 196432 kb
Host smart-ea5cd840-4a30-4e6c-ae6c-26ff354e5d5b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314992543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.314992543
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.4133398576
Short name T298
Test name
Test status
Simulation time 139091865 ps
CPU time 0.84 seconds
Started Mar 17 02:52:28 PM PDT 24
Finished Mar 17 02:52:29 PM PDT 24
Peak memory 195916 kb
Host smart-7f8a0c35-c393-4a8e-919d-1a77c8783475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133398576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.4133398576
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4016130623
Short name T157
Test name
Test status
Simulation time 189741932 ps
CPU time 1.38 seconds
Started Mar 17 02:52:12 PM PDT 24
Finished Mar 17 02:52:14 PM PDT 24
Peak memory 197036 kb
Host smart-79a9d4ff-92f1-4f5b-bc3e-1e8f98bd1b8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016130623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4016130623
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.335397378
Short name T218
Test name
Test status
Simulation time 80791451 ps
CPU time 3.28 seconds
Started Mar 17 02:52:13 PM PDT 24
Finished Mar 17 02:52:16 PM PDT 24
Peak memory 198096 kb
Host smart-9f405257-ffe2-4684-8cfd-487ad86bfb96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335397378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.335397378
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2861583868
Short name T381
Test name
Test status
Simulation time 284467131 ps
CPU time 1.8 seconds
Started Mar 17 02:52:12 PM PDT 24
Finished Mar 17 02:52:14 PM PDT 24
Peak memory 195796 kb
Host smart-f4636c79-ff7e-45e3-a91b-43cfccfc2023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861583868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2861583868
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1861366211
Short name T360
Test name
Test status
Simulation time 17515802 ps
CPU time 0.68 seconds
Started Mar 17 02:52:10 PM PDT 24
Finished Mar 17 02:52:11 PM PDT 24
Peak memory 194304 kb
Host smart-8282bf42-f597-4cb2-9a02-337bf932ca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861366211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1861366211
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1155835364
Short name T474
Test name
Test status
Simulation time 110636454 ps
CPU time 0.8 seconds
Started Mar 17 02:52:12 PM PDT 24
Finished Mar 17 02:52:13 PM PDT 24
Peak memory 196480 kb
Host smart-61a3a184-d9ed-407f-9176-11052ea8341b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155835364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1155835364
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3058058331
Short name T403
Test name
Test status
Simulation time 1128046690 ps
CPU time 4.84 seconds
Started Mar 17 02:52:19 PM PDT 24
Finished Mar 17 02:52:25 PM PDT 24
Peak memory 197920 kb
Host smart-9be70fe0-ada2-46af-b0a3-fb3dbbaf8583
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058058331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3058058331
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.4190449351
Short name T284
Test name
Test status
Simulation time 102614519 ps
CPU time 1.37 seconds
Started Mar 17 02:52:13 PM PDT 24
Finished Mar 17 02:52:15 PM PDT 24
Peak memory 196220 kb
Host smart-31049e1b-dc62-4641-a820-74240e9daa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190449351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.4190449351
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1966734033
Short name T167
Test name
Test status
Simulation time 42016088 ps
CPU time 1.23 seconds
Started Mar 17 02:52:14 PM PDT 24
Finished Mar 17 02:52:15 PM PDT 24
Peak memory 196584 kb
Host smart-ef2a7c6f-2d18-4ab5-9ae9-1b4aae1c9574
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966734033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1966734033
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2274710231
Short name T300
Test name
Test status
Simulation time 34101123210 ps
CPU time 110.43 seconds
Started Mar 17 02:52:32 PM PDT 24
Finished Mar 17 02:54:23 PM PDT 24
Peak memory 198184 kb
Host smart-7b582075-9f53-4bcd-af6f-5f4940c96a59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274710231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2274710231
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1626568475
Short name T211
Test name
Test status
Simulation time 40224306 ps
CPU time 0.59 seconds
Started Mar 17 02:52:33 PM PDT 24
Finished Mar 17 02:52:34 PM PDT 24
Peak memory 194084 kb
Host smart-fdb79a63-bcce-4f3a-b662-adb2d9dc1fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626568475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1626568475
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.980275947
Short name T281
Test name
Test status
Simulation time 55904492 ps
CPU time 0.87 seconds
Started Mar 17 02:52:17 PM PDT 24
Finished Mar 17 02:52:19 PM PDT 24
Peak memory 195472 kb
Host smart-b998af7f-57db-467d-966b-10ff01dfa1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980275947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.980275947
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2055539506
Short name T470
Test name
Test status
Simulation time 380670413 ps
CPU time 5.94 seconds
Started Mar 17 02:52:39 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 196968 kb
Host smart-9bb8eb42-3bd2-4844-ad96-367c8de4aca3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055539506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2055539506
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2765574445
Short name T229
Test name
Test status
Simulation time 637238097 ps
CPU time 1 seconds
Started Mar 17 02:52:30 PM PDT 24
Finished Mar 17 02:52:31 PM PDT 24
Peak memory 196576 kb
Host smart-88faf39d-c7cc-4f2a-b39b-08282dde95fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765574445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2765574445
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.938276291
Short name T58
Test name
Test status
Simulation time 111813148 ps
CPU time 0.99 seconds
Started Mar 17 02:52:17 PM PDT 24
Finished Mar 17 02:52:19 PM PDT 24
Peak memory 196620 kb
Host smart-b4617efe-9435-44fe-901b-b03e1ab3640a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938276291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.938276291
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.88825254
Short name T296
Test name
Test status
Simulation time 313821381 ps
CPU time 3.37 seconds
Started Mar 17 02:52:18 PM PDT 24
Finished Mar 17 02:52:22 PM PDT 24
Peak memory 198068 kb
Host smart-8623a274-f0c7-468a-b0e3-f9b75d5a69cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88825254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.gpio_intr_with_filter_rand_intr_event.88825254
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1456495615
Short name T125
Test name
Test status
Simulation time 58415778 ps
CPU time 1.35 seconds
Started Mar 17 02:52:17 PM PDT 24
Finished Mar 17 02:52:18 PM PDT 24
Peak memory 196500 kb
Host smart-923af56c-7f7c-47e5-9bdf-22bfe681bf56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456495615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1456495615
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.265843816
Short name T478
Test name
Test status
Simulation time 111397161 ps
CPU time 1.25 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 197968 kb
Host smart-690ddd63-688a-4e1f-a229-86c69b75805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265843816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.265843816
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3377265320
Short name T136
Test name
Test status
Simulation time 152088227 ps
CPU time 0.88 seconds
Started Mar 17 02:52:16 PM PDT 24
Finished Mar 17 02:52:16 PM PDT 24
Peak memory 195952 kb
Host smart-d813a2b7-5436-4ef4-a614-42db73207f3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377265320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3377265320
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4075246552
Short name T172
Test name
Test status
Simulation time 142368953 ps
CPU time 2.59 seconds
Started Mar 17 02:52:34 PM PDT 24
Finished Mar 17 02:52:37 PM PDT 24
Peak memory 198012 kb
Host smart-785d514c-b423-4b37-bdf1-dbde5539e801
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075246552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.4075246552
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.346805957
Short name T675
Test name
Test status
Simulation time 99486901 ps
CPU time 1.12 seconds
Started Mar 17 02:52:36 PM PDT 24
Finished Mar 17 02:52:38 PM PDT 24
Peak memory 195532 kb
Host smart-988fac30-393e-4794-bb87-756afa363b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346805957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.346805957
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2977351549
Short name T183
Test name
Test status
Simulation time 47521346 ps
CPU time 1.06 seconds
Started Mar 17 02:52:32 PM PDT 24
Finished Mar 17 02:52:33 PM PDT 24
Peak memory 195728 kb
Host smart-c72a7e0d-b089-47aa-8b5b-4eae4560674a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977351549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2977351549
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.596740458
Short name T443
Test name
Test status
Simulation time 9896154618 ps
CPU time 146.28 seconds
Started Mar 17 02:52:22 PM PDT 24
Finished Mar 17 02:54:49 PM PDT 24
Peak memory 198236 kb
Host smart-2585f5ba-70d1-4501-82e8-9209fe9f7c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596740458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.596740458
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.48966338
Short name T207
Test name
Test status
Simulation time 24644168 ps
CPU time 0.58 seconds
Started Mar 17 02:52:23 PM PDT 24
Finished Mar 17 02:52:24 PM PDT 24
Peak memory 194116 kb
Host smart-07233f02-449a-4743-a9ce-5e9d3e3572db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48966338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.48966338
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.226910301
Short name T331
Test name
Test status
Simulation time 102457003 ps
CPU time 0.73 seconds
Started Mar 17 02:52:32 PM PDT 24
Finished Mar 17 02:52:33 PM PDT 24
Peak memory 196124 kb
Host smart-6aebed0a-626b-4186-8a64-b495242032d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226910301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.226910301
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2050128215
Short name T423
Test name
Test status
Simulation time 2290466163 ps
CPU time 21.04 seconds
Started Mar 17 02:52:34 PM PDT 24
Finished Mar 17 02:52:56 PM PDT 24
Peak memory 197008 kb
Host smart-0f4fdaf7-6db3-4efa-8026-1c79d685a27f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050128215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2050128215
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1459419323
Short name T8
Test name
Test status
Simulation time 73833395 ps
CPU time 1.02 seconds
Started Mar 17 02:52:39 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 197960 kb
Host smart-da1550d8-5437-4c89-ada9-f53e89fe6b3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459419323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1459419323
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3337973609
Short name T153
Test name
Test status
Simulation time 19105064 ps
CPU time 0.78 seconds
Started Mar 17 02:52:41 PM PDT 24
Finished Mar 17 02:52:42 PM PDT 24
Peak memory 196236 kb
Host smart-6deee727-6ccb-46c3-a6ca-769482f27271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337973609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3337973609
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.4231089471
Short name T666
Test name
Test status
Simulation time 70657422 ps
CPU time 2.66 seconds
Started Mar 17 02:52:45 PM PDT 24
Finished Mar 17 02:52:48 PM PDT 24
Peak memory 198052 kb
Host smart-2afd90dd-2c53-4ee6-a23b-3fb07eb4b8d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231089471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.4231089471
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2660669336
Short name T314
Test name
Test status
Simulation time 108361859 ps
CPU time 1.08 seconds
Started Mar 17 02:52:23 PM PDT 24
Finished Mar 17 02:52:25 PM PDT 24
Peak memory 196000 kb
Host smart-d9b9c0ee-118c-4e46-9970-ce75c0b20dd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660669336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2660669336
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3007408405
Short name T223
Test name
Test status
Simulation time 69987869 ps
CPU time 0.73 seconds
Started Mar 17 02:52:33 PM PDT 24
Finished Mar 17 02:52:34 PM PDT 24
Peak memory 194376 kb
Host smart-47cb6b63-8165-46ca-a8c8-05af474071fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007408405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3007408405
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4117205707
Short name T587
Test name
Test status
Simulation time 152760540 ps
CPU time 1.1 seconds
Started Mar 17 02:52:21 PM PDT 24
Finished Mar 17 02:52:23 PM PDT 24
Peak memory 196048 kb
Host smart-f94f15e2-3f81-47c2-8c42-74957bb61694
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117205707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4117205707
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.284331619
Short name T332
Test name
Test status
Simulation time 918763635 ps
CPU time 3.42 seconds
Started Mar 17 02:52:35 PM PDT 24
Finished Mar 17 02:52:38 PM PDT 24
Peak memory 197920 kb
Host smart-1f8d66cb-f834-47c2-b7e9-590508f8e798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284331619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.284331619
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.422631333
Short name T160
Test name
Test status
Simulation time 197307585 ps
CPU time 1.11 seconds
Started Mar 17 02:52:17 PM PDT 24
Finished Mar 17 02:52:19 PM PDT 24
Peak memory 196508 kb
Host smart-9a32a049-a3c9-47c7-982b-e1ee7d03315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422631333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.422631333
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1048647266
Short name T25
Test name
Test status
Simulation time 68391159 ps
CPU time 1.35 seconds
Started Mar 17 02:52:16 PM PDT 24
Finished Mar 17 02:52:18 PM PDT 24
Peak memory 196688 kb
Host smart-8158f206-1c08-41d7-a888-9c8f52647957
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048647266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1048647266
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1811077047
Short name T598
Test name
Test status
Simulation time 6709843111 ps
CPU time 176.32 seconds
Started Mar 17 02:52:21 PM PDT 24
Finished Mar 17 02:55:18 PM PDT 24
Peak memory 198108 kb
Host smart-902e4b6a-3db2-48ac-8da7-09e46bf347b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811077047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1811077047
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.712736995
Short name T346
Test name
Test status
Simulation time 14073607 ps
CPU time 0.55 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 193948 kb
Host smart-cb42ce57-e4cf-424b-a3bd-be6d786f9a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712736995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.712736995
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.759505720
Short name T538
Test name
Test status
Simulation time 116534650 ps
CPU time 0.66 seconds
Started Mar 17 02:52:21 PM PDT 24
Finished Mar 17 02:52:23 PM PDT 24
Peak memory 194112 kb
Host smart-0fd995bd-0012-403c-b3e3-908ded0daaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759505720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.759505720
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.280226579
Short name T491
Test name
Test status
Simulation time 1190560290 ps
CPU time 9.67 seconds
Started Mar 17 02:52:35 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 197976 kb
Host smart-ea18242e-ea48-4839-aaba-536e8fef66f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280226579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.280226579
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2913805098
Short name T238
Test name
Test status
Simulation time 815020620 ps
CPU time 1.04 seconds
Started Mar 17 02:52:43 PM PDT 24
Finished Mar 17 02:52:44 PM PDT 24
Peak memory 197284 kb
Host smart-36cb742e-12ce-42c9-8ceb-7d664f8cc6da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913805098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2913805098
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3670282312
Short name T431
Test name
Test status
Simulation time 106561883 ps
CPU time 1.06 seconds
Started Mar 17 02:52:22 PM PDT 24
Finished Mar 17 02:52:24 PM PDT 24
Peak memory 195916 kb
Host smart-9e4827d1-7c37-4b2a-812c-2ce97556fb82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670282312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3670282312
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1905701002
Short name T427
Test name
Test status
Simulation time 30088010 ps
CPU time 1.22 seconds
Started Mar 17 02:52:21 PM PDT 24
Finished Mar 17 02:52:23 PM PDT 24
Peak memory 196528 kb
Host smart-492fbf02-0e70-4044-ba12-d8d605c0b0ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905701002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1905701002
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3759971477
Short name T570
Test name
Test status
Simulation time 256582895 ps
CPU time 1.88 seconds
Started Mar 17 02:52:22 PM PDT 24
Finished Mar 17 02:52:25 PM PDT 24
Peak memory 197272 kb
Host smart-2a52b6a0-9fc6-4adf-9cc8-6ddb26cce599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759971477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3759971477
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.170628348
Short name T384
Test name
Test status
Simulation time 62713061 ps
CPU time 1.05 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 195668 kb
Host smart-58ef5520-9898-4831-9c8b-ec118c3102d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170628348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.170628348
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3736613313
Short name T217
Test name
Test status
Simulation time 19774957 ps
CPU time 0.66 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 194060 kb
Host smart-0f4a31e3-8afd-46a8-b4a4-48365735f033
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736613313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3736613313
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1360197307
Short name T591
Test name
Test status
Simulation time 354395057 ps
CPU time 1.41 seconds
Started Mar 17 02:52:25 PM PDT 24
Finished Mar 17 02:52:27 PM PDT 24
Peak memory 197848 kb
Host smart-5e63157a-18a0-4db4-95c5-0b97078c7d2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360197307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1360197307
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.4092176444
Short name T307
Test name
Test status
Simulation time 24795179 ps
CPU time 0.84 seconds
Started Mar 17 02:52:24 PM PDT 24
Finished Mar 17 02:52:25 PM PDT 24
Peak memory 195340 kb
Host smart-971053a2-3fc7-4319-b492-8fec44f997f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092176444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.4092176444
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.452708864
Short name T554
Test name
Test status
Simulation time 44005128 ps
CPU time 1.05 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 195576 kb
Host smart-c1af8122-d977-4667-8af6-320e4c1dc779
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452708864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.452708864
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2953034889
Short name T555
Test name
Test status
Simulation time 13164660446 ps
CPU time 144.48 seconds
Started Mar 17 02:52:25 PM PDT 24
Finished Mar 17 02:54:50 PM PDT 24
Peak memory 198136 kb
Host smart-b7438c64-4537-4849-b2e8-aa98a31ef7e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953034889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2953034889
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1038321446
Short name T351
Test name
Test status
Simulation time 40678545 ps
CPU time 0.6 seconds
Started Mar 17 02:52:30 PM PDT 24
Finished Mar 17 02:52:31 PM PDT 24
Peak memory 195004 kb
Host smart-b5dda85f-03af-4efb-9e97-60f0bdf1caa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038321446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1038321446
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.4212081281
Short name T252
Test name
Test status
Simulation time 142034717 ps
CPU time 0.85 seconds
Started Mar 17 02:52:46 PM PDT 24
Finished Mar 17 02:52:47 PM PDT 24
Peak memory 196244 kb
Host smart-22c34451-4c1d-41b6-9e03-5606b9f2b5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212081281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.4212081281
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3197955765
Short name T158
Test name
Test status
Simulation time 738577004 ps
CPU time 11.48 seconds
Started Mar 17 02:52:26 PM PDT 24
Finished Mar 17 02:52:38 PM PDT 24
Peak memory 196316 kb
Host smart-142c4b58-bb51-4142-a720-66143b94384c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197955765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3197955765
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2430356888
Short name T213
Test name
Test status
Simulation time 53049888 ps
CPU time 0.9 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 197152 kb
Host smart-4e762895-671a-4f66-a5a0-11621d27eaec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430356888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2430356888
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.454332198
Short name T150
Test name
Test status
Simulation time 114913591 ps
CPU time 1.46 seconds
Started Mar 17 02:52:41 PM PDT 24
Finished Mar 17 02:52:42 PM PDT 24
Peak memory 197092 kb
Host smart-a5224a68-64d6-4bf1-a1c0-243a1fe6ef54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454332198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.454332198
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.625930561
Short name T107
Test name
Test status
Simulation time 33606632 ps
CPU time 1.47 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:52:57 PM PDT 24
Peak memory 196748 kb
Host smart-fc74e169-cbdb-4e57-afef-1346fe1c8d7e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625930561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.625930561
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2470746199
Short name T487
Test name
Test status
Simulation time 71918987 ps
CPU time 1.59 seconds
Started Mar 17 02:52:27 PM PDT 24
Finished Mar 17 02:52:29 PM PDT 24
Peak memory 196088 kb
Host smart-4422b69d-2943-4677-8763-cc44e5edcf86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470746199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2470746199
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2960075243
Short name T113
Test name
Test status
Simulation time 53400889 ps
CPU time 1.16 seconds
Started Mar 17 02:52:26 PM PDT 24
Finished Mar 17 02:52:27 PM PDT 24
Peak memory 196780 kb
Host smart-49427270-3041-4300-a123-c9001df65e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960075243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2960075243
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2778113732
Short name T653
Test name
Test status
Simulation time 37760704 ps
CPU time 0.9 seconds
Started Mar 17 02:52:26 PM PDT 24
Finished Mar 17 02:52:27 PM PDT 24
Peak memory 196536 kb
Host smart-d546896c-f4ca-474d-b903-1fbac0117070
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778113732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2778113732
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3014303355
Short name T60
Test name
Test status
Simulation time 93931305 ps
CPU time 2.19 seconds
Started Mar 17 02:52:27 PM PDT 24
Finished Mar 17 02:52:30 PM PDT 24
Peak memory 197964 kb
Host smart-d63b6cc6-0ff3-4da3-ae93-ca617d195208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014303355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3014303355
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1808728602
Short name T451
Test name
Test status
Simulation time 140535888 ps
CPU time 1.29 seconds
Started Mar 17 02:52:43 PM PDT 24
Finished Mar 17 02:52:44 PM PDT 24
Peak memory 196340 kb
Host smart-5221a48b-1e22-4dc6-9cea-fbe94bbfde1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808728602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1808728602
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2998180433
Short name T615
Test name
Test status
Simulation time 255420740 ps
CPU time 1.26 seconds
Started Mar 17 02:52:41 PM PDT 24
Finished Mar 17 02:52:42 PM PDT 24
Peak memory 195892 kb
Host smart-75f464ae-5174-4933-81ea-7168ce4ab28e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998180433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2998180433
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2618457505
Short name T130
Test name
Test status
Simulation time 1958554563 ps
CPU time 28.82 seconds
Started Mar 17 02:52:43 PM PDT 24
Finished Mar 17 02:53:12 PM PDT 24
Peak memory 198120 kb
Host smart-d9a0de4a-d9f9-431c-97f3-4d317b877e1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618457505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2618457505
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2581150913
Short name T513
Test name
Test status
Simulation time 13766776 ps
CPU time 0.58 seconds
Started Mar 17 02:52:32 PM PDT 24
Finished Mar 17 02:52:33 PM PDT 24
Peak memory 193928 kb
Host smart-1c8a682e-a70c-4235-89ec-35be3adb6ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581150913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2581150913
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3009533191
Short name T418
Test name
Test status
Simulation time 65834078 ps
CPU time 0.78 seconds
Started Mar 17 02:52:48 PM PDT 24
Finished Mar 17 02:52:48 PM PDT 24
Peak memory 194880 kb
Host smart-512c34ad-14a5-49cf-bbf4-339bfdb5a17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009533191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3009533191
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.68448203
Short name T330
Test name
Test status
Simulation time 501446998 ps
CPU time 13.98 seconds
Started Mar 17 02:52:58 PM PDT 24
Finished Mar 17 02:53:12 PM PDT 24
Peak memory 195544 kb
Host smart-eee06204-3c9c-4948-978d-3f610f245fcc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68448203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stress
.68448203
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2099597709
Short name T575
Test name
Test status
Simulation time 34994467 ps
CPU time 0.8 seconds
Started Mar 17 02:52:31 PM PDT 24
Finished Mar 17 02:52:31 PM PDT 24
Peak memory 196596 kb
Host smart-e9c08788-49bd-4835-b889-4e640eb46390
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099597709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2099597709
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1790464781
Short name T406
Test name
Test status
Simulation time 51437027 ps
CPU time 0.77 seconds
Started Mar 17 02:52:48 PM PDT 24
Finished Mar 17 02:52:49 PM PDT 24
Peak memory 194396 kb
Host smart-d3d4afae-3f51-490b-a47e-4acc662966dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790464781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1790464781
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3297369063
Short name T539
Test name
Test status
Simulation time 97907243 ps
CPU time 2.11 seconds
Started Mar 17 02:52:49 PM PDT 24
Finished Mar 17 02:52:51 PM PDT 24
Peak memory 196520 kb
Host smart-3f84f179-b5fd-4029-b2f6-9c2d8240064f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297369063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3297369063
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3749836039
Short name T383
Test name
Test status
Simulation time 442738165 ps
CPU time 2.92 seconds
Started Mar 17 02:52:31 PM PDT 24
Finished Mar 17 02:52:34 PM PDT 24
Peak memory 197240 kb
Host smart-dfcc827b-bfbb-41f1-b2d8-dc40788c4b0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749836039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3749836039
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2354979527
Short name T185
Test name
Test status
Simulation time 116956261 ps
CPU time 1.32 seconds
Started Mar 17 02:52:35 PM PDT 24
Finished Mar 17 02:52:37 PM PDT 24
Peak memory 196520 kb
Host smart-19333666-0cef-4534-9418-2796f46ff317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354979527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2354979527
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1406570377
Short name T626
Test name
Test status
Simulation time 48599271 ps
CPU time 1 seconds
Started Mar 17 02:52:48 PM PDT 24
Finished Mar 17 02:52:49 PM PDT 24
Peak memory 196684 kb
Host smart-9be6707d-211c-46bb-84a6-05287084348c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406570377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1406570377
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1963076017
Short name T661
Test name
Test status
Simulation time 171728502 ps
CPU time 3.05 seconds
Started Mar 17 02:52:34 PM PDT 24
Finished Mar 17 02:52:37 PM PDT 24
Peak memory 197612 kb
Host smart-df3b664a-a89d-4bbf-bd38-35070390cc0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963076017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1963076017
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3953523936
Short name T677
Test name
Test status
Simulation time 71365581 ps
CPU time 0.95 seconds
Started Mar 17 02:52:28 PM PDT 24
Finished Mar 17 02:52:29 PM PDT 24
Peak memory 196452 kb
Host smart-c50c0e73-102f-44e1-90be-da080fc4b99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953523936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3953523936
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2933274608
Short name T358
Test name
Test status
Simulation time 59008150 ps
CPU time 0.93 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 195512 kb
Host smart-3920b0be-847b-4916-9c95-d983d775c35f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933274608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2933274608
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2595119488
Short name T543
Test name
Test status
Simulation time 17062377317 ps
CPU time 123.8 seconds
Started Mar 17 02:52:49 PM PDT 24
Finished Mar 17 02:54:53 PM PDT 24
Peak memory 198192 kb
Host smart-e4d2e470-9f14-4851-a7a9-fc6a82ee5414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595119488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2595119488
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3970297036
Short name T559
Test name
Test status
Simulation time 54497424119 ps
CPU time 867.01 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 03:07:18 PM PDT 24
Peak memory 198256 kb
Host smart-6e1bc8b0-d8d9-48c2-a963-35391e598d8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3970297036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3970297036
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4162957610
Short name T652
Test name
Test status
Simulation time 111586343 ps
CPU time 0.89 seconds
Started Mar 17 02:52:46 PM PDT 24
Finished Mar 17 02:52:47 PM PDT 24
Peak memory 197400 kb
Host smart-1584a508-18e3-4d33-a660-ee477ddbd95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162957610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4162957610
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3260298310
Short name T375
Test name
Test status
Simulation time 965940150 ps
CPU time 6.22 seconds
Started Mar 17 02:52:46 PM PDT 24
Finished Mar 17 02:52:52 PM PDT 24
Peak memory 196684 kb
Host smart-cdb39d8b-d7d5-4fc0-822f-03afb03db63c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260298310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3260298310
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3147992262
Short name T162
Test name
Test status
Simulation time 88437986 ps
CPU time 1.08 seconds
Started Mar 17 02:52:32 PM PDT 24
Finished Mar 17 02:52:33 PM PDT 24
Peak memory 196472 kb
Host smart-8c34da6f-3f75-438d-a63b-c8529c186284
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147992262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3147992262
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1542373372
Short name T388
Test name
Test status
Simulation time 170513445 ps
CPU time 1.02 seconds
Started Mar 17 02:52:34 PM PDT 24
Finished Mar 17 02:52:36 PM PDT 24
Peak memory 196688 kb
Host smart-af6ae57c-9414-408c-9c70-9a90fdbe7b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542373372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1542373372
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1686183533
Short name T68
Test name
Test status
Simulation time 149164933 ps
CPU time 1.55 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:52:57 PM PDT 24
Peak memory 198060 kb
Host smart-80311c57-c14c-4aa7-ba73-d014c1ca678c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686183533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1686183533
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3768137055
Short name T237
Test name
Test status
Simulation time 99143628 ps
CPU time 2.19 seconds
Started Mar 17 02:52:45 PM PDT 24
Finished Mar 17 02:52:48 PM PDT 24
Peak memory 196964 kb
Host smart-d32a5b05-b78e-4895-b9de-53b4b4366afd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768137055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3768137055
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2633340241
Short name T328
Test name
Test status
Simulation time 1077418478 ps
CPU time 1.14 seconds
Started Mar 17 02:52:33 PM PDT 24
Finished Mar 17 02:52:34 PM PDT 24
Peak memory 196192 kb
Host smart-ec4d9535-4aa5-4938-9b4e-e790a25caf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633340241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2633340241
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2317123675
Short name T356
Test name
Test status
Simulation time 59559301 ps
CPU time 1.27 seconds
Started Mar 17 02:52:45 PM PDT 24
Finished Mar 17 02:52:46 PM PDT 24
Peak memory 198096 kb
Host smart-d15c4d32-a8e0-43be-8628-e2827d2ea0d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317123675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2317123675
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3296292060
Short name T261
Test name
Test status
Simulation time 1121013889 ps
CPU time 5.45 seconds
Started Mar 17 02:52:30 PM PDT 24
Finished Mar 17 02:52:35 PM PDT 24
Peak memory 197928 kb
Host smart-fbdbf907-653d-451d-97c0-798ee2b274b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296292060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3296292060
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.395185582
Short name T536
Test name
Test status
Simulation time 191020700 ps
CPU time 1.11 seconds
Started Mar 17 02:52:32 PM PDT 24
Finished Mar 17 02:52:33 PM PDT 24
Peak memory 195708 kb
Host smart-3451ae7c-da1b-41cf-b0eb-9aac01039530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395185582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.395185582
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.971121013
Short name T435
Test name
Test status
Simulation time 81755714 ps
CPU time 1.39 seconds
Started Mar 17 02:52:31 PM PDT 24
Finished Mar 17 02:52:32 PM PDT 24
Peak memory 195532 kb
Host smart-4d4bd3e0-27c2-473e-8898-6975edfc423a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971121013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.971121013
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2867526787
Short name T450
Test name
Test status
Simulation time 3124441248 ps
CPU time 83 seconds
Started Mar 17 02:52:50 PM PDT 24
Finished Mar 17 02:54:13 PM PDT 24
Peak memory 198148 kb
Host smart-baaea741-1202-497f-ab39-9e4374aa9e97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867526787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2867526787
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3633788801
Short name T36
Test name
Test status
Simulation time 14806737665 ps
CPU time 237.39 seconds
Started Mar 17 02:52:34 PM PDT 24
Finished Mar 17 02:56:32 PM PDT 24
Peak memory 198236 kb
Host smart-d33d5e2b-37bb-496b-a5dd-42e37a66ba15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3633788801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3633788801
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1006300087
Short name T489
Test name
Test status
Simulation time 14472732 ps
CPU time 0.58 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:52:52 PM PDT 24
Peak memory 194600 kb
Host smart-f3cc9275-d116-40f5-809e-5e432200d602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006300087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1006300087
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3440107982
Short name T190
Test name
Test status
Simulation time 138823181 ps
CPU time 0.87 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 196212 kb
Host smart-b4b9b514-a587-416d-b9d5-099835bfb0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440107982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3440107982
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2380689668
Short name T712
Test name
Test status
Simulation time 1758882828 ps
CPU time 20.01 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:53:11 PM PDT 24
Peak memory 197988 kb
Host smart-e9fcc8a8-c611-4f62-afcd-790425e6ce41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380689668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2380689668
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3364101626
Short name T448
Test name
Test status
Simulation time 119510256 ps
CPU time 1.08 seconds
Started Mar 17 02:52:58 PM PDT 24
Finished Mar 17 02:52:59 PM PDT 24
Peak memory 196280 kb
Host smart-3538a903-d136-4e9b-8c40-13e23ef81958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364101626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3364101626
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1806300180
Short name T347
Test name
Test status
Simulation time 52109689 ps
CPU time 1.46 seconds
Started Mar 17 02:52:43 PM PDT 24
Finished Mar 17 02:52:44 PM PDT 24
Peak memory 197244 kb
Host smart-594fec01-6883-45dd-a8f7-90aab6ec1feb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806300180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1806300180
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.510612563
Short name T385
Test name
Test status
Simulation time 513507502 ps
CPU time 2.7 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:52:54 PM PDT 24
Peak memory 197836 kb
Host smart-dc67f511-cf42-4c85-83ca-e5e06cd42731
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510612563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.510612563
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3858221363
Short name T329
Test name
Test status
Simulation time 58471506 ps
CPU time 1.34 seconds
Started Mar 17 02:52:31 PM PDT 24
Finished Mar 17 02:52:33 PM PDT 24
Peak memory 196892 kb
Host smart-9a6bc1e6-cd87-4492-8e17-f1cffbe09b7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858221363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3858221363
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.822796623
Short name T685
Test name
Test status
Simulation time 205997697 ps
CPU time 1.26 seconds
Started Mar 17 02:52:31 PM PDT 24
Finished Mar 17 02:52:32 PM PDT 24
Peak memory 195816 kb
Host smart-29c0245f-6063-4126-8791-bc195d29f641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822796623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.822796623
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3081437767
Short name T316
Test name
Test status
Simulation time 101149995 ps
CPU time 1.12 seconds
Started Mar 17 02:52:36 PM PDT 24
Finished Mar 17 02:52:37 PM PDT 24
Peak memory 195836 kb
Host smart-1d8d1cd6-3d18-4163-9033-ab274f423bbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081437767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3081437767
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.370987320
Short name T222
Test name
Test status
Simulation time 853617962 ps
CPU time 3.74 seconds
Started Mar 17 02:52:34 PM PDT 24
Finished Mar 17 02:52:38 PM PDT 24
Peak memory 197908 kb
Host smart-5d754c67-2e7d-4375-a9bf-ec6875e3e3b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370987320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.370987320
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.45133334
Short name T574
Test name
Test status
Simulation time 148322804 ps
CPU time 0.91 seconds
Started Mar 17 02:52:29 PM PDT 24
Finished Mar 17 02:52:30 PM PDT 24
Peak memory 195460 kb
Host smart-25450ebd-4bd5-4d97-b90d-09aeb7faf5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45133334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.45133334
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1531390727
Short name T460
Test name
Test status
Simulation time 131184115 ps
CPU time 0.86 seconds
Started Mar 17 02:52:32 PM PDT 24
Finished Mar 17 02:52:33 PM PDT 24
Peak memory 195340 kb
Host smart-558b8885-301d-4459-a6cd-13fc5a962ea3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531390727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1531390727
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1539833872
Short name T465
Test name
Test status
Simulation time 45655438122 ps
CPU time 150.65 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:55:22 PM PDT 24
Peak memory 198140 kb
Host smart-d68ddf35-5a1b-4b67-8c40-df3d304642a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539833872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1539833872
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.61190774
Short name T660
Test name
Test status
Simulation time 34131639 ps
CPU time 0.59 seconds
Started Mar 17 02:52:50 PM PDT 24
Finished Mar 17 02:52:51 PM PDT 24
Peak memory 193836 kb
Host smart-3f270650-28dc-4f21-b06a-706bb245c1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61190774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.61190774
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2071585540
Short name T672
Test name
Test status
Simulation time 32940281 ps
CPU time 0.75 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 194268 kb
Host smart-32049a02-af4e-4f5a-ab9a-5207da2205ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071585540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2071585540
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2658444597
Short name T221
Test name
Test status
Simulation time 306902194 ps
CPU time 5.38 seconds
Started Mar 17 02:52:47 PM PDT 24
Finished Mar 17 02:52:52 PM PDT 24
Peak memory 197168 kb
Host smart-671a3fc8-b3a7-470a-9471-f0d61560cdc5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658444597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2658444597
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1636422388
Short name T611
Test name
Test status
Simulation time 97426473 ps
CPU time 1.18 seconds
Started Mar 17 02:52:30 PM PDT 24
Finished Mar 17 02:52:32 PM PDT 24
Peak memory 197952 kb
Host smart-b9c766ea-78cf-4743-9a03-eb7e025d1b4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636422388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1636422388
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1163305581
Short name T370
Test name
Test status
Simulation time 479097223 ps
CPU time 0.99 seconds
Started Mar 17 02:52:31 PM PDT 24
Finished Mar 17 02:52:32 PM PDT 24
Peak memory 195728 kb
Host smart-b79ba0a3-b976-4ed9-bb72-e6094495fbe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163305581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1163305581
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.4176264271
Short name T532
Test name
Test status
Simulation time 118371425 ps
CPU time 2.55 seconds
Started Mar 17 02:52:33 PM PDT 24
Finished Mar 17 02:52:36 PM PDT 24
Peak memory 196520 kb
Host smart-827b08bf-1196-4fb6-8daa-c0d5e00e8bb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176264271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.4176264271
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3732781551
Short name T410
Test name
Test status
Simulation time 93832084 ps
CPU time 0.99 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 195996 kb
Host smart-68003fec-7d64-4f57-883b-e78700639ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732781551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3732781551
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.4291733090
Short name T426
Test name
Test status
Simulation time 28771971 ps
CPU time 1.03 seconds
Started Mar 17 02:52:33 PM PDT 24
Finished Mar 17 02:52:34 PM PDT 24
Peak memory 196200 kb
Host smart-ab82b27f-aa88-4a76-b3dc-75ce15896231
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291733090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.4291733090
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2488840746
Short name T613
Test name
Test status
Simulation time 1472576774 ps
CPU time 2.03 seconds
Started Mar 17 02:52:36 PM PDT 24
Finished Mar 17 02:52:38 PM PDT 24
Peak memory 197932 kb
Host smart-5951df7f-eb88-4b59-8a11-533b45a03a65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488840746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2488840746
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3541795987
Short name T274
Test name
Test status
Simulation time 54827223 ps
CPU time 1.04 seconds
Started Mar 17 02:52:30 PM PDT 24
Finished Mar 17 02:52:32 PM PDT 24
Peak memory 195528 kb
Host smart-5854d1dc-a869-4a77-be99-c2a730c8b1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541795987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3541795987
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3201000049
Short name T567
Test name
Test status
Simulation time 35834505 ps
CPU time 1.05 seconds
Started Mar 17 02:52:30 PM PDT 24
Finished Mar 17 02:52:32 PM PDT 24
Peak memory 195824 kb
Host smart-22819076-c881-45cf-a9de-71749b212e1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201000049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3201000049
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3636377563
Short name T437
Test name
Test status
Simulation time 5381285742 ps
CPU time 145.55 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:55:17 PM PDT 24
Peak memory 198164 kb
Host smart-6ab94b97-2258-4228-be8c-b139b7f73445
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636377563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3636377563
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2195719583
Short name T54
Test name
Test status
Simulation time 68685518 ps
CPU time 0.58 seconds
Started Mar 17 02:51:19 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 193936 kb
Host smart-828c0410-5e80-478c-a4d1-c25d670dbc8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195719583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2195719583
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3417449193
Short name T133
Test name
Test status
Simulation time 69322835 ps
CPU time 0.84 seconds
Started Mar 17 02:51:18 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 195380 kb
Host smart-bef42a42-a48f-44e9-9b56-1a917294518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417449193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3417449193
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4273210546
Short name T428
Test name
Test status
Simulation time 508232327 ps
CPU time 8.66 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:29 PM PDT 24
Peak memory 197980 kb
Host smart-f09597bb-cbc2-4ebc-bb67-2404ad04a10a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273210546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4273210546
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2650918764
Short name T507
Test name
Test status
Simulation time 96163455 ps
CPU time 1.08 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:24 PM PDT 24
Peak memory 196640 kb
Host smart-01451122-a6fe-44f7-b92a-52a6fbae0e1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650918764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2650918764
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.4225886369
Short name T708
Test name
Test status
Simulation time 102596478 ps
CPU time 1.38 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 197136 kb
Host smart-5b8e8c83-85bd-4c8a-b927-b168cc696830
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225886369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.4225886369
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1753586251
Short name T220
Test name
Test status
Simulation time 344778742 ps
CPU time 2.54 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 198120 kb
Host smart-63c70986-399f-4b0b-8a0c-ea489a0fa777
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753586251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1753586251
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.547991046
Short name T498
Test name
Test status
Simulation time 200961439 ps
CPU time 1.78 seconds
Started Mar 17 02:51:16 PM PDT 24
Finished Mar 17 02:51:18 PM PDT 24
Peak memory 196980 kb
Host smart-0f66461f-f909-4b87-aa77-2692c5a07490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547991046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.547991046
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3487720545
Short name T28
Test name
Test status
Simulation time 219111355 ps
CPU time 1.04 seconds
Started Mar 17 02:51:18 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 195824 kb
Host smart-d7797c4a-5e7d-4a00-a43f-d2883c3c8a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487720545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3487720545
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3245005226
Short name T288
Test name
Test status
Simulation time 90625470 ps
CPU time 0.96 seconds
Started Mar 17 02:51:19 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 196656 kb
Host smart-be8f3d06-3219-4f62-9f5d-05ae7f6977d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245005226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3245005226
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.317641245
Short name T561
Test name
Test status
Simulation time 38156274 ps
CPU time 1.84 seconds
Started Mar 17 02:51:18 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 197948 kb
Host smart-9db1500f-51e0-46f7-8190-56c5aa689d52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317641245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.317641245
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1140647861
Short name T53
Test name
Test status
Simulation time 64483209 ps
CPU time 0.86 seconds
Started Mar 17 02:51:18 PM PDT 24
Finished Mar 17 02:51:19 PM PDT 24
Peak memory 213808 kb
Host smart-123e0d23-ffe4-4f4e-8fcd-7a77e9f6e43f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140647861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1140647861
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3127486935
Short name T678
Test name
Test status
Simulation time 146852256 ps
CPU time 0.95 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:22 PM PDT 24
Peak memory 196580 kb
Host smart-dc243103-3cc3-4e52-87c1-bf9dd786e81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127486935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3127486935
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2774136269
Short name T495
Test name
Test status
Simulation time 120818122 ps
CPU time 0.98 seconds
Started Mar 17 02:51:19 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 195804 kb
Host smart-f3477105-c3c8-4000-969e-f8e5f97352a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774136269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2774136269
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3785765007
Short name T590
Test name
Test status
Simulation time 3775928662 ps
CPU time 26.22 seconds
Started Mar 17 02:51:17 PM PDT 24
Finished Mar 17 02:51:43 PM PDT 24
Peak memory 198196 kb
Host smart-1580dcf4-e506-4109-b3b2-bc8b42946426
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785765007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3785765007
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1211429018
Short name T62
Test name
Test status
Simulation time 79888869431 ps
CPU time 2053.47 seconds
Started Mar 17 02:51:20 PM PDT 24
Finished Mar 17 03:25:34 PM PDT 24
Peak memory 198172 kb
Host smart-8445bd7d-def2-4f01-a1e9-c4b9778e3798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1211429018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1211429018
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2396171726
Short name T632
Test name
Test status
Simulation time 42311731 ps
CPU time 0.58 seconds
Started Mar 17 02:52:48 PM PDT 24
Finished Mar 17 02:52:49 PM PDT 24
Peak memory 194584 kb
Host smart-433e9970-baac-4f50-95d0-e5e6ffe9ef5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396171726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2396171726
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.505629291
Short name T693
Test name
Test status
Simulation time 35434385 ps
CPU time 0.76 seconds
Started Mar 17 02:52:36 PM PDT 24
Finished Mar 17 02:52:36 PM PDT 24
Peak memory 195280 kb
Host smart-6df22a5a-d205-426d-98a9-1a73608d5eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505629291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.505629291
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3436957506
Short name T523
Test name
Test status
Simulation time 187065554 ps
CPU time 9.04 seconds
Started Mar 17 02:52:35 PM PDT 24
Finished Mar 17 02:52:44 PM PDT 24
Peak memory 196908 kb
Host smart-0022419d-455a-4a3b-9b14-aa67329efa7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436957506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3436957506
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2634883247
Short name T421
Test name
Test status
Simulation time 74652212 ps
CPU time 0.88 seconds
Started Mar 17 02:52:37 PM PDT 24
Finished Mar 17 02:52:38 PM PDT 24
Peak memory 196980 kb
Host smart-11bb7766-7580-4d1b-8398-8cee66d92a84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634883247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2634883247
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3495214461
Short name T606
Test name
Test status
Simulation time 87486696 ps
CPU time 0.86 seconds
Started Mar 17 02:52:38 PM PDT 24
Finished Mar 17 02:52:39 PM PDT 24
Peak memory 195592 kb
Host smart-f4d03d27-f4fa-474d-bbba-6117853465b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495214461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3495214461
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1982034087
Short name T108
Test name
Test status
Simulation time 742315091 ps
CPU time 2.32 seconds
Started Mar 17 02:52:38 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 197932 kb
Host smart-a9c05a7c-ccb0-4707-8d25-cef6c6fa434f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982034087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1982034087
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2574197706
Short name T541
Test name
Test status
Simulation time 56563507 ps
CPU time 1.12 seconds
Started Mar 17 02:52:36 PM PDT 24
Finished Mar 17 02:52:37 PM PDT 24
Peak memory 195560 kb
Host smart-dc407d08-01f2-4b62-a342-f2013d1155d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574197706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2574197706
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2521010429
Short name T280
Test name
Test status
Simulation time 35581314 ps
CPU time 0.84 seconds
Started Mar 17 02:52:45 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 195484 kb
Host smart-249a8b8a-13bb-459c-8921-b80c6b15b31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521010429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2521010429
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2183319261
Short name T515
Test name
Test status
Simulation time 82546301 ps
CPU time 1.4 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:46 PM PDT 24
Peak memory 197056 kb
Host smart-baffe850-2500-4c17-9a9f-6afcc4c66d8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183319261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2183319261
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2989911614
Short name T692
Test name
Test status
Simulation time 181107124 ps
CPU time 3.12 seconds
Started Mar 17 02:52:36 PM PDT 24
Finished Mar 17 02:52:39 PM PDT 24
Peak memory 197888 kb
Host smart-fb51e8d1-4f9c-4620-8760-ccf55c16403b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989911614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2989911614
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1996524671
Short name T309
Test name
Test status
Simulation time 111181747 ps
CPU time 1.31 seconds
Started Mar 17 02:52:49 PM PDT 24
Finished Mar 17 02:52:50 PM PDT 24
Peak memory 196832 kb
Host smart-306fa10b-d8ea-4f19-99c4-c388269c0da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996524671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1996524671
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2940662869
Short name T441
Test name
Test status
Simulation time 181222811 ps
CPU time 1.4 seconds
Started Mar 17 02:52:37 PM PDT 24
Finished Mar 17 02:52:38 PM PDT 24
Peak memory 196800 kb
Host smart-df4dfaa7-adaf-451c-ab63-f1c584a0fbc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940662869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2940662869
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.4180075602
Short name T15
Test name
Test status
Simulation time 59445393859 ps
CPU time 193.83 seconds
Started Mar 17 02:52:37 PM PDT 24
Finished Mar 17 02:55:51 PM PDT 24
Peak memory 198212 kb
Host smart-7cf21ffa-f8cb-4cb8-90ba-e1a887a75ad6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180075602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.4180075602
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3378533337
Short name T262
Test name
Test status
Simulation time 13215426 ps
CPU time 0.59 seconds
Started Mar 17 02:52:45 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 194584 kb
Host smart-391259e3-17ee-48a0-bf5f-1777c2ab2f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378533337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3378533337
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3467803569
Short name T319
Test name
Test status
Simulation time 18604163 ps
CPU time 0.72 seconds
Started Mar 17 02:52:49 PM PDT 24
Finished Mar 17 02:52:50 PM PDT 24
Peak memory 194172 kb
Host smart-83ae49f9-741a-494d-99a7-a60e3c61f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467803569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3467803569
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3477726199
Short name T34
Test name
Test status
Simulation time 319074218 ps
CPU time 4.5 seconds
Started Mar 17 02:52:37 PM PDT 24
Finished Mar 17 02:52:42 PM PDT 24
Peak memory 195564 kb
Host smart-28fcbc35-67be-4e4d-92de-65688f29be49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477726199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3477726199
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1210486455
Short name T285
Test name
Test status
Simulation time 148998132 ps
CPU time 0.74 seconds
Started Mar 17 02:52:45 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 194768 kb
Host smart-8ef524b2-97f3-4b50-bab9-6651d07c6913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210486455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1210486455
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2880023389
Short name T663
Test name
Test status
Simulation time 337361806 ps
CPU time 1.35 seconds
Started Mar 17 02:52:46 PM PDT 24
Finished Mar 17 02:52:48 PM PDT 24
Peak memory 196744 kb
Host smart-44b3f328-86bd-43ce-8de4-657c0d755dcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880023389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2880023389
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1313819871
Short name T239
Test name
Test status
Simulation time 68776339 ps
CPU time 2.73 seconds
Started Mar 17 02:52:39 PM PDT 24
Finished Mar 17 02:52:42 PM PDT 24
Peak memory 198060 kb
Host smart-998eee88-b49c-4358-94ef-9e351d8a53e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313819871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1313819871
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3922308234
Short name T228
Test name
Test status
Simulation time 129160995 ps
CPU time 2.02 seconds
Started Mar 17 02:52:46 PM PDT 24
Finished Mar 17 02:52:48 PM PDT 24
Peak memory 197076 kb
Host smart-de0ba62e-00c7-4a88-b372-1f68468ab18e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922308234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3922308234
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.4157483406
Short name T364
Test name
Test status
Simulation time 415588887 ps
CPU time 1.26 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 198068 kb
Host smart-ba84a7d4-4920-4e79-b881-30e79019e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157483406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.4157483406
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2674723091
Short name T436
Test name
Test status
Simulation time 46693236 ps
CPU time 1.29 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:54 PM PDT 24
Peak memory 196880 kb
Host smart-d5e1dcc7-40eb-464e-ad52-6472a60ee183
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674723091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2674723091
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1828752517
Short name T508
Test name
Test status
Simulation time 254875162 ps
CPU time 1.36 seconds
Started Mar 17 02:52:42 PM PDT 24
Finished Mar 17 02:52:43 PM PDT 24
Peak memory 198004 kb
Host smart-3f70ecc9-2020-4ec5-b78c-563d437df004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828752517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1828752517
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.911796513
Short name T131
Test name
Test status
Simulation time 38368155 ps
CPU time 1.19 seconds
Started Mar 17 02:52:48 PM PDT 24
Finished Mar 17 02:52:50 PM PDT 24
Peak memory 196536 kb
Host smart-6d66fdd8-92d0-4e21-8166-84252d1ba743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911796513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.911796513
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2872133363
Short name T146
Test name
Test status
Simulation time 177664639 ps
CPU time 1.36 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 196732 kb
Host smart-17542b73-99ce-477f-84e2-338ec78aa452
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872133363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2872133363
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1883228855
Short name T19
Test name
Test status
Simulation time 73115170378 ps
CPU time 149.7 seconds
Started Mar 17 02:52:49 PM PDT 24
Finished Mar 17 02:55:19 PM PDT 24
Peak memory 198112 kb
Host smart-902d1781-3651-43de-aee3-e921b47b0e03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883228855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1883228855
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.869821928
Short name T547
Test name
Test status
Simulation time 20204145 ps
CPU time 0.57 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 193924 kb
Host smart-8ebbe572-8743-45a6-aaa5-b2972d94549f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869821928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.869821928
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.894694800
Short name T413
Test name
Test status
Simulation time 36149249 ps
CPU time 0.71 seconds
Started Mar 17 02:52:38 PM PDT 24
Finished Mar 17 02:52:39 PM PDT 24
Peak memory 194164 kb
Host smart-63f1638d-31dd-41ea-9492-2367c63ba061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894694800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.894694800
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3398566583
Short name T250
Test name
Test status
Simulation time 1796339588 ps
CPU time 15.83 seconds
Started Mar 17 02:52:39 PM PDT 24
Finished Mar 17 02:52:55 PM PDT 24
Peak memory 197984 kb
Host smart-ae553007-0a46-43f8-81ff-29ea8a1a40ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398566583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3398566583
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3525446667
Short name T455
Test name
Test status
Simulation time 126739175 ps
CPU time 0.88 seconds
Started Mar 17 02:52:50 PM PDT 24
Finished Mar 17 02:52:51 PM PDT 24
Peak memory 195876 kb
Host smart-55503e91-897a-47af-9488-e05244788aff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525446667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3525446667
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1439509322
Short name T270
Test name
Test status
Simulation time 122516953 ps
CPU time 1 seconds
Started Mar 17 02:52:39 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 195940 kb
Host smart-3b59ea4c-f494-498a-8014-c78f781befef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439509322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1439509322
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2388140907
Short name T485
Test name
Test status
Simulation time 88483421 ps
CPU time 1.06 seconds
Started Mar 17 02:52:47 PM PDT 24
Finished Mar 17 02:52:48 PM PDT 24
Peak memory 196772 kb
Host smart-4e406992-a098-430e-9697-7e12cf342259
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388140907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2388140907
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.646869277
Short name T161
Test name
Test status
Simulation time 132367531 ps
CPU time 1.77 seconds
Started Mar 17 02:52:35 PM PDT 24
Finished Mar 17 02:52:37 PM PDT 24
Peak memory 196148 kb
Host smart-27e4a047-63eb-4bc4-b78d-c291ff7836ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646869277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
646869277
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.121780009
Short name T67
Test name
Test status
Simulation time 92668568 ps
CPU time 1.06 seconds
Started Mar 17 02:52:45 PM PDT 24
Finished Mar 17 02:52:46 PM PDT 24
Peak memory 195784 kb
Host smart-2fa7eac1-ef94-46c2-a0b0-9fb1ce48e1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121780009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.121780009
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3926209588
Short name T702
Test name
Test status
Simulation time 32275885 ps
CPU time 1.23 seconds
Started Mar 17 02:52:48 PM PDT 24
Finished Mar 17 02:52:49 PM PDT 24
Peak memory 197024 kb
Host smart-d3439ee7-9741-48b8-b6aa-f27490b4a974
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926209588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3926209588
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.874070557
Short name T430
Test name
Test status
Simulation time 414355713 ps
CPU time 1.67 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:42 PM PDT 24
Peak memory 198004 kb
Host smart-136232fd-e3d6-44d7-a78f-d68c9927b23b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874070557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.874070557
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3340813190
Short name T424
Test name
Test status
Simulation time 135803384 ps
CPU time 1.27 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 196864 kb
Host smart-c635d2a1-8427-4051-a8e1-87b36d9bb610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340813190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3340813190
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.521189038
Short name T514
Test name
Test status
Simulation time 135323696 ps
CPU time 1.32 seconds
Started Mar 17 02:52:47 PM PDT 24
Finished Mar 17 02:52:48 PM PDT 24
Peak memory 196768 kb
Host smart-a1de30b0-6538-4f18-8326-855f1f71ffa6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521189038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.521189038
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2531160024
Short name T408
Test name
Test status
Simulation time 4576045851 ps
CPU time 128.74 seconds
Started Mar 17 02:52:38 PM PDT 24
Finished Mar 17 02:54:46 PM PDT 24
Peak memory 198260 kb
Host smart-095c7601-850b-4811-9af6-d4b481a63c68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531160024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2531160024
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3094940495
Short name T63
Test name
Test status
Simulation time 32791953055 ps
CPU time 254.38 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:57:06 PM PDT 24
Peak memory 198256 kb
Host smart-2287c0fa-1dbf-4dbd-b6fa-ca4b74ee6838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3094940495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3094940495
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.4125393364
Short name T339
Test name
Test status
Simulation time 36947374 ps
CPU time 0.57 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 193904 kb
Host smart-1163b981-e418-4534-ac24-b50068558781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125393364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.4125393364
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1314586254
Short name T134
Test name
Test status
Simulation time 86264603 ps
CPU time 1.01 seconds
Started Mar 17 02:52:42 PM PDT 24
Finished Mar 17 02:52:43 PM PDT 24
Peak memory 196404 kb
Host smart-c6ce9cf5-6473-43d4-b570-ebb1561314e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314586254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1314586254
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3920639942
Short name T132
Test name
Test status
Simulation time 448145824 ps
CPU time 13.25 seconds
Started Mar 17 02:52:41 PM PDT 24
Finished Mar 17 02:52:54 PM PDT 24
Peak memory 195452 kb
Host smart-1f4e1cf9-e517-4133-8485-41d588932eee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920639942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3920639942
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2005915031
Short name T249
Test name
Test status
Simulation time 172402403 ps
CPU time 0.8 seconds
Started Mar 17 02:52:55 PM PDT 24
Finished Mar 17 02:52:56 PM PDT 24
Peak memory 196684 kb
Host smart-304b2795-02e7-4f04-8900-3d929ff2099b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005915031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2005915031
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1902370643
Short name T70
Test name
Test status
Simulation time 223908831 ps
CPU time 1.46 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 197152 kb
Host smart-163de1b4-b891-4ac4-82ef-34b12baa1e0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902370643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1902370643
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.14720467
Short name T566
Test name
Test status
Simulation time 364157002 ps
CPU time 3.6 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:53:00 PM PDT 24
Peak memory 198080 kb
Host smart-6fb49c93-adc2-4977-97fa-bd16c044e4d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14720467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.gpio_intr_with_filter_rand_intr_event.14720467
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2501026751
Short name T267
Test name
Test status
Simulation time 725890708 ps
CPU time 2.97 seconds
Started Mar 17 02:52:41 PM PDT 24
Finished Mar 17 02:52:44 PM PDT 24
Peak memory 197272 kb
Host smart-dcd58968-095f-42da-89cb-5c4985b5c3ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501026751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2501026751
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1636053246
Short name T143
Test name
Test status
Simulation time 607468642 ps
CPU time 1.14 seconds
Started Mar 17 02:52:49 PM PDT 24
Finished Mar 17 02:52:50 PM PDT 24
Peak memory 195900 kb
Host smart-6d1e8ce9-9d2e-484f-9d39-154f46360e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636053246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1636053246
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.731977850
Short name T671
Test name
Test status
Simulation time 32258021 ps
CPU time 0.77 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:52:52 PM PDT 24
Peak memory 195468 kb
Host smart-0c428da6-1efd-4c36-8aff-ed51c7b652fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731977850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.731977850
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3845538309
Short name T6
Test name
Test status
Simulation time 392052360 ps
CPU time 5.31 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:49 PM PDT 24
Peak memory 197304 kb
Host smart-97ff1e52-d7a8-4213-8fc2-2c8bf6da0f97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845538309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3845538309
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.333044585
Short name T544
Test name
Test status
Simulation time 64087152 ps
CPU time 1.26 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:52:52 PM PDT 24
Peak memory 196796 kb
Host smart-65769085-73a9-4a19-ad9e-eab386841c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333044585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.333044585
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3875248461
Short name T476
Test name
Test status
Simulation time 304158843 ps
CPU time 1.32 seconds
Started Mar 17 02:52:45 PM PDT 24
Finished Mar 17 02:52:46 PM PDT 24
Peak memory 195548 kb
Host smart-0e61051c-adb9-415a-97ce-5d454e053587
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875248461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3875248461
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3557617781
Short name T600
Test name
Test status
Simulation time 43353398312 ps
CPU time 122.11 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:54:54 PM PDT 24
Peak memory 198184 kb
Host smart-67d13641-b3a3-429e-9d94-3d8aa229a352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557617781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3557617781
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.333471133
Short name T321
Test name
Test status
Simulation time 16878335 ps
CPU time 0.62 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:54 PM PDT 24
Peak memory 193952 kb
Host smart-a2917040-6a44-415d-b43a-00371cb9d0d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333471133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.333471133
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3737092324
Short name T551
Test name
Test status
Simulation time 152916384 ps
CPU time 0.89 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 197088 kb
Host smart-4a9b5970-fcd3-42ea-816e-6ee23ca91695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737092324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3737092324
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.657919398
Short name T715
Test name
Test status
Simulation time 835861815 ps
CPU time 4.15 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:57 PM PDT 24
Peak memory 195864 kb
Host smart-0f991132-a51d-49cc-a137-c1155e9a2e04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657919398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.657919398
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.265962080
Short name T114
Test name
Test status
Simulation time 59407400 ps
CPU time 0.8 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:52:52 PM PDT 24
Peak memory 196188 kb
Host smart-b856cc5a-1419-4ebf-ae71-eb035dab5f20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265962080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.265962080
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1559465134
Short name T499
Test name
Test status
Simulation time 170584710 ps
CPU time 0.75 seconds
Started Mar 17 02:53:00 PM PDT 24
Finished Mar 17 02:53:01 PM PDT 24
Peak memory 194488 kb
Host smart-8c35b888-75eb-4d27-a568-f33baf3d2652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559465134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1559465134
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1041326763
Short name T655
Test name
Test status
Simulation time 33374603 ps
CPU time 1.46 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:52:59 PM PDT 24
Peak memory 197704 kb
Host smart-f1701e60-60d2-4a92-94d3-b1adf4a32898
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041326763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1041326763
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1118621755
Short name T417
Test name
Test status
Simulation time 105261222 ps
CPU time 1.75 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:42 PM PDT 24
Peak memory 195788 kb
Host smart-8dcbd99e-0820-45e3-8c7b-997634f4fea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118621755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1118621755
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2769303559
Short name T529
Test name
Test status
Simulation time 17776384 ps
CPU time 0.74 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:41 PM PDT 24
Peak memory 195388 kb
Host smart-9c7d3b90-7085-4473-8dc0-9fcb37f0cacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769303559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2769303559
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2537392784
Short name T650
Test name
Test status
Simulation time 142288686 ps
CPU time 1.31 seconds
Started Mar 17 02:52:41 PM PDT 24
Finished Mar 17 02:52:42 PM PDT 24
Peak memory 197132 kb
Host smart-9699066b-8eed-4b67-90bb-406b393a36b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537392784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2537392784
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3460933239
Short name T442
Test name
Test status
Simulation time 533224892 ps
CPU time 1.91 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 198000 kb
Host smart-5065ae0a-b4f4-461a-a228-ecc981d068f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460933239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3460933239
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3194944302
Short name T687
Test name
Test status
Simulation time 311622578 ps
CPU time 1.38 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 196828 kb
Host smart-18c73557-ac44-45d1-9ec8-630dfa69923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194944302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3194944302
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1915992858
Short name T227
Test name
Test status
Simulation time 277164150 ps
CPU time 1.29 seconds
Started Mar 17 02:52:55 PM PDT 24
Finished Mar 17 02:52:57 PM PDT 24
Peak memory 195804 kb
Host smart-80220ac0-4277-4c57-a990-983017b0b6b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915992858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1915992858
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3472855579
Short name T396
Test name
Test status
Simulation time 29993726048 ps
CPU time 209.54 seconds
Started Mar 17 02:52:43 PM PDT 24
Finished Mar 17 02:56:13 PM PDT 24
Peak memory 198092 kb
Host smart-8ce44287-3488-4e49-b1f2-8c22b48c37aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472855579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3472855579
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2020014190
Short name T506
Test name
Test status
Simulation time 45988264 ps
CPU time 0.6 seconds
Started Mar 17 02:52:59 PM PDT 24
Finished Mar 17 02:53:00 PM PDT 24
Peak memory 193860 kb
Host smart-14a72918-fa4c-422a-9973-1908111db855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020014190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2020014190
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2121968594
Short name T694
Test name
Test status
Simulation time 17701094 ps
CPU time 0.66 seconds
Started Mar 17 02:52:43 PM PDT 24
Finished Mar 17 02:52:44 PM PDT 24
Peak memory 194048 kb
Host smart-caacc878-1d9d-4c5f-9f85-23b926042de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121968594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2121968594
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1814542089
Short name T399
Test name
Test status
Simulation time 540358053 ps
CPU time 19.48 seconds
Started Mar 17 02:52:39 PM PDT 24
Finished Mar 17 02:52:59 PM PDT 24
Peak memory 198024 kb
Host smart-d71d001f-c090-41a2-b7d7-70d93b2eaf9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814542089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1814542089
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1472195051
Short name T394
Test name
Test status
Simulation time 407293897 ps
CPU time 1.1 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:46 PM PDT 24
Peak memory 196668 kb
Host smart-05fe5135-6207-4744-8d40-fa9bb030de83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472195051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1472195051
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3680057913
Short name T242
Test name
Test status
Simulation time 55385265 ps
CPU time 1.39 seconds
Started Mar 17 02:52:43 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 196860 kb
Host smart-633c5a4a-e303-4d66-abf6-362234f9ef0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680057913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3680057913
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1680582655
Short name T171
Test name
Test status
Simulation time 75402772 ps
CPU time 1.03 seconds
Started Mar 17 02:52:42 PM PDT 24
Finished Mar 17 02:52:43 PM PDT 24
Peak memory 196444 kb
Host smart-98c25132-a3be-4779-ba32-d7e0dc2c999c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680582655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1680582655
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3983615200
Short name T163
Test name
Test status
Simulation time 76524968 ps
CPU time 2.67 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:52:59 PM PDT 24
Peak memory 198000 kb
Host smart-7c48e12b-f8f4-4828-b8d4-8bff1487fc40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983615200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3983615200
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1753787803
Short name T633
Test name
Test status
Simulation time 57557379 ps
CPU time 1.24 seconds
Started Mar 17 02:52:38 PM PDT 24
Finished Mar 17 02:52:39 PM PDT 24
Peak memory 196604 kb
Host smart-d2eb1dcb-122d-49be-b20f-3fa6bce44334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753787803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1753787803
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.341361129
Short name T517
Test name
Test status
Simulation time 46691065 ps
CPU time 1.11 seconds
Started Mar 17 02:52:55 PM PDT 24
Finished Mar 17 02:52:56 PM PDT 24
Peak memory 195948 kb
Host smart-2eb83c0d-1fe6-4bbd-bf5a-279888f976dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341361129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.341361129
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.909526202
Short name T5
Test name
Test status
Simulation time 423002308 ps
CPU time 2.72 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:43 PM PDT 24
Peak memory 197936 kb
Host smart-44ec1898-63de-4a9b-86a7-e912a015c0cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909526202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.909526202
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1051577275
Short name T558
Test name
Test status
Simulation time 96834560 ps
CPU time 1.27 seconds
Started Mar 17 02:53:01 PM PDT 24
Finished Mar 17 02:53:02 PM PDT 24
Peak memory 196504 kb
Host smart-33558ff9-07fa-4314-a462-434abe2d1ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051577275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1051577275
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2235967679
Short name T580
Test name
Test status
Simulation time 114474667 ps
CPU time 1.14 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 195376 kb
Host smart-ddfae6c2-e5ab-4013-99d9-8fca09c3e6c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235967679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2235967679
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1152787033
Short name T155
Test name
Test status
Simulation time 980944075 ps
CPU time 26.74 seconds
Started Mar 17 02:52:42 PM PDT 24
Finished Mar 17 02:53:09 PM PDT 24
Peak memory 198044 kb
Host smart-c5cc50bd-c718-487e-8a1a-14d75c3e6514
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152787033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1152787033
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2450894589
Short name T363
Test name
Test status
Simulation time 13868281 ps
CPU time 0.63 seconds
Started Mar 17 02:52:50 PM PDT 24
Finished Mar 17 02:52:51 PM PDT 24
Peak memory 193956 kb
Host smart-40a9c548-6969-4b54-8548-3314ff65ca9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450894589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2450894589
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2162379332
Short name T287
Test name
Test status
Simulation time 79262436 ps
CPU time 0.81 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:54 PM PDT 24
Peak memory 195444 kb
Host smart-6a65dd54-e242-4ea8-bd2d-b403769d9582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162379332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2162379332
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1195722755
Short name T711
Test name
Test status
Simulation time 2996364309 ps
CPU time 14.74 seconds
Started Mar 17 02:52:43 PM PDT 24
Finished Mar 17 02:52:58 PM PDT 24
Peak memory 196932 kb
Host smart-261ac0a8-d9b0-413a-b357-a3e6b7d66911
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195722755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1195722755
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2010839420
Short name T278
Test name
Test status
Simulation time 28865446 ps
CPU time 0.67 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:52:54 PM PDT 24
Peak memory 194976 kb
Host smart-5d38d03b-912f-46d3-bee6-6fea2dc52d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010839420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2010839420
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2015370568
Short name T199
Test name
Test status
Simulation time 56505169 ps
CPU time 0.95 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:52:55 PM PDT 24
Peak memory 196032 kb
Host smart-48a68565-7c6b-419a-aeb1-bb68af1d300c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015370568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2015370568
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1466310049
Short name T374
Test name
Test status
Simulation time 59830077 ps
CPU time 1.94 seconds
Started Mar 17 02:52:45 PM PDT 24
Finished Mar 17 02:52:47 PM PDT 24
Peak memory 198032 kb
Host smart-adf686a2-5a94-4b4b-b98b-68dafbdb49a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466310049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1466310049
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.4197331439
Short name T568
Test name
Test status
Simulation time 601476237 ps
CPU time 3.3 seconds
Started Mar 17 02:52:58 PM PDT 24
Finished Mar 17 02:53:02 PM PDT 24
Peak memory 198068 kb
Host smart-0d7ebc82-94e4-4f78-a865-e6d7eca886e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197331439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.4197331439
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3982458961
Short name T586
Test name
Test status
Simulation time 60878132 ps
CPU time 0.72 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:52:55 PM PDT 24
Peak memory 196124 kb
Host smart-a3d03881-3cdb-4630-bb40-484ff201ca11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982458961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3982458961
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.741362089
Short name T565
Test name
Test status
Simulation time 86679537 ps
CPU time 1.21 seconds
Started Mar 17 02:52:42 PM PDT 24
Finished Mar 17 02:52:44 PM PDT 24
Peak memory 196748 kb
Host smart-4759419b-ad2f-4e34-a2c0-c7769208eb2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741362089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.741362089
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2420929314
Short name T176
Test name
Test status
Simulation time 233758605 ps
CPU time 1.99 seconds
Started Mar 17 02:52:49 PM PDT 24
Finished Mar 17 02:52:51 PM PDT 24
Peak memory 197888 kb
Host smart-f1434721-8416-4301-9f8d-c96c44657fe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420929314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2420929314
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2310797585
Short name T145
Test name
Test status
Simulation time 138226903 ps
CPU time 1.33 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 196256 kb
Host smart-441f8b4a-2b8a-4fc4-9bb2-406f2ab7249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310797585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2310797585
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2990801440
Short name T123
Test name
Test status
Simulation time 47680104 ps
CPU time 1.01 seconds
Started Mar 17 02:52:40 PM PDT 24
Finished Mar 17 02:52:42 PM PDT 24
Peak memory 195528 kb
Host smart-83dba1f3-ebb3-4904-99a9-eb5473809727
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990801440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2990801440
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.263330279
Short name T612
Test name
Test status
Simulation time 3807651325 ps
CPU time 53.39 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:53:46 PM PDT 24
Peak memory 198184 kb
Host smart-3171de1a-fe6d-4bdd-9c56-53d260d3f4ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263330279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.263330279
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.619706470
Short name T604
Test name
Test status
Simulation time 16727793 ps
CPU time 0.59 seconds
Started Mar 17 02:53:01 PM PDT 24
Finished Mar 17 02:53:02 PM PDT 24
Peak memory 194764 kb
Host smart-75f04ac5-899d-416f-87d0-ded5e5c50474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619706470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.619706470
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3598256211
Short name T275
Test name
Test status
Simulation time 37646552 ps
CPU time 0.65 seconds
Started Mar 17 02:52:48 PM PDT 24
Finished Mar 17 02:52:49 PM PDT 24
Peak memory 194800 kb
Host smart-616d8028-a5da-47f1-9c0a-03c82d2b7acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598256211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3598256211
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.645862159
Short name T628
Test name
Test status
Simulation time 1356106058 ps
CPU time 23.93 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:53:21 PM PDT 24
Peak memory 198052 kb
Host smart-77326576-a414-4366-ac9a-642c86b9dfd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645862159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.645862159
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2253028342
Short name T377
Test name
Test status
Simulation time 130141982 ps
CPU time 1.01 seconds
Started Mar 17 02:53:04 PM PDT 24
Finished Mar 17 02:53:05 PM PDT 24
Peak memory 197968 kb
Host smart-47e9f087-7349-4d76-bd7e-cc04dbcfe6ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253028342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2253028342
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3038717133
Short name T124
Test name
Test status
Simulation time 42041886 ps
CPU time 1.23 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 02:52:52 PM PDT 24
Peak memory 196228 kb
Host smart-a48520d9-f3eb-4504-ad85-dc6e2d1f5958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038717133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3038717133
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3088793825
Short name T589
Test name
Test status
Simulation time 360777026 ps
CPU time 4.04 seconds
Started Mar 17 02:52:46 PM PDT 24
Finished Mar 17 02:52:51 PM PDT 24
Peak memory 196504 kb
Host smart-d8f78c0b-91da-4e5c-ab44-8eefcbc4a6ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088793825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3088793825
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1529376304
Short name T553
Test name
Test status
Simulation time 454799163 ps
CPU time 1.82 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:52:56 PM PDT 24
Peak memory 195760 kb
Host smart-65acb287-aed1-4556-89e7-f8f2c0fdca9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529376304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1529376304
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1863306949
Short name T349
Test name
Test status
Simulation time 50432197 ps
CPU time 1.1 seconds
Started Mar 17 02:53:03 PM PDT 24
Finished Mar 17 02:53:04 PM PDT 24
Peak memory 195840 kb
Host smart-788f3a1a-4986-484e-a43b-495c0f928284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863306949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1863306949
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.960148875
Short name T502
Test name
Test status
Simulation time 198618793 ps
CPU time 1.02 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:52:55 PM PDT 24
Peak memory 195720 kb
Host smart-ed427bd8-de9e-475a-a98a-89c2de83cd36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960148875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.960148875
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1502950406
Short name T148
Test name
Test status
Simulation time 31265595 ps
CPU time 1.3 seconds
Started Mar 17 02:53:31 PM PDT 24
Finished Mar 17 02:53:32 PM PDT 24
Peak memory 197984 kb
Host smart-9d700fd0-f07b-4808-b92a-80aca252f87e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502950406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1502950406
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2707970257
Short name T59
Test name
Test status
Simulation time 254062016 ps
CPU time 1.23 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 197140 kb
Host smart-310252ee-9d82-4ebb-8947-568d1a6f43a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707970257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2707970257
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2766249563
Short name T706
Test name
Test status
Simulation time 97680426 ps
CPU time 1.13 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:45 PM PDT 24
Peak memory 195780 kb
Host smart-122df99a-507f-4c37-b84e-4a59ff03e684
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766249563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2766249563
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3117245125
Short name T582
Test name
Test status
Simulation time 30818063782 ps
CPU time 82.47 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:54:19 PM PDT 24
Peak memory 198116 kb
Host smart-8f5dcef3-e98a-4a72-91d3-afab5c21d0bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117245125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3117245125
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.362562057
Short name T208
Test name
Test status
Simulation time 12012603 ps
CPU time 0.56 seconds
Started Mar 17 02:52:49 PM PDT 24
Finished Mar 17 02:52:50 PM PDT 24
Peak memory 193936 kb
Host smart-9d13ed8a-e514-4b5d-9e99-1f7bc59fafcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362562057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.362562057
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3137363310
Short name T617
Test name
Test status
Simulation time 30597216 ps
CPU time 0.9 seconds
Started Mar 17 02:52:48 PM PDT 24
Finished Mar 17 02:52:49 PM PDT 24
Peak memory 195708 kb
Host smart-36eba0e1-ad84-407a-9ef0-a9b1d15c66d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137363310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3137363310
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3610334850
Short name T468
Test name
Test status
Simulation time 2246261639 ps
CPU time 15.35 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:53:11 PM PDT 24
Peak memory 196328 kb
Host smart-675af6d5-418f-48cf-99b8-1e8209135554
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610334850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3610334850
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.618916392
Short name T192
Test name
Test status
Simulation time 204096786 ps
CPU time 0.82 seconds
Started Mar 17 02:52:50 PM PDT 24
Finished Mar 17 02:52:51 PM PDT 24
Peak memory 196020 kb
Host smart-9432444d-c9fc-4feb-956b-4559616f1612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618916392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.618916392
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1976308965
Short name T243
Test name
Test status
Simulation time 166448851 ps
CPU time 0.98 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:52:59 PM PDT 24
Peak memory 196012 kb
Host smart-7227fec3-a3ae-43bc-867a-6cf6ce678801
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976308965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1976308965
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.242989116
Short name T292
Test name
Test status
Simulation time 102328115 ps
CPU time 3.09 seconds
Started Mar 17 02:52:55 PM PDT 24
Finished Mar 17 02:52:58 PM PDT 24
Peak memory 198040 kb
Host smart-eb04680d-0bb4-4de4-bb2c-3bebf794b17b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242989116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.242989116
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3664601541
Short name T607
Test name
Test status
Simulation time 123243048 ps
CPU time 3.7 seconds
Started Mar 17 02:52:48 PM PDT 24
Finished Mar 17 02:52:52 PM PDT 24
Peak memory 197144 kb
Host smart-b28e2811-aeb4-4732-a7a1-31a98df35eeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664601541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3664601541
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1663798441
Short name T459
Test name
Test status
Simulation time 112953519 ps
CPU time 1.53 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:52:57 PM PDT 24
Peak memory 198036 kb
Host smart-e1b8eeee-11b2-414c-bf77-59ce2266fd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663798441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1663798441
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1767670269
Short name T326
Test name
Test status
Simulation time 372457539 ps
CPU time 1 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:52:55 PM PDT 24
Peak memory 195772 kb
Host smart-5354c537-fc19-4879-a465-1f0ce9d193b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767670269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1767670269
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1375082322
Short name T521
Test name
Test status
Simulation time 101515091 ps
CPU time 5.29 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:50 PM PDT 24
Peak memory 197976 kb
Host smart-990c6c80-a21f-498e-90d1-f1e35aba2181
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375082322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1375082322
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2276114942
Short name T479
Test name
Test status
Simulation time 24671474 ps
CPU time 0.81 seconds
Started Mar 17 02:52:44 PM PDT 24
Finished Mar 17 02:52:44 PM PDT 24
Peak memory 195348 kb
Host smart-223017c7-5027-42dc-b57e-463c97493f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276114942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2276114942
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1651003846
Short name T177
Test name
Test status
Simulation time 80268212 ps
CPU time 1.49 seconds
Started Mar 17 02:52:46 PM PDT 24
Finished Mar 17 02:52:48 PM PDT 24
Peak memory 196808 kb
Host smart-37edae8c-4a35-45aa-b039-27d5e9f0ac1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651003846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1651003846
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1768355723
Short name T166
Test name
Test status
Simulation time 44289447850 ps
CPU time 80.06 seconds
Started Mar 17 02:53:01 PM PDT 24
Finished Mar 17 02:54:21 PM PDT 24
Peak memory 198168 kb
Host smart-dec21651-6127-47a0-8dc7-5dd8c3370199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768355723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1768355723
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2869995326
Short name T411
Test name
Test status
Simulation time 17125645 ps
CPU time 0.58 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 193524 kb
Host smart-90f0f76a-3b0e-4e17-bc7a-285a24078600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869995326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2869995326
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1939255580
Short name T657
Test name
Test status
Simulation time 21923393 ps
CPU time 0.66 seconds
Started Mar 17 02:52:56 PM PDT 24
Finished Mar 17 02:52:57 PM PDT 24
Peak memory 194760 kb
Host smart-6611d6b4-8c53-4d3c-9a84-66e6ca3cc0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939255580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1939255580
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1588043291
Short name T419
Test name
Test status
Simulation time 2516906840 ps
CPU time 15.46 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:53:10 PM PDT 24
Peak memory 197376 kb
Host smart-89feb785-3ad7-4d2c-b9fe-2d95c5c370a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588043291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1588043291
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2557801904
Short name T126
Test name
Test status
Simulation time 64345597 ps
CPU time 1.01 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:52:58 PM PDT 24
Peak memory 196532 kb
Host smart-80b69a79-72b9-4b05-9c9e-45b29406fa95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557801904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2557801904
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.352551103
Short name T681
Test name
Test status
Simulation time 42470122 ps
CPU time 0.84 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:54 PM PDT 24
Peak memory 196396 kb
Host smart-f2d9a276-5d5e-49e2-b31e-ca222bb4fad7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352551103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.352551103
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3245110012
Short name T109
Test name
Test status
Simulation time 86415835 ps
CPU time 3.66 seconds
Started Mar 17 02:53:00 PM PDT 24
Finished Mar 17 02:53:04 PM PDT 24
Peak memory 198064 kb
Host smart-e80fc771-72d1-44f7-b536-f11509dbc761
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245110012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3245110012
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1946478657
Short name T320
Test name
Test status
Simulation time 648897304 ps
CPU time 2.44 seconds
Started Mar 17 02:52:57 PM PDT 24
Finished Mar 17 02:52:59 PM PDT 24
Peak memory 198020 kb
Host smart-2ffc544e-c5ae-404c-98bb-7f9f64e2f065
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946478657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1946478657
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2631902396
Short name T182
Test name
Test status
Simulation time 30357559 ps
CPU time 0.87 seconds
Started Mar 17 02:52:52 PM PDT 24
Finished Mar 17 02:52:53 PM PDT 24
Peak memory 196348 kb
Host smart-d34161f9-13ad-4499-a73d-6e8536f65529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631902396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2631902396
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3055972829
Short name T371
Test name
Test status
Simulation time 139050303 ps
CPU time 1.08 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:52:54 PM PDT 24
Peak memory 196060 kb
Host smart-93643641-0bef-4c4b-8451-cd822bbdb039
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055972829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3055972829
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3937186940
Short name T323
Test name
Test status
Simulation time 108695129 ps
CPU time 4.98 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:52:59 PM PDT 24
Peak memory 198044 kb
Host smart-3ea78f03-c78e-4224-8c8f-0dd7a44aae1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937186940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3937186940
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3175268895
Short name T493
Test name
Test status
Simulation time 50698164 ps
CPU time 0.71 seconds
Started Mar 17 02:52:54 PM PDT 24
Finished Mar 17 02:52:55 PM PDT 24
Peak memory 194204 kb
Host smart-a8651311-82cd-4b1f-9513-da0c94c8d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175268895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3175268895
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1631243347
Short name T457
Test name
Test status
Simulation time 175806907 ps
CPU time 0.94 seconds
Started Mar 17 02:53:02 PM PDT 24
Finished Mar 17 02:53:03 PM PDT 24
Peak memory 195844 kb
Host smart-e417cc57-999d-4917-9b2e-a7691b808b06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631243347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1631243347
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3068822922
Short name T173
Test name
Test status
Simulation time 5705745396 ps
CPU time 36.81 seconds
Started Mar 17 02:52:53 PM PDT 24
Finished Mar 17 02:53:30 PM PDT 24
Peak memory 198192 kb
Host smart-c0c94c68-140f-44d9-b4d5-76ca20eb80f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068822922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3068822922
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2177587442
Short name T22
Test name
Test status
Simulation time 314656841840 ps
CPU time 1918.81 seconds
Started Mar 17 02:52:51 PM PDT 24
Finished Mar 17 03:24:50 PM PDT 24
Peak memory 206428 kb
Host smart-bbc905fe-05b5-4c86-9a89-2a07a6108a7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2177587442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2177587442
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.472021259
Short name T16
Test name
Test status
Simulation time 52711108 ps
CPU time 0.62 seconds
Started Mar 17 02:51:25 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 194008 kb
Host smart-ae8b8496-c0e6-4dba-ba8b-e7877637e47d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472021259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.472021259
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3442654051
Short name T129
Test name
Test status
Simulation time 53654598 ps
CPU time 0.67 seconds
Started Mar 17 02:51:26 PM PDT 24
Finished Mar 17 02:51:27 PM PDT 24
Peak memory 194828 kb
Host smart-f3c6fc9d-5b49-4f14-9dad-9a93f345c674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442654051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3442654051
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1431603501
Short name T119
Test name
Test status
Simulation time 244716201 ps
CPU time 8.49 seconds
Started Mar 17 02:51:20 PM PDT 24
Finished Mar 17 02:51:29 PM PDT 24
Peak memory 196936 kb
Host smart-483723b4-8bd2-4bf1-8b13-bf20c2f20501
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431603501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1431603501
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.514774082
Short name T372
Test name
Test status
Simulation time 67753308 ps
CPU time 1.04 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 196436 kb
Host smart-f2cb7036-457b-4256-9652-1447c90b0a94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514774082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.514774082
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.4243759763
Short name T501
Test name
Test status
Simulation time 16274422 ps
CPU time 0.65 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:21 PM PDT 24
Peak memory 194984 kb
Host smart-ecc53ed4-4aa1-4bb8-8005-5efb3fb6ac0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243759763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.4243759763
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4093013877
Short name T453
Test name
Test status
Simulation time 331098086 ps
CPU time 3.55 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 198104 kb
Host smart-786ef29c-b298-4317-aa74-32e7355dc03b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093013877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4093013877
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2360940433
Short name T209
Test name
Test status
Simulation time 243597216 ps
CPU time 3.31 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 197092 kb
Host smart-ebaabfe9-87db-4cf4-85c5-6ed1f8d64440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360940433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2360940433
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2781993757
Short name T492
Test name
Test status
Simulation time 119415998 ps
CPU time 1.25 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 197944 kb
Host smart-04da402e-40b1-4432-aef1-7ad413fb186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781993757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2781993757
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.277139734
Short name T700
Test name
Test status
Simulation time 24110748 ps
CPU time 0.65 seconds
Started Mar 17 02:51:23 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 195036 kb
Host smart-d928df11-5be7-46f0-8529-b7f034c19b1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277139734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.277139734
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3181686647
Short name T264
Test name
Test status
Simulation time 126678518 ps
CPU time 1.39 seconds
Started Mar 17 02:51:25 PM PDT 24
Finished Mar 17 02:51:27 PM PDT 24
Peak memory 198020 kb
Host smart-be080ba6-7ccd-4f63-adcb-59fb6c7243e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181686647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3181686647
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2629974808
Short name T519
Test name
Test status
Simulation time 56026732 ps
CPU time 0.99 seconds
Started Mar 17 02:51:19 PM PDT 24
Finished Mar 17 02:51:20 PM PDT 24
Peak memory 195596 kb
Host smart-68caaa65-e9d6-4d91-b9f9-fa494ebf5871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629974808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2629974808
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3571857559
Short name T414
Test name
Test status
Simulation time 248613223 ps
CPU time 1.11 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 195784 kb
Host smart-cd8857c6-9f34-4931-b1d1-58ac0f9d4a12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571857559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3571857559
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2896567331
Short name T142
Test name
Test status
Simulation time 2454734586 ps
CPU time 33.7 seconds
Started Mar 17 02:51:24 PM PDT 24
Finished Mar 17 02:51:58 PM PDT 24
Peak memory 198144 kb
Host smart-489a87a5-2318-4c46-94d0-d666c69316bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896567331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2896567331
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2361324379
Short name T66
Test name
Test status
Simulation time 181629005139 ps
CPU time 1867.78 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 03:22:30 PM PDT 24
Peak memory 198268 kb
Host smart-7ffcf6ed-3f02-4808-ad4c-5e6232c374f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2361324379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2361324379
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.511089838
Short name T648
Test name
Test status
Simulation time 16402787 ps
CPU time 0.58 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 194028 kb
Host smart-e50de804-bd57-4ec9-97d4-d48834ada404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511089838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.511089838
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.645697935
Short name T625
Test name
Test status
Simulation time 52305423 ps
CPU time 0.77 seconds
Started Mar 17 02:51:25 PM PDT 24
Finished Mar 17 02:51:26 PM PDT 24
Peak memory 196096 kb
Host smart-c5e47a1d-43ed-442d-8123-99afceb6e3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645697935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.645697935
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1058504036
Short name T35
Test name
Test status
Simulation time 990661911 ps
CPU time 12.62 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:35 PM PDT 24
Peak memory 197140 kb
Host smart-202b8abb-4371-494e-9466-1a0d2a39b368
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058504036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1058504036
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3837742705
Short name T324
Test name
Test status
Simulation time 143884107 ps
CPU time 0.68 seconds
Started Mar 17 02:51:24 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 194700 kb
Host smart-55192cf9-1cd8-404c-9112-e49619dd9e9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837742705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3837742705
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.650115148
Short name T593
Test name
Test status
Simulation time 29350839 ps
CPU time 0.93 seconds
Started Mar 17 02:51:23 PM PDT 24
Finished Mar 17 02:51:24 PM PDT 24
Peak memory 197544 kb
Host smart-29d9842b-6faa-49f6-9368-d9dd0fcd95bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650115148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.650115148
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2384130164
Short name T669
Test name
Test status
Simulation time 67422117 ps
CPU time 1.56 seconds
Started Mar 17 02:51:23 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 198144 kb
Host smart-3cde9554-b31a-4377-9c7d-2f14d70af050
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384130164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2384130164
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.416131045
Short name T546
Test name
Test status
Simulation time 97815578 ps
CPU time 1.34 seconds
Started Mar 17 02:51:25 PM PDT 24
Finished Mar 17 02:51:26 PM PDT 24
Peak memory 196392 kb
Host smart-8c0f7ab2-bb4a-4e0c-9185-011e4edd5b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416131045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.416131045
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3593119364
Short name T152
Test name
Test status
Simulation time 37271756 ps
CPU time 1.24 seconds
Started Mar 17 02:51:23 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 197016 kb
Host smart-6117df1f-bcc9-4f07-84bc-51036ebff1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593119364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3593119364
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.274985032
Short name T127
Test name
Test status
Simulation time 24053300 ps
CPU time 0.75 seconds
Started Mar 17 02:51:25 PM PDT 24
Finished Mar 17 02:51:26 PM PDT 24
Peak memory 194456 kb
Host smart-5c55c109-6e43-424c-a566-fa532c0f0f3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274985032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.274985032
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3938539691
Short name T231
Test name
Test status
Simulation time 193124245 ps
CPU time 2.3 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:24 PM PDT 24
Peak memory 197964 kb
Host smart-5762ec25-47fb-4876-b5d0-cc5c611f96c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938539691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3938539691
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3922193021
Short name T235
Test name
Test status
Simulation time 104304634 ps
CPU time 1.04 seconds
Started Mar 17 02:51:24 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 196264 kb
Host smart-50646eac-5a62-41b6-b625-aee6249ef4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922193021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3922193021
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.897990912
Short name T362
Test name
Test status
Simulation time 82134114 ps
CPU time 1.41 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:24 PM PDT 24
Peak memory 195740 kb
Host smart-947de5da-bfea-452a-a1a9-a80aa7c43f94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897990912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.897990912
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1343889836
Short name T263
Test name
Test status
Simulation time 4767639751 ps
CPU time 70.35 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:52:33 PM PDT 24
Peak memory 198164 kb
Host smart-b5839402-39cf-40ad-a799-32a34b4691e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343889836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1343889836
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.544706558
Short name T64
Test name
Test status
Simulation time 20225169570 ps
CPU time 584.98 seconds
Started Mar 17 02:51:24 PM PDT 24
Finished Mar 17 03:01:09 PM PDT 24
Peak memory 198296 kb
Host smart-306bd956-d419-4340-a9c0-da70e69e1bb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=544706558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.544706558
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2867525062
Short name T534
Test name
Test status
Simulation time 10503757 ps
CPU time 0.55 seconds
Started Mar 17 02:51:29 PM PDT 24
Finished Mar 17 02:51:30 PM PDT 24
Peak memory 194664 kb
Host smart-6771a20d-a3a3-485b-ac4b-353b94ead049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867525062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2867525062
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4232299035
Short name T571
Test name
Test status
Simulation time 20535992 ps
CPU time 0.66 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 194044 kb
Host smart-b1a89da3-5369-4274-b5bb-30de00592e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232299035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4232299035
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1792283473
Short name T535
Test name
Test status
Simulation time 855986290 ps
CPU time 14.49 seconds
Started Mar 17 02:51:26 PM PDT 24
Finished Mar 17 02:51:41 PM PDT 24
Peak memory 195468 kb
Host smart-37ffa6be-d682-422a-a6f8-9d26f9e7de50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792283473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1792283473
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2396996223
Short name T511
Test name
Test status
Simulation time 427200429 ps
CPU time 1.06 seconds
Started Mar 17 02:51:28 PM PDT 24
Finished Mar 17 02:51:29 PM PDT 24
Peak memory 196304 kb
Host smart-2d627898-2cf7-4f16-8756-d8f412268c75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396996223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2396996223
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2375189175
Short name T510
Test name
Test status
Simulation time 39611938 ps
CPU time 0.63 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 194292 kb
Host smart-b2c394d3-2cf7-47e3-a78d-7f3e189e0128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375189175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2375189175
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3631194993
Short name T373
Test name
Test status
Simulation time 19758286 ps
CPU time 0.92 seconds
Started Mar 17 02:51:24 PM PDT 24
Finished Mar 17 02:51:25 PM PDT 24
Peak memory 196300 kb
Host smart-53f620d3-9a9e-470b-9800-6558d72c3872
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631194993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3631194993
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.302195992
Short name T245
Test name
Test status
Simulation time 252331140 ps
CPU time 1.31 seconds
Started Mar 17 02:51:21 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 197536 kb
Host smart-ccebe5c4-af6f-4aee-b9be-6ab35010cedd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302195992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.302195992
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3106917513
Short name T343
Test name
Test status
Simulation time 33774481 ps
CPU time 0.94 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 196064 kb
Host smart-fea4e706-df5e-48aa-b9c2-935edfeafaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106917513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3106917513
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3579401363
Short name T522
Test name
Test status
Simulation time 50479927 ps
CPU time 0.73 seconds
Started Mar 17 02:51:23 PM PDT 24
Finished Mar 17 02:51:24 PM PDT 24
Peak memory 195512 kb
Host smart-a03ca641-ba7e-4caa-b02d-9fdef3f35cbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579401363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3579401363
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.169405016
Short name T112
Test name
Test status
Simulation time 3483972967 ps
CPU time 4.79 seconds
Started Mar 17 02:51:28 PM PDT 24
Finished Mar 17 02:51:33 PM PDT 24
Peak memory 198080 kb
Host smart-ebc3b9ad-0823-4e77-8938-10f1333b0bde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169405016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.169405016
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3342878944
Short name T154
Test name
Test status
Simulation time 74600765 ps
CPU time 1.08 seconds
Started Mar 17 02:51:22 PM PDT 24
Finished Mar 17 02:51:23 PM PDT 24
Peak memory 195796 kb
Host smart-1f54c98c-af40-441b-a2d7-f942f852e6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342878944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3342878944
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2495099458
Short name T354
Test name
Test status
Simulation time 159384949 ps
CPU time 0.89 seconds
Started Mar 17 02:51:23 PM PDT 24
Finished Mar 17 02:51:29 PM PDT 24
Peak memory 197184 kb
Host smart-bfbcb46a-43df-4745-ba43-0c7c1ea06a0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495099458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2495099458
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2799926219
Short name T147
Test name
Test status
Simulation time 952605300 ps
CPU time 24.51 seconds
Started Mar 17 02:51:28 PM PDT 24
Finished Mar 17 02:51:52 PM PDT 24
Peak memory 197904 kb
Host smart-25233ece-09ac-463f-9939-d54f3aba2b71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799926219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2799926219
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4239156239
Short name T429
Test name
Test status
Simulation time 37344506 ps
CPU time 0.58 seconds
Started Mar 17 02:51:29 PM PDT 24
Finished Mar 17 02:51:30 PM PDT 24
Peak memory 193576 kb
Host smart-3081b2aa-b48c-4606-a6fc-0e221b755db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239156239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4239156239
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3839277475
Short name T466
Test name
Test status
Simulation time 31642547 ps
CPU time 0.78 seconds
Started Mar 17 02:51:26 PM PDT 24
Finished Mar 17 02:51:27 PM PDT 24
Peak memory 195188 kb
Host smart-779a9069-b1a4-4619-a5a0-828c0b505b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839277475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3839277475
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2929779837
Short name T11
Test name
Test status
Simulation time 2010838419 ps
CPU time 16.57 seconds
Started Mar 17 02:51:29 PM PDT 24
Finished Mar 17 02:51:46 PM PDT 24
Peak memory 195736 kb
Host smart-9b9362e2-6119-445f-a90d-34cc5f8897b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929779837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2929779837
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2120392923
Short name T680
Test name
Test status
Simulation time 114498310 ps
CPU time 0.8 seconds
Started Mar 17 02:51:27 PM PDT 24
Finished Mar 17 02:51:28 PM PDT 24
Peak memory 194760 kb
Host smart-7a8f0188-8dac-4b31-b67a-b70f750fbd13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120392923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2120392923
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3255360067
Short name T503
Test name
Test status
Simulation time 638677278 ps
CPU time 1.49 seconds
Started Mar 17 02:51:27 PM PDT 24
Finished Mar 17 02:51:29 PM PDT 24
Peak memory 198024 kb
Host smart-0f2782c9-4284-4ee5-9f0c-7828da62c5e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255360067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3255360067
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2713372497
Short name T552
Test name
Test status
Simulation time 91905200 ps
CPU time 3.55 seconds
Started Mar 17 02:51:27 PM PDT 24
Finished Mar 17 02:51:31 PM PDT 24
Peak memory 198052 kb
Host smart-ac540ac8-1c80-4019-807e-983378e33d99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713372497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2713372497
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.4139137823
Short name T29
Test name
Test status
Simulation time 85873334 ps
CPU time 1.74 seconds
Started Mar 17 02:51:32 PM PDT 24
Finished Mar 17 02:51:34 PM PDT 24
Peak memory 195768 kb
Host smart-e9624c3b-86ed-473a-87dc-43d2822e2477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139137823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
4139137823
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1682602041
Short name T121
Test name
Test status
Simulation time 74375895 ps
CPU time 0.92 seconds
Started Mar 17 02:51:34 PM PDT 24
Finished Mar 17 02:51:35 PM PDT 24
Peak memory 196668 kb
Host smart-10e2e30f-8bdc-4f04-967f-2079a8dc968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682602041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1682602041
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1634490404
Short name T456
Test name
Test status
Simulation time 87310397 ps
CPU time 1.05 seconds
Started Mar 17 02:51:29 PM PDT 24
Finished Mar 17 02:51:30 PM PDT 24
Peak memory 195804 kb
Host smart-69450d15-4963-4cd3-965c-7db28cdf7367
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634490404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1634490404
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2344725946
Short name T526
Test name
Test status
Simulation time 69852974 ps
CPU time 3.25 seconds
Started Mar 17 02:51:26 PM PDT 24
Finished Mar 17 02:51:29 PM PDT 24
Peak memory 197988 kb
Host smart-99b59734-bdaa-4ea4-b519-98a07959554b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344725946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2344725946
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2266985160
Short name T203
Test name
Test status
Simulation time 83064617 ps
CPU time 0.82 seconds
Started Mar 17 02:51:25 PM PDT 24
Finished Mar 17 02:51:26 PM PDT 24
Peak memory 195900 kb
Host smart-c6258270-abe5-450c-934a-bff969335023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266985160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2266985160
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2617364818
Short name T327
Test name
Test status
Simulation time 273444520 ps
CPU time 1.21 seconds
Started Mar 17 02:51:28 PM PDT 24
Finished Mar 17 02:51:29 PM PDT 24
Peak memory 196432 kb
Host smart-7b09fac7-cda5-4043-8cfa-ecd5ae2c78ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617364818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2617364818
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1228905642
Short name T471
Test name
Test status
Simulation time 8334430612 ps
CPU time 57.12 seconds
Started Mar 17 02:51:29 PM PDT 24
Finished Mar 17 02:52:26 PM PDT 24
Peak memory 198200 kb
Host smart-40a73be8-adeb-486a-b33e-f12cff0f9a38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228905642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1228905642
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2751418264
Short name T549
Test name
Test status
Simulation time 58910408450 ps
CPU time 1195.08 seconds
Started Mar 17 02:51:26 PM PDT 24
Finished Mar 17 03:11:21 PM PDT 24
Peak memory 198248 kb
Host smart-fc908b15-ed97-4bf2-a57e-740adfac2e21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2751418264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2751418264
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3672281834
Short name T488
Test name
Test status
Simulation time 12340388 ps
CPU time 0.59 seconds
Started Mar 17 02:51:44 PM PDT 24
Finished Mar 17 02:51:46 PM PDT 24
Peak memory 194588 kb
Host smart-5e1d5b7e-2575-43c7-b40e-ec05062ffe44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672281834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3672281834
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1109170902
Short name T516
Test name
Test status
Simulation time 85025291 ps
CPU time 0.81 seconds
Started Mar 17 02:51:41 PM PDT 24
Finished Mar 17 02:51:42 PM PDT 24
Peak memory 195612 kb
Host smart-73dd589a-d4cd-4c06-a99c-34ad9a6348ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109170902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1109170902
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2272887592
Short name T286
Test name
Test status
Simulation time 983622211 ps
CPU time 25.04 seconds
Started Mar 17 02:51:36 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 196472 kb
Host smart-a7e2f13c-6493-40ce-b543-ca229b873e2d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272887592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2272887592
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.257907666
Short name T682
Test name
Test status
Simulation time 142552927 ps
CPU time 0.75 seconds
Started Mar 17 02:51:41 PM PDT 24
Finished Mar 17 02:51:42 PM PDT 24
Peak memory 196624 kb
Host smart-adb9d91a-6a5a-4c4a-b7f2-229b6a3005c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257907666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.257907666
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1970561813
Short name T56
Test name
Test status
Simulation time 98521891 ps
CPU time 0.96 seconds
Started Mar 17 02:51:39 PM PDT 24
Finished Mar 17 02:51:40 PM PDT 24
Peak memory 197392 kb
Host smart-30a0236c-8e0e-4831-9dee-f31bc24526a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970561813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1970561813
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.460527684
Short name T651
Test name
Test status
Simulation time 49190363 ps
CPU time 1.88 seconds
Started Mar 17 02:51:38 PM PDT 24
Finished Mar 17 02:51:40 PM PDT 24
Peak memory 198052 kb
Host smart-b0ef3bd9-883c-43dc-bb45-4d8d11882adc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460527684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.460527684
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.63092137
Short name T313
Test name
Test status
Simulation time 132169367 ps
CPU time 1.46 seconds
Started Mar 17 02:51:37 PM PDT 24
Finished Mar 17 02:51:39 PM PDT 24
Peak memory 196068 kb
Host smart-634ce325-95c1-4489-a99f-b61b45b944db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63092137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.63092137
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3627970124
Short name T366
Test name
Test status
Simulation time 24048992 ps
CPU time 0.94 seconds
Started Mar 17 02:51:26 PM PDT 24
Finished Mar 17 02:51:27 PM PDT 24
Peak memory 196608 kb
Host smart-84f51679-5544-48d6-91a2-66916a87045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627970124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3627970124
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.425670213
Short name T642
Test name
Test status
Simulation time 118407082 ps
CPU time 1.13 seconds
Started Mar 17 02:51:26 PM PDT 24
Finished Mar 17 02:51:28 PM PDT 24
Peak memory 196592 kb
Host smart-bc9a7a6b-26c9-4645-9155-bc93c084d5c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425670213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.425670213
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1007934188
Short name T269
Test name
Test status
Simulation time 617844052 ps
CPU time 2.74 seconds
Started Mar 17 02:51:31 PM PDT 24
Finished Mar 17 02:51:34 PM PDT 24
Peak memory 197096 kb
Host smart-9fd0e69a-cab6-4861-9dd3-aa08874d373f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007934188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1007934188
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.649435650
Short name T206
Test name
Test status
Simulation time 61970084 ps
CPU time 1.13 seconds
Started Mar 17 02:51:28 PM PDT 24
Finished Mar 17 02:51:30 PM PDT 24
Peak memory 195576 kb
Host smart-a3efe56e-08a0-4c52-9c29-e0fb4ad55871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649435650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.649435650
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1533033144
Short name T670
Test name
Test status
Simulation time 70014785 ps
CPU time 1.41 seconds
Started Mar 17 02:51:26 PM PDT 24
Finished Mar 17 02:51:28 PM PDT 24
Peak memory 198064 kb
Host smart-d4f62933-9a56-46aa-8c62-0bf14a05ed0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533033144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1533033144
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.68503841
Short name T348
Test name
Test status
Simulation time 17291076151 ps
CPU time 210.83 seconds
Started Mar 17 02:51:31 PM PDT 24
Finished Mar 17 02:55:02 PM PDT 24
Peak memory 198108 kb
Host smart-db687bfb-7a25-4b97-b1e1-06cea45fb176
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68503841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpi
o_stress_all.68503841
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1102023192
Short name T872
Test name
Test status
Simulation time 37219071 ps
CPU time 0.94 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:41 PM PDT 24
Peak memory 192336 kb
Host smart-dd8ebe2e-b996-4f3e-972b-9174e48c2c99
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1102023192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1102023192
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1266706906
Short name T939
Test name
Test status
Simulation time 94590843 ps
CPU time 1.42 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:46:39 PM PDT 24
Peak memory 192348 kb
Host smart-b9ac42c9-1c12-4776-85c8-ee97d4656895
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266706906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1266706906
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2835839592
Short name T885
Test name
Test status
Simulation time 28618963 ps
CPU time 0.82 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192140 kb
Host smart-0cd12959-527e-4637-b632-b1e6effacb63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2835839592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2835839592
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865098376
Short name T929
Test name
Test status
Simulation time 47188950 ps
CPU time 0.89 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 192108 kb
Host smart-d769732a-2533-4077-afa3-c6806c28681a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865098376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3865098376
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1662736753
Short name T922
Test name
Test status
Simulation time 203874870 ps
CPU time 1.38 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 192264 kb
Host smart-27706b32-579d-4da1-8b39-07d70e0c3233
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1662736753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1662736753
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3592934793
Short name T888
Test name
Test status
Simulation time 119252878 ps
CPU time 0.81 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 192164 kb
Host smart-13a21215-8e4f-4c2e-9c13-9a05021be530
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592934793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3592934793
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.85018539
Short name T934
Test name
Test status
Simulation time 50080628 ps
CPU time 0.99 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 192344 kb
Host smart-687e79ec-14e9-4f13-84d2-4f17148e289c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=85018539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.85018539
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1056005070
Short name T867
Test name
Test status
Simulation time 118175452 ps
CPU time 0.8 seconds
Started Mar 17 01:46:49 PM PDT 24
Finished Mar 17 01:46:50 PM PDT 24
Peak memory 192164 kb
Host smart-79eb2266-3e0b-4e21-a2f7-f1784bb52995
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056005070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1056005070
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2145542954
Short name T906
Test name
Test status
Simulation time 41457845 ps
CPU time 0.84 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:46:36 PM PDT 24
Peak memory 192108 kb
Host smart-621c0ae4-22d8-4508-b53c-b8b93e51ad0d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2145542954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2145542954
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.457499275
Short name T937
Test name
Test status
Simulation time 89979110 ps
CPU time 1.01 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 196952 kb
Host smart-24b5e133-b9a5-487a-b190-034b81c92418
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457499275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.457499275
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4123793093
Short name T932
Test name
Test status
Simulation time 33684752 ps
CPU time 0.94 seconds
Started Mar 17 01:46:48 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 192340 kb
Host smart-84d9816b-c62a-454e-80dd-84e4a90d3401
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4123793093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.4123793093
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.479854972
Short name T846
Test name
Test status
Simulation time 333630557 ps
CPU time 1.42 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 192352 kb
Host smart-d5e18cba-3955-43c9-88b3-61d006615ddb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479854972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.479854972
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3166346797
Short name T933
Test name
Test status
Simulation time 113355498 ps
CPU time 0.76 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:46:38 PM PDT 24
Peak memory 192068 kb
Host smart-fad5a9b3-36ee-49a8-a7da-7facf79847bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3166346797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3166346797
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.379937000
Short name T864
Test name
Test status
Simulation time 96841945 ps
CPU time 1.39 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:46:37 PM PDT 24
Peak memory 192340 kb
Host smart-09bf5890-f26a-48d7-9a30-8870af9bc1d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379937000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.379937000
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2989025004
Short name T892
Test name
Test status
Simulation time 312171440 ps
CPU time 1 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 192304 kb
Host smart-e79fee75-a5b6-40b1-b77f-1ef34228bf9b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2989025004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2989025004
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712569138
Short name T841
Test name
Test status
Simulation time 85761287 ps
CPU time 1.4 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 192300 kb
Host smart-25803814-7fc3-4aa4-9e8b-d2fbd1e59e9a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712569138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2712569138
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4029204217
Short name T927
Test name
Test status
Simulation time 94836561 ps
CPU time 0.94 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 198472 kb
Host smart-bec8e9be-e9e6-41ad-a4e8-49b7c19aa1ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4029204217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.4029204217
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.210572962
Short name T863
Test name
Test status
Simulation time 27169619 ps
CPU time 0.82 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 192172 kb
Host smart-84b2c6f2-0d0f-49ba-bc5b-42a288e0289d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210572962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.210572962
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2543376533
Short name T869
Test name
Test status
Simulation time 271859147 ps
CPU time 1.4 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:46:39 PM PDT 24
Peak memory 192272 kb
Host smart-e8421eb7-1996-41a0-9eef-05b9dc60b126
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2543376533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2543376533
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999119364
Short name T897
Test name
Test status
Simulation time 32934862 ps
CPU time 1.12 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 192288 kb
Host smart-c29878e9-8d47-4355-a8b6-7d82d0734597
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999119364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2999119364
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3808334473
Short name T851
Test name
Test status
Simulation time 165854670 ps
CPU time 1 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 192288 kb
Host smart-df8b788a-76ec-4368-8630-7271cf087d83
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3808334473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3808334473
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3445006735
Short name T910
Test name
Test status
Simulation time 44976885 ps
CPU time 0.92 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:46:53 PM PDT 24
Peak memory 192164 kb
Host smart-400a74f2-2fad-497e-be6b-2241c864ade6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445006735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3445006735
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2343158710
Short name T913
Test name
Test status
Simulation time 166089771 ps
CPU time 1.33 seconds
Started Mar 17 01:46:48 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 198644 kb
Host smart-c0d11f4b-280b-46db-bcb0-fad4c00508cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2343158710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2343158710
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.474229347
Short name T853
Test name
Test status
Simulation time 376649857 ps
CPU time 1.5 seconds
Started Mar 17 01:46:48 PM PDT 24
Finished Mar 17 01:46:50 PM PDT 24
Peak memory 198012 kb
Host smart-43fd94dc-1cfd-4e2e-b3c2-ef0e6608f874
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474229347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.474229347
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1803302497
Short name T936
Test name
Test status
Simulation time 694388407 ps
CPU time 1.3 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 192376 kb
Host smart-0751a74f-65d7-4c44-8dee-c8464e32cdf4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1803302497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1803302497
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2365826588
Short name T891
Test name
Test status
Simulation time 158495110 ps
CPU time 1.17 seconds
Started Mar 17 01:46:54 PM PDT 24
Finished Mar 17 01:46:55 PM PDT 24
Peak memory 198584 kb
Host smart-4ffbb0b6-a869-47f0-b3af-74ec8734036e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365826588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2365826588
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1901837160
Short name T924
Test name
Test status
Simulation time 39971491 ps
CPU time 1.11 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 192196 kb
Host smart-559468f9-7fe6-4446-b041-7050a01beb4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1901837160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1901837160
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1188645552
Short name T917
Test name
Test status
Simulation time 38354444 ps
CPU time 1.18 seconds
Started Mar 17 01:46:42 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 198656 kb
Host smart-476e20e4-0ec8-4cdd-9e72-0ab2fa171703
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188645552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1188645552
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1000150015
Short name T854
Test name
Test status
Simulation time 136932218 ps
CPU time 0.95 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 192104 kb
Host smart-0a094fc1-4b09-477c-9340-e123977edc55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1000150015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1000150015
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3577883941
Short name T849
Test name
Test status
Simulation time 33717635 ps
CPU time 0.87 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:42 PM PDT 24
Peak memory 192152 kb
Host smart-07566e09-ea1b-4de7-9015-6c3749458ac6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577883941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3577883941
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.289424260
Short name T912
Test name
Test status
Simulation time 223390006 ps
CPU time 1.05 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 198608 kb
Host smart-5ce979d4-1641-423f-9e27-cf92148aef8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=289424260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.289424260
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3298554415
Short name T914
Test name
Test status
Simulation time 77955370 ps
CPU time 0.82 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 192376 kb
Host smart-0366cf00-fa20-45b9-8ee3-fee49adbb827
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298554415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3298554415
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3706903283
Short name T925
Test name
Test status
Simulation time 111148952 ps
CPU time 1.55 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 192296 kb
Host smart-e09cccea-8b47-4846-832a-5baf1c1dfe56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3706903283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3706903283
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224886154
Short name T920
Test name
Test status
Simulation time 56264594 ps
CPU time 0.99 seconds
Started Mar 17 01:46:42 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 192224 kb
Host smart-c6039271-9add-4792-8287-47208e147604
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224886154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4224886154
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1108268043
Short name T883
Test name
Test status
Simulation time 136045255 ps
CPU time 0.97 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:46:36 PM PDT 24
Peak memory 198872 kb
Host smart-463840cc-60b4-4c1d-aec4-66fc2ea87f1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1108268043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1108268043
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2258996908
Short name T873
Test name
Test status
Simulation time 63412516 ps
CPU time 1.09 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192288 kb
Host smart-cd2b6de3-da09-48aa-a970-a70cd41c15ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258996908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2258996908
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.11315512
Short name T847
Test name
Test status
Simulation time 51148044 ps
CPU time 0.95 seconds
Started Mar 17 01:46:49 PM PDT 24
Finished Mar 17 01:46:50 PM PDT 24
Peak memory 197660 kb
Host smart-11061bc5-7f1e-4048-86c8-f5c183e565c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=11315512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.11315512
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4167347132
Short name T874
Test name
Test status
Simulation time 47372047 ps
CPU time 0.99 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 196840 kb
Host smart-190a4f00-ebff-42b0-80ea-9b3605ea1085
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167347132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4167347132
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3373475987
Short name T882
Test name
Test status
Simulation time 63664384 ps
CPU time 1.21 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 197028 kb
Host smart-14251237-53b8-4f36-88a5-70473a637c69
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3373475987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3373475987
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3391588821
Short name T916
Test name
Test status
Simulation time 313373938 ps
CPU time 1.45 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192300 kb
Host smart-3c218e8c-f124-4514-b891-397667031d6e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391588821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3391588821
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2177664893
Short name T844
Test name
Test status
Simulation time 79886809 ps
CPU time 1.25 seconds
Started Mar 17 01:46:34 PM PDT 24
Finished Mar 17 01:46:35 PM PDT 24
Peak memory 192284 kb
Host smart-e94c8b7f-e337-4839-9191-6aa36f444947
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2177664893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2177664893
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1207693998
Short name T876
Test name
Test status
Simulation time 93406508 ps
CPU time 1.29 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192280 kb
Host smart-941c8ac4-4a77-492b-9e17-287ae8bd5e1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207693998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1207693998
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2274248831
Short name T896
Test name
Test status
Simulation time 40842666 ps
CPU time 0.92 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:38 PM PDT 24
Peak memory 192164 kb
Host smart-a2b78a1c-4253-4a40-8616-8fc7ba1d0a35
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2274248831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2274248831
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3591827986
Short name T930
Test name
Test status
Simulation time 55457029 ps
CPU time 0.99 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:38 PM PDT 24
Peak memory 192200 kb
Host smart-82a665db-9a06-4a8e-9462-823bc528c05b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591827986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3591827986
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.117900747
Short name T858
Test name
Test status
Simulation time 533481384 ps
CPU time 0.85 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 196684 kb
Host smart-3c29d165-4174-48ec-9381-9c2fbb52a381
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=117900747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.117900747
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1459239988
Short name T895
Test name
Test status
Simulation time 63912221 ps
CPU time 1.14 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192300 kb
Host smart-2bdc84a2-68ca-4c7f-9b5d-ada5551ae8ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459239988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1459239988
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.428344255
Short name T877
Test name
Test status
Simulation time 192322392 ps
CPU time 1.04 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:37 PM PDT 24
Peak memory 192408 kb
Host smart-6a781cc8-ec7b-43b9-9470-1b66121bfb9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=428344255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.428344255
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3353087682
Short name T904
Test name
Test status
Simulation time 34379113 ps
CPU time 0.86 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 192144 kb
Host smart-36152cd7-9a65-40c4-ac22-a8efb7240d6e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353087682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3353087682
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.282386592
Short name T878
Test name
Test status
Simulation time 62097350 ps
CPU time 1.25 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 192304 kb
Host smart-a133d32b-1a9e-4f6e-ae99-c03f017d9f5d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=282386592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.282386592
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1148267337
Short name T915
Test name
Test status
Simulation time 367088569 ps
CPU time 1.15 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 192220 kb
Host smart-cdd1f0c2-6edd-41bb-823e-baf412712bd9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148267337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1148267337
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.349313028
Short name T862
Test name
Test status
Simulation time 56471874 ps
CPU time 0.96 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:46:53 PM PDT 24
Peak memory 198464 kb
Host smart-0ea0e363-722b-405c-b312-c0ca23569cab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=349313028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.349313028
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1647610941
Short name T850
Test name
Test status
Simulation time 42785077 ps
CPU time 1.11 seconds
Started Mar 17 01:46:42 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192364 kb
Host smart-31ce89f5-300a-45b0-b36c-b281df60c188
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647610941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1647610941
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3608630351
Short name T857
Test name
Test status
Simulation time 261416074 ps
CPU time 1.15 seconds
Started Mar 17 01:46:48 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 196948 kb
Host smart-1039af24-07db-4839-9982-acd7c42082f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3608630351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3608630351
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.765117152
Short name T907
Test name
Test status
Simulation time 192394237 ps
CPU time 1.23 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 192264 kb
Host smart-a92fe1c4-983d-4b3b-9afa-64b41031a64b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765117152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.765117152
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3054072130
Short name T879
Test name
Test status
Simulation time 62960779 ps
CPU time 0.75 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192064 kb
Host smart-07b5f2d6-e6eb-4030-8845-243a342d6479
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3054072130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3054072130
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2214206074
Short name T905
Test name
Test status
Simulation time 30028362 ps
CPU time 0.93 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 192136 kb
Host smart-11272086-2095-4891-9126-ca2991b8c48f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214206074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2214206074
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.579109273
Short name T880
Test name
Test status
Simulation time 48017281 ps
CPU time 0.99 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 192336 kb
Host smart-9b78986a-aaa4-4d92-809f-79ebff16ec5a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=579109273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.579109273
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1777611854
Short name T871
Test name
Test status
Simulation time 307698637 ps
CPU time 1.41 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 192284 kb
Host smart-62b4a9a2-10ca-4516-bbd6-f75e2252bf4d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777611854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1777611854
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1276326640
Short name T865
Test name
Test status
Simulation time 252884413 ps
CPU time 1.37 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:42 PM PDT 24
Peak memory 192228 kb
Host smart-ecae3534-0ec8-4e39-bedf-a45f0ef9aebb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1276326640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1276326640
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3733111380
Short name T899
Test name
Test status
Simulation time 58163982 ps
CPU time 0.93 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:42 PM PDT 24
Peak memory 197096 kb
Host smart-fcd741a1-1882-42f0-acdf-2ff20dbf97f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733111380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3733111380
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1757923280
Short name T902
Test name
Test status
Simulation time 208011511 ps
CPU time 1.1 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:46:51 PM PDT 24
Peak memory 192368 kb
Host smart-45c606e3-a4be-4951-8192-38e8a94cf48c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1757923280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1757923280
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1991790570
Short name T894
Test name
Test status
Simulation time 57205053 ps
CPU time 1.12 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:46:51 PM PDT 24
Peak memory 192244 kb
Host smart-c5c32d5f-32af-4e12-8d31-b4a815594f9e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991790570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1991790570
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1630689847
Short name T908
Test name
Test status
Simulation time 145095080 ps
CPU time 0.86 seconds
Started Mar 17 01:46:42 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 192100 kb
Host smart-4fbbf20c-b774-40ee-ac68-69c8c3ef9588
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1630689847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1630689847
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.281258299
Short name T911
Test name
Test status
Simulation time 165761073 ps
CPU time 1.23 seconds
Started Mar 17 01:46:56 PM PDT 24
Finished Mar 17 01:46:58 PM PDT 24
Peak memory 192328 kb
Host smart-a6b8a335-63a4-4c03-b69b-37f21dc35270
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281258299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.281258299
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.57441798
Short name T921
Test name
Test status
Simulation time 37622131 ps
CPU time 1.12 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:46:51 PM PDT 24
Peak memory 192344 kb
Host smart-38fcb59f-7bbc-4198-b7b2-04d3c492d130
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=57441798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.57441798
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4165531435
Short name T940
Test name
Test status
Simulation time 162485429 ps
CPU time 1.21 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 192304 kb
Host smart-c86f7373-85fd-418a-b480-98f24a505e32
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165531435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4165531435
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2680423405
Short name T935
Test name
Test status
Simulation time 54821674 ps
CPU time 1.05 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 198528 kb
Host smart-e53c3261-b997-4d96-b319-5ba5dd123128
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2680423405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2680423405
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.259387173
Short name T860
Test name
Test status
Simulation time 211288302 ps
CPU time 0.89 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 192232 kb
Host smart-6fe5a228-286d-4ddb-b888-5590287e532b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259387173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.259387173
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2913702004
Short name T889
Test name
Test status
Simulation time 39135235 ps
CPU time 1.09 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:46:51 PM PDT 24
Peak memory 192284 kb
Host smart-07e92381-0f33-4e69-a852-c67b28324851
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2913702004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2913702004
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3276347818
Short name T852
Test name
Test status
Simulation time 55665528 ps
CPU time 0.95 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192292 kb
Host smart-c4c114ec-e2c6-454c-bf6b-79d4368a0923
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276347818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3276347818
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3202735054
Short name T855
Test name
Test status
Simulation time 78853832 ps
CPU time 1.08 seconds
Started Mar 17 01:46:52 PM PDT 24
Finished Mar 17 01:46:54 PM PDT 24
Peak memory 198604 kb
Host smart-10838574-5af4-4909-8d63-f212b28af322
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3202735054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3202735054
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.483731478
Short name T866
Test name
Test status
Simulation time 77668194 ps
CPU time 0.89 seconds
Started Mar 17 01:46:55 PM PDT 24
Finished Mar 17 01:46:56 PM PDT 24
Peak memory 192152 kb
Host smart-c154e6b4-f468-449f-bcdf-edf1ecdce987
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483731478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.483731478
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1555746023
Short name T881
Test name
Test status
Simulation time 81554300 ps
CPU time 1.24 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192220 kb
Host smart-167101eb-560f-44c0-8ee2-3a46ec97c5f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1555746023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1555746023
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.837950670
Short name T870
Test name
Test status
Simulation time 449347581 ps
CPU time 0.94 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 192200 kb
Host smart-8735c0a2-9114-42c6-856c-6e780a9389ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837950670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.837950670
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1515714837
Short name T856
Test name
Test status
Simulation time 259385823 ps
CPU time 0.75 seconds
Started Mar 17 01:46:54 PM PDT 24
Finished Mar 17 01:46:55 PM PDT 24
Peak memory 195612 kb
Host smart-843399f4-419c-4997-81c9-8b4f838697bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1515714837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1515714837
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513593451
Short name T868
Test name
Test status
Simulation time 467327045 ps
CPU time 1.15 seconds
Started Mar 17 01:46:49 PM PDT 24
Finished Mar 17 01:46:50 PM PDT 24
Peak memory 192324 kb
Host smart-762a0a2d-55de-4e6b-8afd-ac0d67c35fa5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513593451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.513593451
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3669978859
Short name T886
Test name
Test status
Simulation time 520000373 ps
CPU time 1.01 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:42 PM PDT 24
Peak memory 192232 kb
Host smart-70ef11a8-bbde-402f-9879-be7d69ff83af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3669978859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3669978859
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4212503151
Short name T928
Test name
Test status
Simulation time 135606130 ps
CPU time 0.88 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:46:51 PM PDT 24
Peak memory 192080 kb
Host smart-ec3ae3af-a7ac-484d-a7b4-689051fbcfa8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212503151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4212503151
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1438592284
Short name T859
Test name
Test status
Simulation time 166471551 ps
CPU time 0.98 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:46:53 PM PDT 24
Peak memory 192172 kb
Host smart-4dce40ef-3a02-492e-a983-f46b3c625ba3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1438592284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1438592284
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1028949219
Short name T884
Test name
Test status
Simulation time 1201647228 ps
CPU time 1.29 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:40 PM PDT 24
Peak memory 192272 kb
Host smart-a52111e2-46f1-4bd7-80b1-6bf79cf79d4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028949219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1028949219
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2270196443
Short name T861
Test name
Test status
Simulation time 41687628 ps
CPU time 0.86 seconds
Started Mar 17 01:46:54 PM PDT 24
Finished Mar 17 01:46:56 PM PDT 24
Peak memory 192176 kb
Host smart-ae36dd75-9787-4a16-b19c-5a856670bc87
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2270196443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2270196443
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3922486945
Short name T909
Test name
Test status
Simulation time 78836592 ps
CPU time 1.08 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192288 kb
Host smart-34a9e648-98c0-44dc-90bd-87306180ee89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922486945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3922486945
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2069736617
Short name T900
Test name
Test status
Simulation time 69457247 ps
CPU time 1.21 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 192332 kb
Host smart-8a97bf58-9ea6-4e32-ae2a-46ab4d0ba747
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2069736617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2069736617
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1793623649
Short name T898
Test name
Test status
Simulation time 95082767 ps
CPU time 1.02 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:46:51 PM PDT 24
Peak memory 192324 kb
Host smart-c6010fd8-6ae2-461e-927e-ce289a82d403
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793623649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1793623649
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3851025096
Short name T919
Test name
Test status
Simulation time 321590798 ps
CPU time 0.99 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 192312 kb
Host smart-f50df82a-50ef-400e-9ca6-88d6c503d179
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3851025096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3851025096
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2186060384
Short name T893
Test name
Test status
Simulation time 336283682 ps
CPU time 1.41 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 192388 kb
Host smart-05934278-dbf4-498e-ba34-a90300a41480
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186060384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2186060384
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1149794598
Short name T931
Test name
Test status
Simulation time 223041018 ps
CPU time 1.52 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 198656 kb
Host smart-2b17297f-f173-405b-99bf-984119705eed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1149794598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1149794598
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3456075294
Short name T875
Test name
Test status
Simulation time 107955980 ps
CPU time 0.86 seconds
Started Mar 17 01:46:56 PM PDT 24
Finished Mar 17 01:46:57 PM PDT 24
Peak memory 192136 kb
Host smart-92559b88-d3e7-4fb1-9602-1d37c8856315
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456075294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3456075294
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2739571498
Short name T887
Test name
Test status
Simulation time 371633615 ps
CPU time 0.92 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 197896 kb
Host smart-48255bca-a666-4bbb-ae91-c6ef11f43baa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2739571498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2739571498
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2372544035
Short name T938
Test name
Test status
Simulation time 107461558 ps
CPU time 1.15 seconds
Started Mar 17 01:46:52 PM PDT 24
Finished Mar 17 01:46:55 PM PDT 24
Peak memory 192312 kb
Host smart-dcbc4743-6609-41d7-ad64-3e71f6586ec5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372544035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2372544035
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1565983236
Short name T903
Test name
Test status
Simulation time 57260117 ps
CPU time 1.14 seconds
Started Mar 17 01:46:49 PM PDT 24
Finished Mar 17 01:46:50 PM PDT 24
Peak memory 192344 kb
Host smart-eb81de38-fe7f-4d48-997a-de210e282996
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1565983236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1565983236
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2597610203
Short name T848
Test name
Test status
Simulation time 146634815 ps
CPU time 1.31 seconds
Started Mar 17 01:46:42 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 198640 kb
Host smart-d4b6f2c0-f02e-4e0c-a2fd-8d712f9ae0b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597610203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2597610203
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2949151321
Short name T923
Test name
Test status
Simulation time 25798019 ps
CPU time 0.79 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 192172 kb
Host smart-1a2aef63-3a66-4670-a7f6-636001f668f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2949151321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2949151321
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4214567694
Short name T926
Test name
Test status
Simulation time 718550196 ps
CPU time 1.42 seconds
Started Mar 17 01:46:42 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 198656 kb
Host smart-176527ed-e315-45e9-831f-0fe432e838df
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214567694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4214567694
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4118531047
Short name T918
Test name
Test status
Simulation time 275587869 ps
CPU time 0.92 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 192064 kb
Host smart-2200328e-5447-4257-8c9d-4df71728c8ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4118531047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.4118531047
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3917084901
Short name T842
Test name
Test status
Simulation time 92868154 ps
CPU time 1.3 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 192272 kb
Host smart-c27dcece-d7db-495d-9fe7-82b0d5e82bcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917084901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3917084901
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.750721020
Short name T890
Test name
Test status
Simulation time 44512664 ps
CPU time 1.34 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 198668 kb
Host smart-28df165c-ae07-4003-9d7e-08d5df21a56b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=750721020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.750721020
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.869084143
Short name T843
Test name
Test status
Simulation time 54072042 ps
CPU time 1.12 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 198564 kb
Host smart-4c9df4ef-e3cf-48eb-9628-2c1d29eefc08
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869084143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.869084143
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.529257029
Short name T845
Test name
Test status
Simulation time 207002414 ps
CPU time 1.52 seconds
Started Mar 17 01:46:42 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 192284 kb
Host smart-0b48716c-52f5-467f-9727-a2d74497d69c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=529257029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.529257029
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1905864889
Short name T901
Test name
Test status
Simulation time 45744363 ps
CPU time 1.2 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:40 PM PDT 24
Peak memory 192388 kb
Host smart-18ff2d14-dd7e-47c3-a875-d417af34ae3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905864889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1905864889
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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