Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 36 0 36 100.00
Crosses 128 0 128 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 32 0 32 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 128 0 128 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 32 0 32 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 3279765 1 T25 55 T26 1 T27 25
all_pins[1] 3279765 1 T25 55 T26 1 T27 25
all_pins[2] 3279765 1 T25 55 T26 1 T27 25
all_pins[3] 3279765 1 T25 55 T26 1 T27 25
all_pins[4] 3279765 1 T25 55 T26 1 T27 25
all_pins[5] 3279765 1 T25 55 T26 1 T27 25
all_pins[6] 3279765 1 T25 55 T26 1 T27 25
all_pins[7] 3279765 1 T25 55 T26 1 T27 25
all_pins[8] 3279765 1 T25 55 T26 1 T27 25
all_pins[9] 3279765 1 T25 55 T26 1 T27 25
all_pins[10] 3279765 1 T25 55 T26 1 T27 25
all_pins[11] 3279765 1 T25 55 T26 1 T27 25
all_pins[12] 3279765 1 T25 55 T26 1 T27 25
all_pins[13] 3279765 1 T25 55 T26 1 T27 25
all_pins[14] 3279765 1 T25 55 T26 1 T27 25
all_pins[15] 3279765 1 T25 55 T26 1 T27 25
all_pins[16] 3279765 1 T25 55 T26 1 T27 25
all_pins[17] 3279765 1 T25 55 T26 1 T27 25
all_pins[18] 3279765 1 T25 55 T26 1 T27 25
all_pins[19] 3279765 1 T25 55 T26 1 T27 25
all_pins[20] 3279765 1 T25 55 T26 1 T27 25
all_pins[21] 3279765 1 T25 55 T26 1 T27 25
all_pins[22] 3279765 1 T25 55 T26 1 T27 25
all_pins[23] 3279765 1 T25 55 T26 1 T27 25
all_pins[24] 3279765 1 T25 55 T26 1 T27 25
all_pins[25] 3279765 1 T25 55 T26 1 T27 25
all_pins[26] 3279765 1 T25 55 T26 1 T27 25
all_pins[27] 3279765 1 T25 55 T26 1 T27 25
all_pins[28] 3279765 1 T25 55 T26 1 T27 25
all_pins[29] 3279765 1 T25 55 T26 1 T27 25
all_pins[30] 3279765 1 T25 55 T26 1 T27 25
all_pins[31] 3279765 1 T25 55 T26 1 T27 25



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 65186221 1 T25 913 T26 32 T27 760
values[0x1] 39766259 1 T25 847 T27 40 T1 10105
transitions[0x0=>0x1] 23822199 1 T25 434 T27 31 T1 6107
transitions[0x1=>0x0] 23822058 1 T25 434 T27 31 T1 6106



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 2034768 1 T25 27 T26 1 T27 24
all_pins[0] values[0x1] 1244997 1 T25 28 T27 1 T1 320
all_pins[0] transitions[0x0=>0x1] 772180 1 T25 17 T27 1 T1 221
all_pins[0] transitions[0x1=>0x0] 768815 1 T25 13 T1 203 T11 16
all_pins[1] values[0x0] 2033451 1 T25 26 T26 1 T27 25
all_pins[1] values[0x1] 1246314 1 T25 29 T1 369 T11 31
all_pins[1] transitions[0x0=>0x1] 743464 1 T25 14 T1 214 T11 17
all_pins[1] transitions[0x1=>0x0] 742147 1 T25 13 T27 1 T1 165
all_pins[2] values[0x0] 2038505 1 T25 30 T26 1 T27 21
all_pins[2] values[0x1] 1241260 1 T25 25 T27 4 T1 353
all_pins[2] transitions[0x0=>0x1] 740576 1 T25 11 T27 4 T1 193
all_pins[2] transitions[0x1=>0x0] 745630 1 T25 15 T1 209 T11 12
all_pins[3] values[0x0] 2036883 1 T25 27 T26 1 T27 24
all_pins[3] values[0x1] 1242882 1 T25 28 T27 1 T1 340
all_pins[3] transitions[0x0=>0x1] 746553 1 T25 15 T27 1 T1 178
all_pins[3] transitions[0x1=>0x0] 744931 1 T25 12 T27 4 T1 191
all_pins[4] values[0x0] 2039696 1 T25 33 T26 1 T27 25
all_pins[4] values[0x1] 1240069 1 T25 22 T1 420 T11 47
all_pins[4] transitions[0x0=>0x1] 741927 1 T25 12 T1 251 T11 19
all_pins[4] transitions[0x1=>0x0] 744740 1 T25 18 T27 1 T1 171
all_pins[5] values[0x0] 2036494 1 T25 19 T26 1 T27 25
all_pins[5] values[0x1] 1243271 1 T25 36 T1 306 T11 30
all_pins[5] transitions[0x0=>0x1] 745065 1 T25 23 T1 158 T11 14
all_pins[5] transitions[0x1=>0x0] 741863 1 T25 9 T1 272 T11 31
all_pins[6] values[0x0] 2037189 1 T25 27 T26 1 T27 25
all_pins[6] values[0x1] 1242576 1 T25 28 T1 303 T11 33
all_pins[6] transitions[0x0=>0x1] 744226 1 T25 10 T1 196 T11 21
all_pins[6] transitions[0x1=>0x0] 744921 1 T25 18 T1 199 T11 18
all_pins[7] values[0x0] 2035325 1 T25 31 T26 1 T27 25
all_pins[7] values[0x1] 1244440 1 T25 24 T1 355 T11 34
all_pins[7] transitions[0x0=>0x1] 743201 1 T25 11 T1 211 T11 18
all_pins[7] transitions[0x1=>0x0] 741337 1 T25 15 T1 159 T11 17
all_pins[8] values[0x0] 2034761 1 T25 34 T26 1 T27 25
all_pins[8] values[0x1] 1245004 1 T25 21 T1 331 T11 39
all_pins[8] transitions[0x0=>0x1] 745723 1 T25 13 T1 176 T11 21
all_pins[8] transitions[0x1=>0x0] 745159 1 T25 16 T1 200 T11 16
all_pins[9] values[0x0] 2038075 1 T25 26 T26 1 T27 25
all_pins[9] values[0x1] 1241690 1 T25 29 T1 311 T11 27
all_pins[9] transitions[0x0=>0x1] 742182 1 T25 17 T1 149 T11 16
all_pins[9] transitions[0x1=>0x0] 745496 1 T25 9 T1 169 T11 28
all_pins[10] values[0x0] 2030635 1 T25 31 T26 1 T27 25
all_pins[10] values[0x1] 1249130 1 T25 24 T1 280 T11 42
all_pins[10] transitions[0x0=>0x1] 746212 1 T25 11 T1 179 T11 27
all_pins[10] transitions[0x1=>0x0] 738772 1 T25 16 T1 210 T11 12
all_pins[11] values[0x0] 2033048 1 T25 28 T26 1 T27 25
all_pins[11] values[0x1] 1246717 1 T25 27 T1 385 T11 35
all_pins[11] transitions[0x0=>0x1] 742287 1 T25 15 T1 249 T11 14
all_pins[11] transitions[0x1=>0x0] 744700 1 T25 12 T1 144 T11 21
all_pins[12] values[0x0] 2037287 1 T25 25 T26 1 T27 23
all_pins[12] values[0x1] 1242478 1 T25 30 T27 2 T1 323
all_pins[12] transitions[0x0=>0x1] 743092 1 T25 13 T27 2 T1 147
all_pins[12] transitions[0x1=>0x0] 747331 1 T25 10 T1 209 T11 21
all_pins[13] values[0x0] 2034911 1 T25 25 T26 1 T27 23
all_pins[13] values[0x1] 1244854 1 T25 30 T27 2 T1 353
all_pins[13] transitions[0x0=>0x1] 745412 1 T25 13 T27 1 T1 236
all_pins[13] transitions[0x1=>0x0] 743036 1 T25 13 T27 1 T1 206
all_pins[14] values[0x0] 2040942 1 T25 27 T26 1 T27 19
all_pins[14] values[0x1] 1238823 1 T25 28 T27 6 T1 301
all_pins[14] transitions[0x0=>0x1] 740237 1 T25 12 T27 5 T1 189
all_pins[14] transitions[0x1=>0x0] 746268 1 T25 14 T27 1 T1 241
all_pins[15] values[0x0] 2039145 1 T25 30 T26 1 T27 25
all_pins[15] values[0x1] 1240620 1 T25 25 T1 339 T11 35
all_pins[15] transitions[0x0=>0x1] 744048 1 T25 13 T1 240 T11 18
all_pins[15] transitions[0x1=>0x0] 742251 1 T25 16 T27 6 T1 202
all_pins[16] values[0x0] 2031991 1 T25 35 T26 1 T27 25
all_pins[16] values[0x1] 1247774 1 T25 20 T1 250 T11 43
all_pins[16] transitions[0x0=>0x1] 747901 1 T25 7 T1 132 T11 19
all_pins[16] transitions[0x1=>0x0] 740747 1 T25 12 T1 221 T11 11
all_pins[17] values[0x0] 2036253 1 T25 30 T26 1 T27 25
all_pins[17] values[0x1] 1243512 1 T25 25 T1 314 T11 31
all_pins[17] transitions[0x0=>0x1] 740795 1 T25 12 T1 215 T11 10
all_pins[17] transitions[0x1=>0x0] 745057 1 T25 7 T1 151 T11 22
all_pins[18] values[0x0] 2039123 1 T25 29 T26 1 T27 25
all_pins[18] values[0x1] 1240642 1 T25 26 T1 317 T11 33
all_pins[18] transitions[0x0=>0x1] 740951 1 T25 16 T1 196 T11 20
all_pins[18] transitions[0x1=>0x0] 743821 1 T25 15 T1 193 T11 18
all_pins[19] values[0x0] 2042872 1 T25 25 T26 1 T27 24
all_pins[19] values[0x1] 1236893 1 T25 30 T27 1 T1 309
all_pins[19] transitions[0x0=>0x1] 741382 1 T25 14 T27 1 T1 180
all_pins[19] transitions[0x1=>0x0] 745131 1 T25 10 T1 188 T11 19
all_pins[20] values[0x0] 2033938 1 T25 34 T26 1 T27 24
all_pins[20] values[0x1] 1245827 1 T25 21 T27 1 T1 300
all_pins[20] transitions[0x0=>0x1] 747808 1 T25 11 T1 183 T11 24
all_pins[20] transitions[0x1=>0x0] 738874 1 T25 20 T1 192 T11 17
all_pins[21] values[0x0] 2038560 1 T25 29 T26 1 T27 22
all_pins[21] values[0x1] 1241205 1 T25 26 T27 3 T1 276
all_pins[21] transitions[0x0=>0x1] 741417 1 T25 17 T27 3 T1 156
all_pins[21] transitions[0x1=>0x0] 746039 1 T25 12 T27 1 T1 180
all_pins[22] values[0x0] 2039271 1 T25 31 T26 1 T27 25
all_pins[22] values[0x1] 1240494 1 T25 24 T1 332 T11 31
all_pins[22] transitions[0x0=>0x1] 744531 1 T25 15 T1 211 T11 11
all_pins[22] transitions[0x1=>0x0] 745242 1 T25 17 T27 3 T1 155
all_pins[23] values[0x0] 2038292 1 T25 25 T26 1 T27 21
all_pins[23] values[0x1] 1241473 1 T25 30 T27 4 T1 305
all_pins[23] transitions[0x0=>0x1] 745241 1 T25 14 T27 4 T1 164
all_pins[23] transitions[0x1=>0x0] 744262 1 T25 8 T1 191 T11 12
all_pins[24] values[0x0] 2035571 1 T25 26 T26 1 T27 24
all_pins[24] values[0x1] 1244194 1 T25 29 T27 1 T1 259
all_pins[24] transitions[0x0=>0x1] 745882 1 T25 16 T1 158 T11 19
all_pins[24] transitions[0x1=>0x0] 743161 1 T25 17 T27 3 T1 204
all_pins[25] values[0x0] 2042026 1 T25 28 T26 1 T27 22
all_pins[25] values[0x1] 1237739 1 T25 27 T27 3 T1 280
all_pins[25] transitions[0x0=>0x1] 738999 1 T25 13 T27 2 T1 203
all_pins[25] transitions[0x1=>0x0] 745454 1 T25 15 T1 182 T11 20
all_pins[26] values[0x0] 2042019 1 T25 29 T26 1 T27 25
all_pins[26] values[0x1] 1237746 1 T25 26 T1 289 T11 43
all_pins[26] transitions[0x0=>0x1] 743289 1 T25 11 T1 185 T11 26
all_pins[26] transitions[0x1=>0x0] 743282 1 T25 12 T27 3 T1 176
all_pins[27] values[0x0] 2039104 1 T25 26 T26 1 T27 20
all_pins[27] values[0x1] 1240661 1 T25 29 T27 5 T1 224
all_pins[27] transitions[0x0=>0x1] 743980 1 T25 16 T27 5 T1 143
all_pins[27] transitions[0x1=>0x0] 741065 1 T25 13 T1 208 T11 24
all_pins[28] values[0x0] 2040366 1 T25 32 T26 1 T27 22
all_pins[28] values[0x1] 1239399 1 T25 23 T27 3 T1 287
all_pins[28] transitions[0x0=>0x1] 743866 1 T25 11 T27 1 T1 230
all_pins[28] transitions[0x1=>0x0] 745128 1 T25 17 T27 3 T1 167
all_pins[29] values[0x0] 2031956 1 T25 27 T26 1 T27 23
all_pins[29] values[0x1] 1247809 1 T25 28 T27 2 T1 293
all_pins[29] transitions[0x0=>0x1] 748369 1 T25 15 T1 171 T11 17
all_pins[29] transitions[0x1=>0x0] 739959 1 T25 10 T27 1 T1 165
all_pins[30] values[0x0] 2035772 1 T25 30 T26 1 T27 24
all_pins[30] values[0x1] 1243993 1 T25 25 T27 1 T1 378
all_pins[30] transitions[0x0=>0x1] 740088 1 T25 11 T27 1 T1 220
all_pins[30] transitions[0x1=>0x0] 743904 1 T25 14 T27 2 T1 135
all_pins[31] values[0x0] 2037992 1 T25 31 T26 1 T27 25
all_pins[31] values[0x1] 1241773 1 T25 24 T1 303 T11 33
all_pins[31] transitions[0x0=>0x1] 741315 1 T25 15 T1 173 T11 13
all_pins[31] transitions[0x1=>0x0] 743535 1 T25 16 T27 1 T1 248

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