Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	11489869	1			T25	36670		T26	164		T27	65
all_values[1]	11489869	1			T25	36670		T26	164		T27	65
all_values[2]	11489869	1			T25	36670		T26	164		T27	65
all_values[3]	11489869	1			T25	36670		T26	164		T27	65
all_values[4]	11489869	1			T25	36670		T26	164		T27	65
all_values[5]	11489869	1			T25	36670		T26	164		T27	65
all_values[6]	11489869	1			T25	36670		T26	164		T27	65
all_values[7]	11489869	1			T25	36670		T26	164		T27	65
all_values[8]	11489869	1			T25	36670		T26	164		T27	65
all_values[9]	11489869	1			T25	36670		T26	164		T27	65
all_values[10]	11489869	1			T25	36670		T26	164		T27	65
all_values[11]	11489869	1			T25	36670		T26	164		T27	65
all_values[12]	11489869	1			T25	36670		T26	164		T27	65
all_values[13]	11489869	1			T25	36670		T26	164		T27	65
all_values[14]	11489869	1			T25	36670		T26	164		T27	65
all_values[15]	11489869	1			T25	36670		T26	164		T27	65
all_values[16]	11489869	1			T25	36670		T26	164		T27	65
all_values[17]	11489869	1			T25	36670		T26	164		T27	65
all_values[18]	11489869	1			T25	36670		T26	164		T27	65
all_values[19]	11489869	1			T25	36670		T26	164		T27	65
all_values[20]	11489869	1			T25	36670		T26	164		T27	65
all_values[21]	11489869	1			T25	36670		T26	164		T27	65
all_values[22]	11489869	1			T25	36670		T26	164		T27	65
all_values[23]	11489869	1			T25	36670		T26	164		T27	65
all_values[24]	11489869	1			T25	36670		T26	164		T27	65
all_values[25]	11489869	1			T25	36670		T26	164		T27	65
all_values[26]	11489869	1			T25	36670		T26	164		T27	65
all_values[27]	11489869	1			T25	36670		T26	164		T27	65
all_values[28]	11489869	1			T25	36670		T26	164		T27	65
all_values[29]	11489869	1			T25	36670		T26	164		T27	65
all_values[30]	11489869	1			T25	36670		T26	164		T27	65
all_values[31]	11489869	1			T25	36670		T26	164		T27	65

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

218697920

1

T25

117344

T26

5248

T27

1827

auto[1]

148977888

1

T27

253

T1

35010

T16

130899

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98371557

1

T25

117344

T26

5248

T27

1292

auto[1]

269304251

1

T27

788

T1

60543

T16

233755

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

363767982

1

T25

117344

T26

5248

T27

1970

auto[1]

3907826

1

T27

110

T1

2829

T16

50937

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2623813	1			T25	36670		T26	164		T27	27
all_values[0]	auto[0]	auto[0]	auto[1]	4159493	1			T27	21		T1	904		T16	36042
all_values[0]	auto[0]	auto[1]	auto[0]	453012	1			T27	11		T1	140		T16	3948
all_values[0]	auto[0]	auto[1]	auto[1]	4131267	1			T27	1		T1	946		T16	36338
all_values[0]	auto[1]	auto[0]	auto[1]	61602	1			T27	5		T1	42		T16	791
all_values[0]	auto[1]	auto[1]	auto[1]	60682	1			T1	48		T16	804		T18	4
all_values[1]	auto[0]	auto[0]	auto[0]	2617684	1			T25	36670		T26	164		T27	30
all_values[1]	auto[0]	auto[0]	auto[1]	4156547	1			T27	19		T1	931		T16	35272
all_values[1]	auto[0]	auto[1]	auto[0]	454649	1			T27	14		T1	43		T16	4707
all_values[1]	auto[0]	auto[1]	auto[1]	4138720	1			T1	1001		T16	35911		T17	765
all_values[1]	auto[1]	auto[0]	auto[1]	61580	1			T27	2		T1	45		T16	815
all_values[1]	auto[1]	auto[1]	auto[1]	60689	1			T1	50		T16	771		T18	3
all_values[2]	auto[0]	auto[0]	auto[0]	2622407	1			T25	36670		T26	164		T27	31
all_values[2]	auto[0]	auto[0]	auto[1]	4183779	1			T27	16		T1	749		T16	36237
all_values[2]	auto[0]	auto[1]	auto[0]	453812	1			T27	7		T1	169		T16	4816
all_values[2]	auto[0]	auto[1]	auto[1]	4108147	1			T27	6		T1	1034		T16	34808
all_values[2]	auto[1]	auto[0]	auto[1]	61018	1			T27	4		T1	32		T16	825
all_values[2]	auto[1]	auto[1]	auto[1]	60706	1			T27	1		T1	62		T16	774
all_values[3]	auto[0]	auto[0]	auto[0]	2617116	1			T25	36670		T26	164		T27	32
all_values[3]	auto[0]	auto[0]	auto[1]	4136966	1			T27	26		T1	882		T16	35557
all_values[3]	auto[0]	auto[1]	auto[0]	449455	1			T27	2		T1	121		T16	4066
all_values[3]	auto[0]	auto[1]	auto[1]	4164350	1			T1	963		T16	36026		T17	779
all_values[3]	auto[1]	auto[0]	auto[1]	60622	1			T27	4		T1	38		T16	804
all_values[3]	auto[1]	auto[1]	auto[1]	61360	1			T27	1		T1	49		T16	840
all_values[4]	auto[0]	auto[0]	auto[0]	2625768	1			T25	36670		T26	164		T27	40
all_values[4]	auto[0]	auto[0]	auto[1]	4170083	1			T27	20		T1	726		T16	35464
all_values[4]	auto[0]	auto[1]	auto[0]	453816	1			T27	3		T1	170		T16	4482
all_values[4]	auto[0]	auto[1]	auto[1]	4118366	1			T1	1152		T16	35693		T17	614
all_values[4]	auto[1]	auto[0]	auto[1]	61234	1			T27	2		T1	32		T16	772
all_values[4]	auto[1]	auto[1]	auto[1]	60602	1			T1	48		T16	757		T18	4
all_values[5]	auto[0]	auto[0]	auto[0]	2630955	1			T25	36670		T26	164		T27	37
all_values[5]	auto[0]	auto[0]	auto[1]	4155509	1			T27	20		T1	792		T16	35962
all_values[5]	auto[0]	auto[1]	auto[0]	451304	1			T27	5		T1	190		T16	4285
all_values[5]	auto[0]	auto[1]	auto[1]	4130092	1			T1	969		T16	35481		T17	801
all_values[5]	auto[1]	auto[0]	auto[1]	61510	1			T27	3		T1	38		T16	781
all_values[5]	auto[1]	auto[1]	auto[1]	60499	1			T1	48		T16	784		T51	33
all_values[6]	auto[0]	auto[0]	auto[0]	2624248	1			T25	36670		T26	164		T27	29
all_values[6]	auto[0]	auto[0]	auto[1]	4133917	1			T27	27		T1	946		T16	34330
all_values[6]	auto[0]	auto[1]	auto[0]	453887	1			T27	7		T1	141		T16	4413
all_values[6]	auto[0]	auto[1]	auto[1]	4156044	1			T1	898		T16	37130		T17	795
all_values[6]	auto[1]	auto[0]	auto[1]	60849	1			T27	2		T1	48		T16	789
all_values[6]	auto[1]	auto[1]	auto[1]	60924	1			T1	35		T16	813		T18	2
all_values[7]	auto[0]	auto[0]	auto[0]	2616180	1			T25	36670		T26	164		T27	41
all_values[7]	auto[0]	auto[0]	auto[1]	4147822	1			T27	21		T1	865		T16	37761
all_values[7]	auto[0]	auto[1]	auto[0]	450926	1			T1	86		T16	4238		T17	23
all_values[7]	auto[0]	auto[1]	auto[1]	4153071	1			T1	1057		T16	33923		T17	423
all_values[7]	auto[1]	auto[0]	auto[1]	60974	1			T27	3		T1	38		T16	800
all_values[7]	auto[1]	auto[1]	auto[1]	60896	1			T1	56		T16	820		T18	5
all_values[8]	auto[0]	auto[0]	auto[0]	2616563	1			T25	36670		T26	164		T27	41
all_values[8]	auto[0]	auto[0]	auto[1]	4153942	1			T27	22		T1	945		T16	33729
all_values[8]	auto[0]	auto[1]	auto[0]	449466	1			T1	78		T16	4333		T17	112
all_values[8]	auto[0]	auto[1]	auto[1]	4147841	1			T1	873		T16	38078		T17	944
all_values[8]	auto[1]	auto[0]	auto[1]	61190	1			T27	2		T1	42		T16	789
all_values[8]	auto[1]	auto[1]	auto[1]	60867	1			T1	37		T16	799		T18	6
all_values[9]	auto[0]	auto[0]	auto[0]	2620240	1			T25	36670		T26	164		T27	49
all_values[9]	auto[0]	auto[0]	auto[1]	4150475	1			T27	10		T1	939		T16	36032
all_values[9]	auto[0]	auto[1]	auto[0]	455275	1			T27	5		T1	152		T16	4151
all_values[9]	auto[0]	auto[1]	auto[1]	4141869	1			T1	824		T16	35957		T17	854
all_values[9]	auto[1]	auto[0]	auto[1]	60894	1			T27	1		T1	51		T16	791
all_values[9]	auto[1]	auto[1]	auto[1]	61116	1			T1	38		T16	824		T18	6
all_values[10]	auto[0]	auto[0]	auto[0]	2622735	1			T25	36670		T26	164		T27	33
all_values[10]	auto[0]	auto[0]	auto[1]	4107827	1			T27	19		T1	925		T16	35693
all_values[10]	auto[0]	auto[1]	auto[0]	455286	1			T27	10		T1	159		T16	4159
all_values[10]	auto[0]	auto[1]	auto[1]	4181832	1			T1	836		T16	35634		T17	942
all_values[10]	auto[1]	auto[0]	auto[1]	61329	1			T27	3		T1	48		T16	800
all_values[10]	auto[1]	auto[1]	auto[1]	60860	1			T1	40		T16	747		T18	3
all_values[11]	auto[0]	auto[0]	auto[0]	2623778	1			T25	36670		T26	164		T27	44
all_values[11]	auto[0]	auto[0]	auto[1]	4145982	1			T27	18		T1	684		T16	34315
all_values[11]	auto[0]	auto[1]	auto[0]	451929	1			T1	158		T16	4293		T17	109
all_values[11]	auto[0]	auto[1]	auto[1]	4146188	1			T1	1120		T16	37048		T17	914
all_values[11]	auto[1]	auto[0]	auto[1]	61053	1			T27	3		T1	26		T16	788
all_values[11]	auto[1]	auto[1]	auto[1]	60939	1			T1	58		T16	786		T18	3
all_values[12]	auto[0]	auto[0]	auto[0]	2636457	1			T25	36670		T26	164		T27	34
all_values[12]	auto[0]	auto[0]	auto[1]	4166982	1			T27	20		T1	859		T16	36307
all_values[12]	auto[0]	auto[1]	auto[0]	446808	1			T27	6		T1	148		T16	4276
all_values[12]	auto[0]	auto[1]	auto[1]	4117268	1			T1	922		T16	34826		T17	516
all_values[12]	auto[1]	auto[0]	auto[1]	61463	1			T27	3		T1	44		T16	812
all_values[12]	auto[1]	auto[1]	auto[1]	60891	1			T27	2		T1	44		T16	752
all_values[13]	auto[0]	auto[0]	auto[0]	2625557	1			T25	36670		T26	164		T27	35
all_values[13]	auto[0]	auto[0]	auto[1]	4145542	1			T27	18		T1	793		T16	35883
all_values[13]	auto[0]	auto[1]	auto[0]	452505	1			T27	8		T1	110		T16	4629
all_values[13]	auto[0]	auto[1]	auto[1]	4144084	1			T27	1		T1	981		T16	35220
all_values[13]	auto[1]	auto[0]	auto[1]	61180	1			T27	2		T1	36		T16	803
all_values[13]	auto[1]	auto[1]	auto[1]	61001	1			T27	1		T1	57		T16	809
all_values[14]	auto[0]	auto[0]	auto[0]	2626804	1			T25	36670		T26	164		T27	24
all_values[14]	auto[0]	auto[0]	auto[1]	4144391	1			T27	20		T1	865		T16	35753
all_values[14]	auto[0]	auto[1]	auto[0]	448722	1			T27	12		T1	106		T16	4292
all_values[14]	auto[0]	auto[1]	auto[1]	4147789	1			T27	5		T1	939		T16	35815
all_values[14]	auto[1]	auto[0]	auto[1]	61273	1			T27	2		T1	52		T16	852
all_values[14]	auto[1]	auto[1]	auto[1]	60890	1			T27	2		T1	49		T16	750
all_values[15]	auto[0]	auto[0]	auto[0]	2623667	1			T25	36670		T26	164		T27	41
all_values[15]	auto[0]	auto[0]	auto[1]	4140130	1			T27	22		T1	905		T16	34899
all_values[15]	auto[0]	auto[1]	auto[0]	449048	1			T1	115		T16	4350		T17	79
all_values[15]	auto[0]	auto[1]	auto[1]	4154763	1			T1	915		T16	37115		T17	920
all_values[15]	auto[1]	auto[0]	auto[1]	61656	1			T27	2		T1	42		T16	755
all_values[15]	auto[1]	auto[1]	auto[1]	60605	1			T1	49		T16	836		T18	5
all_values[16]	auto[0]	auto[0]	auto[0]	2619091	1			T25	36670		T26	164		T27	30
all_values[16]	auto[0]	auto[0]	auto[1]	4153252	1			T27	27		T1	1065		T16	35581
all_values[16]	auto[0]	auto[1]	auto[0]	454624	1			T27	3		T1	92		T16	4375
all_values[16]	auto[0]	auto[1]	auto[1]	4140850	1			T1	774		T16	36047		T17	439
all_values[16]	auto[1]	auto[0]	auto[1]	60912	1			T27	5		T1	47		T16	791
all_values[16]	auto[1]	auto[1]	auto[1]	61140	1			T1	30		T16	821		T18	4
all_values[17]	auto[0]	auto[0]	auto[0]	2624971	1			T25	36670		T26	164		T27	44
all_values[17]	auto[0]	auto[0]	auto[1]	4138850	1			T27	15		T1	882		T16	35775
all_values[17]	auto[0]	auto[1]	auto[0]	448789	1			T27	2		T1	112		T16	4397
all_values[17]	auto[0]	auto[1]	auto[1]	4155095	1			T1	991		T16	35449		T17	698
all_values[17]	auto[1]	auto[0]	auto[1]	61116	1			T27	4		T1	46		T16	822
all_values[17]	auto[1]	auto[1]	auto[1]	61048	1			T1	44		T16	749		T18	3
all_values[18]	auto[0]	auto[0]	auto[0]	2619152	1			T25	36670		T26	164		T27	40
all_values[18]	auto[0]	auto[0]	auto[1]	4163008	1			T27	20		T1	842		T16	34924
all_values[18]	auto[0]	auto[1]	auto[0]	442609	1			T27	3		T1	119		T16	4387
all_values[18]	auto[0]	auto[1]	auto[1]	4142581	1			T1	911		T16	36559		T17	917
all_values[18]	auto[1]	auto[0]	auto[1]	61530	1			T27	2		T1	44		T16	820
all_values[18]	auto[1]	auto[1]	auto[1]	60989	1			T1	44		T16	791		T18	2
all_values[19]	auto[0]	auto[0]	auto[0]	2616797	1			T25	36670		T26	164		T27	27
all_values[19]	auto[0]	auto[0]	auto[1]	4162255	1			T27	25		T1	881		T16	37530
all_values[19]	auto[0]	auto[1]	auto[0]	452702	1			T27	10		T1	151		T16	4504
all_values[19]	auto[0]	auto[1]	auto[1]	4136128	1			T27	1		T1	925		T16	33485
all_values[19]	auto[1]	auto[0]	auto[1]	61357	1			T27	2		T1	47		T16	774
all_values[19]	auto[1]	auto[1]	auto[1]	60630	1			T1	47		T16	840		T18	3
all_values[20]	auto[0]	auto[0]	auto[0]	2631664	1			T25	36670		T26	164		T27	40
all_values[20]	auto[0]	auto[0]	auto[1]	4140575	1			T27	22		T1	1049		T16	36758
all_values[20]	auto[0]	auto[1]	auto[0]	455505	1			T27	1		T1	108		T16	4496
all_values[20]	auto[0]	auto[1]	auto[1]	4140071	1			T27	1		T1	788		T16	34831
all_values[20]	auto[1]	auto[0]	auto[1]	60864	1			T27	1		T1	41		T16	764
all_values[20]	auto[1]	auto[1]	auto[1]	61190	1			T1	45		T16	800		T18	2
all_values[21]	auto[0]	auto[0]	auto[0]	2621191	1			T25	36670		T26	164		T27	25
all_values[21]	auto[0]	auto[0]	auto[1]	4156850	1			T27	20		T1	1011		T16	36194
all_values[21]	auto[0]	auto[1]	auto[0]	445468	1			T27	10		T1	121		T16	4760
all_values[21]	auto[0]	auto[1]	auto[1]	4143757	1			T27	6		T1	775		T16	34905
all_values[21]	auto[1]	auto[0]	auto[1]	61376	1			T27	4		T1	53		T16	820
all_values[21]	auto[1]	auto[1]	auto[1]	61227	1			T1	44		T16	800		T18	3
all_values[22]	auto[0]	auto[0]	auto[0]	2624869	1			T25	36670		T26	164		T27	43
all_values[22]	auto[0]	auto[0]	auto[1]	4126874	1			T27	19		T1	963		T16	35809
all_values[22]	auto[0]	auto[1]	auto[0]	451178	1			T1	112		T16	4358		T17	32
all_values[22]	auto[0]	auto[1]	auto[1]	4165106	1			T1	912		T16	35402		T17	890
all_values[22]	auto[1]	auto[0]	auto[1]	60979	1			T27	3		T1	50		T16	792
all_values[22]	auto[1]	auto[1]	auto[1]	60863	1			T1	41		T16	789		T18	3
all_values[23]	auto[0]	auto[0]	auto[0]	2621322	1			T25	36670		T26	164		T27	30
all_values[23]	auto[0]	auto[0]	auto[1]	4161748	1			T27	15		T1	858		T16	36487
all_values[23]	auto[0]	auto[1]	auto[0]	441751	1			T27	15		T1	183		T16	4561
all_values[23]	auto[0]	auto[1]	auto[1]	4142847	1			T27	2		T1	874		T16	34488
all_values[23]	auto[1]	auto[0]	auto[1]	61587	1			T27	1		T1	46		T16	801
all_values[23]	auto[1]	auto[1]	auto[1]	60614	1			T27	2		T1	45		T16	817
all_values[24]	auto[0]	auto[0]	auto[0]	2625810	1			T25	36670		T26	164		T27	27
all_values[24]	auto[0]	auto[0]	auto[1]	4136279	1			T27	20		T1	1010		T16	34804
all_values[24]	auto[0]	auto[1]	auto[0]	446496	1			T27	13		T1	161		T16	5202
all_values[24]	auto[0]	auto[1]	auto[1]	4159353	1			T1	779		T16	36113		T17	930
all_values[24]	auto[1]	auto[0]	auto[1]	61026	1			T27	4		T1	43		T16	819
all_values[24]	auto[1]	auto[1]	auto[1]	60905	1			T27	1		T1	30		T16	788
all_values[25]	auto[0]	auto[0]	auto[0]	2625383	1			T25	36670		T26	164		T27	27
all_values[25]	auto[0]	auto[0]	auto[1]	4162393	1			T27	18		T1	925		T16	35999
all_values[25]	auto[0]	auto[1]	auto[0]	446736	1			T27	14		T1	95		T16	4149
all_values[25]	auto[0]	auto[1]	auto[1]	4133415	1			T27	1		T1	874		T16	36014
all_values[25]	auto[1]	auto[0]	auto[1]	61410	1			T27	3		T1	47		T16	811
all_values[25]	auto[1]	auto[1]	auto[1]	60532	1			T27	2		T1	43		T16	766
all_values[26]	auto[0]	auto[0]	auto[0]	2624547	1			T25	36670		T26	164		T27	41
all_values[26]	auto[0]	auto[0]	auto[1]	4178109	1			T27	19		T1	870		T16	37111
all_values[26]	auto[0]	auto[1]	auto[0]	444781	1			T1	144		T16	4294		T17	95
all_values[26]	auto[0]	auto[1]	auto[1]	4120178	1			T1	840		T16	34243		T17	681
all_values[26]	auto[1]	auto[0]	auto[1]	61520	1			T27	5		T1	54		T16	838
all_values[26]	auto[1]	auto[1]	auto[1]	60734	1			T1	34		T16	756		T18	2
all_values[27]	auto[0]	auto[0]	auto[0]	2630584	1			T25	36670		T26	164		T27	23
all_values[27]	auto[0]	auto[0]	auto[1]	4136655	1			T27	23		T1	1137		T16	36014
all_values[27]	auto[0]	auto[1]	auto[0]	452694	1			T27	13		T1	121		T16	4590
all_values[27]	auto[0]	auto[1]	auto[1]	4147142	1			T27	4		T1	610		T16	35267
all_values[27]	auto[1]	auto[0]	auto[1]	61734	1			T1	52		T16	853		T18	7
all_values[27]	auto[1]	auto[1]	auto[1]	61060	1			T27	2		T1	28		T16	728
all_values[28]	auto[0]	auto[0]	auto[0]	2626785	1			T25	36670		T26	164		T27	24
all_values[28]	auto[0]	auto[0]	auto[1]	4132759	1			T27	20		T1	731		T16	35279
all_values[28]	auto[0]	auto[1]	auto[0]	455011	1			T27	16		T1	230		T16	4539
all_values[28]	auto[0]	auto[1]	auto[1]	4152856	1			T27	1		T1	953		T16	36299
all_values[28]	auto[1]	auto[0]	auto[1]	61515	1			T27	2		T1	43		T16	823
all_values[28]	auto[1]	auto[1]	auto[1]	60943	1			T27	2		T1	44		T16	790
all_values[29]	auto[0]	auto[0]	auto[0]	2627912	1			T25	36670		T26	164		T27	31
all_values[29]	auto[0]	auto[0]	auto[1]	4149510	1			T27	22		T1	785		T16	35578
all_values[29]	auto[0]	auto[1]	auto[0]	452136	1			T27	5		T1	163		T16	4488
all_values[29]	auto[0]	auto[1]	auto[1]	4138325	1			T27	1		T1	904		T16	35746
all_values[29]	auto[1]	auto[0]	auto[1]	61215	1			T27	5		T1	46		T16	834
all_values[29]	auto[1]	auto[1]	auto[1]	60771	1			T27	1		T1	57		T16	760
all_values[30]	auto[0]	auto[0]	auto[0]	2627483	1			T25	36670		T26	164		T27	34
all_values[30]	auto[0]	auto[0]	auto[1]	4146859	1			T27	24		T1	842		T16	36536
all_values[30]	auto[0]	auto[1]	auto[0]	445658	1			T27	2		T1	116		T16	4040
all_values[30]	auto[0]	auto[1]	auto[1]	4148026	1			T1	1046		T16	35469		T17	772
all_values[30]	auto[1]	auto[0]	auto[1]	60940	1			T27	4		T1	36		T16	786
all_values[30]	auto[1]	auto[1]	auto[1]	60903	1			T27	1		T1	55		T16	773
all_values[31]	auto[0]	auto[0]	auto[0]	2616515	1			T25	36670		T26	164		T27	33
all_values[31]	auto[0]	auto[0]	auto[1]	4134990	1			T27	20		T1	870		T16	34308
all_values[31]	auto[0]	auto[1]	auto[0]	447471	1			T27	8		T1	170		T16	4469
all_values[31]	auto[0]	auto[1]	auto[1]	4168651	1			T1	897		T16	37374		T17	791
all_values[31]	auto[1]	auto[0]	auto[1]	61011	1			T27	4		T1	37		T16	767
all_values[31]	auto[1]	auto[1]	auto[1]	61231	1			T1	44		T16	821		T18	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal