Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[1]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[2]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[3]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[4]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[5]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[6]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[7]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[8]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[9]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[10]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[11]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[12]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[13]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[14]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[15]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[16]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[17]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[18]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[19]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[20]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[21]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[22]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[23]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[24]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[25]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[26]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[27]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[28]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[29]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[30]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[31]	11351349	1			T25	36670		T26	218		T27	103

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212445982

1

T25

580734

T26

4433

T27

1609

auto[1]

150797186

1

T25

592706

T26

2543

T27

1687

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

293543296

1

T25

117344

T26

5226

T27

3029

auto[1]

69699872

1

T26

1750

T27

267

T1

27298

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

273040586

1

T25

117344

T26

5337

T27

2483

auto[1]

90202582

1

T26

1639

T27

813

T1

31386

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4209312	1			T25	18107		T26	99		T27	64
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3232053	1			T25	18563		T26	60		T27	18
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1095196	1			T26	23		T27	6		T1	380
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1337948	1			T26	26		T27	9		T1	615
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	396464	1			T27	5		T1	15		T12	200
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1080376	1			T26	10		T27	1		T1	423
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4211290	1			T25	18444		T26	91		T27	37
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3234471	1			T25	18226		T26	46		T27	45
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1096607	1			T26	30		T27	4		T1	388
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1334661	1			T26	29		T27	14		T1	632
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	394687	1			T27	3		T1	12		T12	213
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1079633	1			T26	22		T1	340		T12	103
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4206348	1			T25	19133		T26	86		T27	34
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3231368	1			T25	17537		T26	52		T27	45
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1097371	1			T26	36		T27	4		T1	445
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1335989	1			T26	16		T27	3		T1	552
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	396589	1			T27	8		T1	19		T12	184
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1083684	1			T26	28		T27	9		T1	462
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4200611	1			T25	18072		T26	92		T27	29
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3229269	1			T25	18598		T26	52		T27	22
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1093155	1			T26	22		T27	9		T1	453
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1337878	1			T26	34		T27	18		T1	500
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	396274	1			T27	5		T1	16		T12	204
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1094162	1			T26	18		T27	20		T1	439
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4196175	1			T25	17580		T26	74		T27	31
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3243265	1			T25	19090		T26	59		T27	46
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1091092	1			T26	25		T1	405		T12	133
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1340586	1			T26	32		T27	20		T1	495
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	392950	1			T27	6		T1	13		T12	213
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1087281	1			T26	28		T1	468		T12	86
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4205205	1			T25	18839		T26	85		T27	25
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3232237	1			T25	17831		T26	54		T27	58
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1095362	1			T26	19		T1	430		T12	123
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1335402	1			T26	22		T1	555		T12	34
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	395065	1			T27	14		T1	11		T12	272
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1088078	1			T26	38		T27	6		T1	382
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4203638	1			T25	18514		T26	79		T27	48
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3233417	1			T25	18156		T26	47		T27	21
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1098403	1			T26	16		T1	472		T12	134
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1334629	1			T26	48		T27	14		T1	462
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	394460	1			T27	5		T1	9		T12	256
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1086802	1			T26	28		T27	15		T1	317
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4199924	1			T25	19905		T26	93		T27	13
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3231122	1			T25	16765		T26	51		T27	76
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1091949	1			T26	22		T1	481		T12	95
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1337587	1			T26	26		T1	570		T12	42
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	397754	1			T27	8		T1	18		T12	297
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1093013	1			T26	26		T27	6		T1	459
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4200895	1			T25	18880		T26	84		T27	27
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3236710	1			T25	17790		T26	51		T27	49
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1099431	1			T26	44		T1	471		T12	86
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1333603	1			T26	15		T27	17		T1	581
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	397944	1			T27	7		T1	10		T12	229
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1082766	1			T26	24		T27	3		T1	269
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4202405	1			T25	17415		T26	94		T27	14
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3227340	1			T25	19255		T26	41		T27	74
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1093609	1			T26	20		T1	433		T12	120
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1340638	1			T26	30		T27	3		T1	487
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	395314	1			T27	12		T1	9		T12	249
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1092043	1			T26	33		T1	360		T12	86
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4203072	1			T25	17855		T26	79		T27	45
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3230426	1			T25	18815		T26	54		T27	15
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1094826	1			T26	37		T1	458		T12	88
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1339098	1			T26	20		T27	15		T1	491
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	396739	1			T27	11		T1	6		T12	258
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1087188	1			T26	28		T27	17		T1	406
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4208832	1			T25	20316		T26	77		T27	55
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3231075	1			T25	16354		T26	60		T27	11
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1095328	1			T26	30		T27	3		T1	334
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1335608	1			T26	32		T27	25		T1	730
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	392705	1			T27	3		T1	22		T12	239
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1087801	1			T26	19		T27	6		T1	326
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4204067	1			T25	18880		T26	84		T27	35
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3233010	1			T25	17790		T26	55		T27	38
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1098374	1			T26	28		T27	3		T1	457
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1337947	1			T26	34		T27	7		T1	538
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	393653	1			T27	15		T1	17		T12	266
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1084298	1			T26	17		T27	5		T1	369
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4189131	1			T25	17039		T26	94		T27	44
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3242489	1			T25	19631		T26	51		T27	21
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1099855	1			T26	30		T27	12		T1	486
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1336641	1			T26	20		T27	17		T1	485
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	394636	1			T27	3		T1	13		T12	186
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1088597	1			T26	23		T27	6		T1	337
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4207940	1			T25	18027		T26	76		T27	46
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3230416	1			T25	18643		T26	48		T27	34
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1094301	1			T26	38		T27	5		T1	337
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1338809	1			T26	30		T27	15		T1	627
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	396599	1			T27	2		T1	13		T12	286
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1083284	1			T26	26		T27	1		T1	520
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4207978	1			T25	17423		T26	83		T27	46
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3231351	1			T25	19247		T26	46		T27	19
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1097042	1			T26	30		T27	1		T1	437
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1334123	1			T26	28		T27	29		T1	582
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	394212	1			T27	4		T1	16		T12	215
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1086643	1			T26	31		T27	4		T1	407
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4210278	1			T25	17548		T26	82		T27	28
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3233572	1			T25	19122		T26	61		T27	46
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1092220	1			T26	27		T1	461		T12	143
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1339675	1			T26	18		T27	17		T1	527
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	396186	1			T27	6		T1	10		T12	164
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1079418	1			T26	30		T27	6		T1	473
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4210440	1			T25	18248		T26	72		T27	62
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3227606	1			T25	18422		T26	55		T27	13
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1092293	1			T26	32		T1	498		T12	128
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1338630	1			T26	31		T27	15		T1	456
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	397547	1			T27	4		T1	14		T12	227
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1084833	1			T26	28		T27	9		T1	354
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4205916	1			T25	17404		T26	97		T27	42
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3233050	1			T25	19266		T26	54		T27	49
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1090207	1			T26	35		T27	2		T1	405
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1344032	1			T26	10		T1	662		T12	35
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	393731	1			T27	5		T1	24		T12	199
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1084413	1			T26	22		T27	5		T1	419
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4207160	1			T25	17361		T26	74		T27	18
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3233525	1			T25	19309		T26	51		T27	45
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1086966	1			T26	18		T27	4		T1	567
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1344280	1			T26	41		T27	12		T1	449
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	395805	1			T27	19		T1	12		T12	197
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1083613	1			T26	34		T27	5		T1	382
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4205697	1			T25	18884		T26	74		T27	26
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3231881	1			T25	17786		T26	51		T27	40
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1092837	1			T26	25		T1	322		T12	105
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1344676	1			T26	28		T27	16		T1	658
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	394012	1			T27	16		T1	12		T12	251
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1082246	1			T26	40		T27	5		T1	498
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4205577	1			T25	17747		T26	75		T27	13
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3232180	1			T25	18923		T26	61		T27	44
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1090420	1			T26	22		T27	9		T1	483
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1343705	1			T26	34		T27	9		T1	437
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	397628	1			T27	17		T1	18		T12	254
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1081839	1			T26	26		T27	11		T1	442
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4212751	1			T25	17033		T26	77		T27	40
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3228537	1			T25	19637		T26	60		T27	33
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1092151	1			T26	22		T27	4		T1	398
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1340540	1			T26	37		T27	15		T1	569
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	396454	1			T27	5		T1	28		T12	225
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1080916	1			T26	22		T27	6		T1	438
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4221293	1			T25	18791		T26	96		T27	50
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3222012	1			T25	17879		T26	49		T27	22
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1093465	1			T26	46		T27	6		T1	462
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1337977	1			T26	16		T27	25		T1	491
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	395099	1			T1	5		T12	269		T13	19
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1081503	1			T26	11		T1	481		T12	150
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4213452	1			T25	18459		T26	89		T27	40
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3232646	1			T25	18211		T26	51		T27	44
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1092315	1			T26	38		T27	3		T1	458
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1337862	1			T26	18		T27	7		T1	601
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	394628	1			T27	9		T1	23		T12	281
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1080446	1			T26	22		T1	471		T12	75
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4202257	1			T25	17641		T26	101		T27	48
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3238428	1			T25	19029		T26	50		T27	36
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1093581	1			T26	20		T27	2		T1	410
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1339944	1			T26	26		T27	7		T1	557
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	395443	1			T27	4		T1	15		T12	274
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1081696	1			T26	21		T27	6		T1	426
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4210081	1			T25	17966		T26	77		T27	54
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3235914	1			T25	18704		T26	62		T27	33
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1096114	1			T26	20		T27	2		T1	511
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1335314	1			T26	22		T27	13		T1	465
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	395934	1			T27	1		T1	20		T12	204
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1077992	1			T26	37		T1	481		T12	117
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4209601	1			T25	17749		T26	85		T27	41
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3225670	1			T25	18921		T26	57		T27	48
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1091722	1			T26	40		T1	474		T12	108
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1344319	1			T26	16		T27	8		T1	485
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	397026	1			T27	5		T1	29		T12	239
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1083011	1			T26	20		T27	1		T1	453
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4215844	1			T25	17906		T26	79		T27	15
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3223392	1			T25	18764		T26	54		T27	52
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1091762	1			T26	30		T1	497		T12	105
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1342160	1			T26	20		T27	3		T1	540
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	395399	1			T27	25		T1	6		T12	222
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1082792	1			T26	35		T27	8		T1	385
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4204553	1			T25	17802		T26	76		T27	19
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3232469	1			T25	18868		T26	63		T27	64
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1089531	1			T26	24		T1	475		T12	109
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1344298	1			T26	22		T1	546		T12	33
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	397050	1			T27	16		T1	20		T12	222
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1083448	1			T26	33		T27	4		T1	489
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4192738	1			T25	18230		T26	82		T27	26
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3245183	1			T25	18440		T26	55		T27	44
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1093557	1			T26	30		T27	6		T1	328
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1340950	1			T26	28		T27	11		T1	660
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	394947	1			T27	11		T1	28		T12	272
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1083974	1			T26	23		T27	5		T1	454
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4207297	1			T25	17536		T26	80		T27	27
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3238365	1			T25	19134		T26	61		T27	45
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1093337	1			T26	50		T27	6		T1	409
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1340336	1			T26	9		T27	12		T1	611
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	394310	1			T27	7		T1	14		T12	325
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1077704	1			T26	18		T27	6		T1	343

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal