Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[1]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[2]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[3]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[4]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[5]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[6]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[7]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[8]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[9]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[10]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[11]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[12]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[13]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[14]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[15]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[16]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[17]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[18]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[19]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[20]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[21]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[22]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[23]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[24]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[25]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[26]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[27]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[28]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[29]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[30]	11351349	1			T25	36670		T26	218		T27	103
bins_for_gpio_bits[31]	11351349	1			T25	36670		T26	218		T27	103

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212445982

1

T25

580734

T26

4433

T27

1609

auto[1]

150797186

1

T25

592706

T26

2543

T27

1687

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212438240

1

T25

580734

T26

4422

T27

1610

auto[1]

150804928

1

T25

592706

T26

2554

T27

1686

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6447594	1			T25	18107		T26	145		T27	79
bins_for_gpio_bits[0]	auto[0]	auto[1]	194606	1			T26	3		T1	69		T12	18
bins_for_gpio_bits[0]	auto[1]	auto[0]	194862	1			T26	3		T1	70		T12	18
bins_for_gpio_bits[0]	auto[1]	auto[1]	4514287	1			T25	18563		T26	67		T27	24
bins_for_gpio_bits[1]	auto[0]	auto[0]	6447505	1			T25	18444		T26	141		T27	55
bins_for_gpio_bits[1]	auto[0]	auto[1]	194790	1			T26	9		T1	52		T12	23
bins_for_gpio_bits[1]	auto[1]	auto[0]	195053	1			T26	9		T1	53		T12	23
bins_for_gpio_bits[1]	auto[1]	auto[1]	4514001	1			T25	18226		T26	59		T27	48
bins_for_gpio_bits[2]	auto[0]	auto[0]	6444819	1			T25	19133		T26	130		T27	41
bins_for_gpio_bits[2]	auto[0]	auto[1]	194635	1			T26	8		T27	1		T1	68
bins_for_gpio_bits[2]	auto[1]	auto[0]	194889	1			T26	8		T1	69		T12	16
bins_for_gpio_bits[2]	auto[1]	auto[1]	4517006	1			T25	17537		T26	72		T27	61
bins_for_gpio_bits[3]	auto[0]	auto[0]	6435473	1			T25	18072		T26	143		T27	54
bins_for_gpio_bits[3]	auto[0]	auto[1]	195976	1			T26	5		T27	1		T1	54
bins_for_gpio_bits[3]	auto[1]	auto[0]	196171	1			T26	5		T27	2		T1	55
bins_for_gpio_bits[3]	auto[1]	auto[1]	4523729	1			T25	18598		T26	65		T27	46
bins_for_gpio_bits[4]	auto[0]	auto[0]	6432884	1			T25	17580		T26	125		T27	51
bins_for_gpio_bits[4]	auto[0]	auto[1]	194717	1			T26	6		T1	61		T12	22
bins_for_gpio_bits[4]	auto[1]	auto[0]	194969	1			T26	6		T1	62		T12	22
bins_for_gpio_bits[4]	auto[1]	auto[1]	4528779	1			T25	19090		T26	81		T27	52
bins_for_gpio_bits[5]	auto[0]	auto[0]	6440776	1			T25	18839		T26	117		T27	25
bins_for_gpio_bits[5]	auto[0]	auto[1]	194907	1			T26	9		T1	57		T12	18
bins_for_gpio_bits[5]	auto[1]	auto[0]	195193	1			T26	9		T1	57		T12	18
bins_for_gpio_bits[5]	auto[1]	auto[1]	4520473	1			T25	17831		T26	83		T27	78
bins_for_gpio_bits[6]	auto[0]	auto[0]	6441614	1			T25	18514		T26	135		T27	62
bins_for_gpio_bits[6]	auto[0]	auto[1]	194824	1			T26	8		T1	53		T12	19
bins_for_gpio_bits[6]	auto[1]	auto[0]	195056	1			T26	8		T1	53		T12	19
bins_for_gpio_bits[6]	auto[1]	auto[1]	4519855	1			T25	18156		T26	67		T27	41
bins_for_gpio_bits[7]	auto[0]	auto[0]	6434254	1			T25	19905		T26	132		T27	13
bins_for_gpio_bits[7]	auto[0]	auto[1]	194981	1			T26	9		T1	68		T12	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	195206	1			T26	9		T1	68		T12	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	4526908	1			T25	16765		T26	68		T27	90
bins_for_gpio_bits[8]	auto[0]	auto[0]	6439399	1			T25	18880		T26	134		T27	44
bins_for_gpio_bits[8]	auto[0]	auto[1]	194319	1			T26	9		T1	49		T12	17
bins_for_gpio_bits[8]	auto[1]	auto[0]	194530	1			T26	9		T1	49		T12	17
bins_for_gpio_bits[8]	auto[1]	auto[1]	4523101	1			T25	17790		T26	66		T27	59
bins_for_gpio_bits[9]	auto[0]	auto[0]	6441330	1			T25	17415		T26	135		T27	17
bins_for_gpio_bits[9]	auto[0]	auto[1]	195031	1			T26	8		T1	62		T12	16
bins_for_gpio_bits[9]	auto[1]	auto[0]	195322	1			T26	9		T1	62		T12	16
bins_for_gpio_bits[9]	auto[1]	auto[1]	4519666	1			T25	19255		T26	66		T27	86
bins_for_gpio_bits[10]	auto[0]	auto[0]	6441863	1			T25	17855		T26	128		T27	60
bins_for_gpio_bits[10]	auto[0]	auto[1]	194899	1			T26	8		T27	1		T1	56
bins_for_gpio_bits[10]	auto[1]	auto[0]	195133	1			T26	8		T1	56		T12	13
bins_for_gpio_bits[10]	auto[1]	auto[1]	4519454	1			T25	18815		T26	74		T27	42
bins_for_gpio_bits[11]	auto[0]	auto[0]	6444297	1			T25	20316		T26	132		T27	83
bins_for_gpio_bits[11]	auto[0]	auto[1]	195204	1			T26	6		T1	47		T12	20
bins_for_gpio_bits[11]	auto[1]	auto[0]	195471	1			T26	7		T1	47		T12	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	4516377	1			T25	16354		T26	73		T27	20
bins_for_gpio_bits[12]	auto[0]	auto[0]	6444826	1			T25	18880		T26	138		T27	45
bins_for_gpio_bits[12]	auto[0]	auto[1]	195312	1			T26	7		T1	58		T12	18
bins_for_gpio_bits[12]	auto[1]	auto[0]	195562	1			T26	8		T1	58		T12	18
bins_for_gpio_bits[12]	auto[1]	auto[1]	4515649	1			T25	17790		T26	65		T27	58
bins_for_gpio_bits[13]	auto[0]	auto[0]	6430510	1			T25	17039		T26	137		T27	73
bins_for_gpio_bits[13]	auto[0]	auto[1]	194888	1			T26	6		T1	54		T12	20
bins_for_gpio_bits[13]	auto[1]	auto[0]	195117	1			T26	7		T1	54		T12	20
bins_for_gpio_bits[13]	auto[1]	auto[1]	4530834	1			T25	19631		T26	68		T27	30
bins_for_gpio_bits[14]	auto[0]	auto[0]	6446594	1			T25	18027		T26	136		T27	66
bins_for_gpio_bits[14]	auto[0]	auto[1]	194234	1			T26	8		T1	65		T12	16
bins_for_gpio_bits[14]	auto[1]	auto[0]	194456	1			T26	8		T1	65		T12	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	4516065	1			T25	18643		T26	66		T27	37
bins_for_gpio_bits[15]	auto[0]	auto[0]	6443910	1			T25	17423		T26	131		T27	76
bins_for_gpio_bits[15]	auto[0]	auto[1]	194973	1			T26	9		T1	62		T12	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	195233	1			T26	10		T1	63		T12	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	4517233	1			T25	19247		T26	68		T27	27
bins_for_gpio_bits[16]	auto[0]	auto[0]	6447337	1			T25	17548		T26	120		T27	45
bins_for_gpio_bits[16]	auto[0]	auto[1]	194604	1			T26	7		T1	65		T12	26
bins_for_gpio_bits[16]	auto[1]	auto[0]	194836	1			T26	7		T1	66		T12	26
bins_for_gpio_bits[16]	auto[1]	auto[1]	4514572	1			T25	19122		T26	84		T27	58
bins_for_gpio_bits[17]	auto[0]	auto[0]	6446021	1			T25	18248		T26	126		T27	77
bins_for_gpio_bits[17]	auto[0]	auto[1]	195083	1			T26	9		T1	59		T12	19
bins_for_gpio_bits[17]	auto[1]	auto[0]	195342	1			T26	9		T1	59		T12	19
bins_for_gpio_bits[17]	auto[1]	auto[1]	4514903	1			T25	18422		T26	74		T27	26
bins_for_gpio_bits[18]	auto[0]	auto[0]	6444967	1			T25	17404		T26	137		T27	44
bins_for_gpio_bits[18]	auto[0]	auto[1]	194941	1			T26	5		T1	64		T12	23
bins_for_gpio_bits[18]	auto[1]	auto[0]	195188	1			T26	5		T1	64		T12	23
bins_for_gpio_bits[18]	auto[1]	auto[1]	4516253	1			T25	19266		T26	71		T27	59
bins_for_gpio_bits[19]	auto[0]	auto[0]	6443355	1			T25	17361		T26	127		T27	34
bins_for_gpio_bits[19]	auto[0]	auto[1]	194804	1			T26	6		T1	61		T12	22
bins_for_gpio_bits[19]	auto[1]	auto[0]	195051	1			T26	6		T1	62		T12	22
bins_for_gpio_bits[19]	auto[1]	auto[1]	4518139	1			T25	19309		T26	79		T27	69
bins_for_gpio_bits[20]	auto[0]	auto[0]	6447793	1			T25	18884		T26	119		T27	42
bins_for_gpio_bits[20]	auto[0]	auto[1]	195159	1			T26	8		T1	75		T12	18
bins_for_gpio_bits[20]	auto[1]	auto[0]	195417	1			T26	8		T1	75		T12	18
bins_for_gpio_bits[20]	auto[1]	auto[1]	4512980	1			T25	17786		T26	83		T27	61
bins_for_gpio_bits[21]	auto[0]	auto[0]	6444870	1			T25	17747		T26	124		T27	31
bins_for_gpio_bits[21]	auto[0]	auto[1]	194602	1			T26	7		T1	66		T12	16
bins_for_gpio_bits[21]	auto[1]	auto[0]	194832	1			T26	7		T1	67		T12	16
bins_for_gpio_bits[21]	auto[1]	auto[1]	4517045	1			T25	18923		T26	80		T27	72
bins_for_gpio_bits[22]	auto[0]	auto[0]	6450460	1			T25	17033		T26	129		T27	59
bins_for_gpio_bits[22]	auto[0]	auto[1]	194776	1			T26	7		T1	58		T12	15
bins_for_gpio_bits[22]	auto[1]	auto[0]	194982	1			T26	7		T1	59		T12	15
bins_for_gpio_bits[22]	auto[1]	auto[1]	4511131	1			T25	19637		T26	75		T27	44
bins_for_gpio_bits[23]	auto[0]	auto[0]	6457696	1			T25	18791		T26	154		T27	81
bins_for_gpio_bits[23]	auto[0]	auto[1]	194830	1			T26	3		T1	73		T12	13
bins_for_gpio_bits[23]	auto[1]	auto[0]	195039	1			T26	4		T1	73		T12	13
bins_for_gpio_bits[23]	auto[1]	auto[1]	4503784	1			T25	17879		T26	57		T27	22
bins_for_gpio_bits[24]	auto[0]	auto[0]	6448847	1			T25	18459		T26	138		T27	50
bins_for_gpio_bits[24]	auto[0]	auto[1]	194559	1			T26	7		T1	63		T12	17
bins_for_gpio_bits[24]	auto[1]	auto[0]	194782	1			T26	7		T1	64		T12	17
bins_for_gpio_bits[24]	auto[1]	auto[1]	4513161	1			T25	18211		T26	66		T27	53
bins_for_gpio_bits[25]	auto[0]	auto[0]	6440366	1			T25	17641		T26	141		T27	57
bins_for_gpio_bits[25]	auto[0]	auto[1]	195188	1			T26	5		T1	62		T12	15
bins_for_gpio_bits[25]	auto[1]	auto[0]	195416	1			T26	6		T1	62		T12	15
bins_for_gpio_bits[25]	auto[1]	auto[1]	4520379	1			T25	19029		T26	66		T27	46
bins_for_gpio_bits[26]	auto[0]	auto[0]	6447121	1			T25	17966		T26	110		T27	69
bins_for_gpio_bits[26]	auto[0]	auto[1]	194110	1			T26	8		T1	68		T12	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	194388	1			T26	9		T1	69		T12	22
bins_for_gpio_bits[26]	auto[1]	auto[1]	4515730	1			T25	18704		T26	91		T27	34
bins_for_gpio_bits[27]	auto[0]	auto[0]	6450170	1			T25	17749		T26	136		T27	49
bins_for_gpio_bits[27]	auto[0]	auto[1]	195196	1			T26	5		T1	61		T12	19
bins_for_gpio_bits[27]	auto[1]	auto[0]	195472	1			T26	5		T1	61		T12	19
bins_for_gpio_bits[27]	auto[1]	auto[1]	4510511	1			T25	18921		T26	72		T27	54
bins_for_gpio_bits[28]	auto[0]	auto[0]	6454162	1			T25	17906		T26	124		T27	18
bins_for_gpio_bits[28]	auto[0]	auto[1]	195363	1			T26	4		T1	62		T12	22
bins_for_gpio_bits[28]	auto[1]	auto[0]	195604	1			T26	5		T1	63		T12	22
bins_for_gpio_bits[28]	auto[1]	auto[1]	4506220	1			T25	18764		T26	85		T27	85
bins_for_gpio_bits[29]	auto[0]	auto[0]	6442926	1			T25	17802		T26	116		T27	19
bins_for_gpio_bits[29]	auto[0]	auto[1]	195222	1			T26	5		T1	67		T12	17
bins_for_gpio_bits[29]	auto[1]	auto[0]	195456	1			T26	6		T1	67		T12	17
bins_for_gpio_bits[29]	auto[1]	auto[1]	4517745	1			T25	18868		T26	91		T27	84
bins_for_gpio_bits[30]	auto[0]	auto[0]	6431178	1			T25	18230		T26	134		T27	43
bins_for_gpio_bits[30]	auto[0]	auto[1]	195837	1			T26	5		T1	67		T12	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	196067	1			T26	6		T1	67		T12	18
bins_for_gpio_bits[30]	auto[1]	auto[1]	4528267	1			T25	18440		T26	73		T27	60
bins_for_gpio_bits[31]	auto[0]	auto[0]	6446120	1			T25	17536		T26	134		T27	45
bins_for_gpio_bits[31]	auto[0]	auto[1]	194633	1			T26	5		T1	53		T12	17
bins_for_gpio_bits[31]	auto[1]	auto[0]	194850	1			T26	5		T1	53		T12	17
bins_for_gpio_bits[31]	auto[1]	auto[1]	4515746	1			T25	19134		T26	74		T27	58