Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6844908 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
53 |
| auto[1] |
4644961 |
1 |
|
|
T27 |
12 |
|
T1 |
1134 |
|
T16 |
41090 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10899743 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
590126 |
1 |
|
|
T27 |
1 |
|
T1 |
43 |
|
T16 |
4562 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6861140 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
52 |
| auto[1] |
4628729 |
1 |
|
|
T27 |
13 |
|
T1 |
1019 |
|
T16 |
43122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2021409 |
1 |
|
|
T27 |
6 |
|
T1 |
476 |
|
T16 |
19339 |
| auto[1] |
auto[0] |
auto[1] |
295425 |
1 |
|
|
T1 |
20 |
|
T16 |
2292 |
|
T17 |
117 |
| auto[1] |
auto[1] |
auto[0] |
2017194 |
1 |
|
|
T27 |
6 |
|
T1 |
500 |
|
T16 |
19221 |
| auto[1] |
auto[1] |
auto[1] |
294701 |
1 |
|
|
T27 |
1 |
|
T1 |
23 |
|
T16 |
2270 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6835811 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
51 |
| auto[1] |
4654058 |
1 |
|
|
T27 |
14 |
|
T1 |
1094 |
|
T16 |
41389 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10896044 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
593825 |
1 |
|
|
T27 |
1 |
|
T1 |
37 |
|
T16 |
4057 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6838689 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
45 |
| auto[1] |
4651180 |
1 |
|
|
T27 |
20 |
|
T1 |
1078 |
|
T16 |
39144 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2032803 |
1 |
|
|
T27 |
19 |
|
T1 |
504 |
|
T16 |
17235 |
| auto[1] |
auto[0] |
auto[1] |
296911 |
1 |
|
|
T27 |
1 |
|
T1 |
17 |
|
T16 |
1937 |
| auto[1] |
auto[1] |
auto[0] |
2024552 |
1 |
|
|
T1 |
537 |
|
T16 |
17852 |
|
T17 |
245 |
| auto[1] |
auto[1] |
auto[1] |
296914 |
1 |
|
|
T1 |
20 |
|
T16 |
2120 |
|
T17 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6791891 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
55 |
| auto[1] |
4697978 |
1 |
|
|
T27 |
10 |
|
T1 |
1035 |
|
T16 |
40540 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10898807 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
63 |
| auto[1] |
591062 |
1 |
|
|
T27 |
2 |
|
T1 |
41 |
|
T16 |
4172 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6852950 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
40 |
| auto[1] |
4636919 |
1 |
|
|
T27 |
25 |
|
T1 |
1169 |
|
T16 |
40549 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2003037 |
1 |
|
|
T27 |
23 |
|
T1 |
559 |
|
T16 |
18287 |
| auto[1] |
auto[0] |
auto[1] |
292334 |
1 |
|
|
T27 |
2 |
|
T1 |
17 |
|
T16 |
2071 |
| auto[1] |
auto[1] |
auto[0] |
2042820 |
1 |
|
|
T1 |
569 |
|
T16 |
18090 |
|
T17 |
511 |
| auto[1] |
auto[1] |
auto[1] |
298728 |
1 |
|
|
T1 |
24 |
|
T16 |
2101 |
|
T17 |
113 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6830813 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
4659056 |
1 |
|
|
T1 |
1336 |
|
T16 |
42127 |
|
T17 |
1023 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10895316 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
594553 |
1 |
|
|
T1 |
37 |
|
T16 |
4139 |
|
T17 |
192 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6833534 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
55 |
| auto[1] |
4656335 |
1 |
|
|
T27 |
10 |
|
T1 |
1253 |
|
T16 |
39927 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2044306 |
1 |
|
|
T27 |
10 |
|
T1 |
528 |
|
T16 |
17319 |
| auto[1] |
auto[0] |
auto[1] |
299776 |
1 |
|
|
T1 |
15 |
|
T16 |
2016 |
|
T17 |
57 |
| auto[1] |
auto[1] |
auto[0] |
2017476 |
1 |
|
|
T1 |
688 |
|
T16 |
18469 |
|
T17 |
542 |
| auto[1] |
auto[1] |
auto[1] |
294777 |
1 |
|
|
T1 |
22 |
|
T16 |
2123 |
|
T17 |
135 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6864902 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
57 |
| auto[1] |
4624967 |
1 |
|
|
T27 |
8 |
|
T1 |
1114 |
|
T16 |
39854 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10896247 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
593622 |
1 |
|
|
T1 |
37 |
|
T16 |
3932 |
|
T17 |
141 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6828933 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
59 |
| auto[1] |
4660936 |
1 |
|
|
T27 |
6 |
|
T1 |
1065 |
|
T16 |
39810 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2044129 |
1 |
|
|
T27 |
6 |
|
T1 |
512 |
|
T16 |
18825 |
| auto[1] |
auto[0] |
auto[1] |
297903 |
1 |
|
|
T1 |
16 |
|
T16 |
2023 |
|
T17 |
118 |
| auto[1] |
auto[1] |
auto[0] |
2023185 |
1 |
|
|
T1 |
516 |
|
T16 |
17053 |
|
T17 |
102 |
| auto[1] |
auto[1] |
auto[1] |
295719 |
1 |
|
|
T1 |
21 |
|
T16 |
1909 |
|
T17 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6832279 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
55 |
| auto[1] |
4657590 |
1 |
|
|
T27 |
10 |
|
T1 |
1148 |
|
T16 |
40658 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10897121 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
592748 |
1 |
|
|
T1 |
39 |
|
T16 |
4160 |
|
T17 |
124 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6842973 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
50 |
| auto[1] |
4646896 |
1 |
|
|
T27 |
15 |
|
T1 |
1122 |
|
T16 |
40667 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2027781 |
1 |
|
|
T27 |
11 |
|
T1 |
466 |
|
T16 |
18375 |
| auto[1] |
auto[0] |
auto[1] |
296569 |
1 |
|
|
T1 |
15 |
|
T16 |
2030 |
|
T17 |
64 |
| auto[1] |
auto[1] |
auto[0] |
2026367 |
1 |
|
|
T27 |
4 |
|
T1 |
617 |
|
T16 |
18132 |
| auto[1] |
auto[1] |
auto[1] |
296179 |
1 |
|
|
T1 |
24 |
|
T16 |
2130 |
|
T17 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6832468 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
46 |
| auto[1] |
4657401 |
1 |
|
|
T27 |
19 |
|
T1 |
1094 |
|
T16 |
40857 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10895620 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
594249 |
1 |
|
|
T27 |
1 |
|
T1 |
28 |
|
T16 |
4224 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6834958 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
40 |
| auto[1] |
4654911 |
1 |
|
|
T27 |
25 |
|
T1 |
958 |
|
T16 |
40643 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2020817 |
1 |
|
|
T27 |
18 |
|
T1 |
466 |
|
T16 |
18687 |
| auto[1] |
auto[0] |
auto[1] |
295951 |
1 |
|
|
T1 |
14 |
|
T16 |
2165 |
|
T17 |
48 |
| auto[1] |
auto[1] |
auto[0] |
2039845 |
1 |
|
|
T27 |
6 |
|
T1 |
464 |
|
T16 |
17732 |
| auto[1] |
auto[1] |
auto[1] |
298298 |
1 |
|
|
T27 |
1 |
|
T1 |
14 |
|
T16 |
2059 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6825453 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
4664416 |
1 |
|
|
T1 |
1079 |
|
T16 |
42301 |
|
T17 |
999 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10896792 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
593077 |
1 |
|
|
T1 |
46 |
|
T16 |
4208 |
|
T17 |
125 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6841130 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
48 |
| auto[1] |
4648739 |
1 |
|
|
T27 |
17 |
|
T1 |
1144 |
|
T16 |
41302 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2028259 |
1 |
|
|
T27 |
17 |
|
T1 |
547 |
|
T16 |
17592 |
| auto[1] |
auto[0] |
auto[1] |
295747 |
1 |
|
|
T1 |
17 |
|
T16 |
1966 |
|
T17 |
48 |
| auto[1] |
auto[1] |
auto[0] |
2027403 |
1 |
|
|
T1 |
551 |
|
T16 |
19502 |
|
T17 |
315 |
| auto[1] |
auto[1] |
auto[1] |
297330 |
1 |
|
|
T1 |
29 |
|
T16 |
2242 |
|
T17 |
77 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6833255 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
4656614 |
1 |
|
|
T27 |
3 |
|
T1 |
896 |
|
T16 |
41243 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10891910 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
597959 |
1 |
|
|
T1 |
32 |
|
T16 |
4141 |
|
T17 |
136 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6814194 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
56 |
| auto[1] |
4675675 |
1 |
|
|
T27 |
9 |
|
T1 |
860 |
|
T16 |
40232 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2052948 |
1 |
|
|
T27 |
9 |
|
T1 |
548 |
|
T16 |
18210 |
| auto[1] |
auto[0] |
auto[1] |
302200 |
1 |
|
|
T1 |
17 |
|
T16 |
2143 |
|
T17 |
115 |
| auto[1] |
auto[1] |
auto[0] |
2024768 |
1 |
|
|
T1 |
280 |
|
T16 |
17881 |
|
T17 |
105 |
| auto[1] |
auto[1] |
auto[1] |
295759 |
1 |
|
|
T1 |
15 |
|
T16 |
1998 |
|
T17 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6824937 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
63 |
| auto[1] |
4664932 |
1 |
|
|
T27 |
2 |
|
T1 |
1147 |
|
T16 |
40595 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10894374 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
595495 |
1 |
|
|
T1 |
38 |
|
T16 |
4251 |
|
T17 |
133 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6831495 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
59 |
| auto[1] |
4658374 |
1 |
|
|
T27 |
6 |
|
T1 |
991 |
|
T16 |
40395 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2024267 |
1 |
|
|
T27 |
6 |
|
T1 |
444 |
|
T16 |
18305 |
| auto[1] |
auto[0] |
auto[1] |
296228 |
1 |
|
|
T1 |
15 |
|
T16 |
2093 |
|
T17 |
70 |
| auto[1] |
auto[1] |
auto[0] |
2038612 |
1 |
|
|
T1 |
509 |
|
T16 |
17839 |
|
T17 |
241 |
| auto[1] |
auto[1] |
auto[1] |
299267 |
1 |
|
|
T1 |
23 |
|
T16 |
2158 |
|
T17 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6843690 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
4646179 |
1 |
|
|
T27 |
3 |
|
T1 |
1074 |
|
T16 |
41737 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10897608 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
592261 |
1 |
|
|
T27 |
1 |
|
T1 |
35 |
|
T16 |
4327 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6845762 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
52 |
| auto[1] |
4644107 |
1 |
|
|
T27 |
13 |
|
T1 |
971 |
|
T16 |
40792 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2026373 |
1 |
|
|
T27 |
12 |
|
T1 |
448 |
|
T16 |
17676 |
| auto[1] |
auto[0] |
auto[1] |
296800 |
1 |
|
|
T27 |
1 |
|
T1 |
19 |
|
T16 |
2083 |
| auto[1] |
auto[1] |
auto[0] |
2025473 |
1 |
|
|
T1 |
488 |
|
T16 |
18789 |
|
T17 |
317 |
| auto[1] |
auto[1] |
auto[1] |
295461 |
1 |
|
|
T1 |
16 |
|
T16 |
2244 |
|
T17 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6840409 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
54 |
| auto[1] |
4649460 |
1 |
|
|
T27 |
11 |
|
T1 |
1123 |
|
T16 |
38829 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10899138 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
590731 |
1 |
|
|
T1 |
35 |
|
T16 |
4384 |
|
T17 |
138 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6851435 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
61 |
| auto[1] |
4638434 |
1 |
|
|
T27 |
4 |
|
T1 |
906 |
|
T16 |
41570 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2031975 |
1 |
|
|
T27 |
4 |
|
T1 |
418 |
|
T16 |
19612 |
| auto[1] |
auto[0] |
auto[1] |
296985 |
1 |
|
|
T1 |
20 |
|
T16 |
2492 |
|
T17 |
92 |
| auto[1] |
auto[1] |
auto[0] |
2015728 |
1 |
|
|
T1 |
453 |
|
T16 |
17574 |
|
T17 |
195 |
| auto[1] |
auto[1] |
auto[1] |
293746 |
1 |
|
|
T1 |
15 |
|
T16 |
1892 |
|
T17 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6867204 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
51 |
| auto[1] |
4622665 |
1 |
|
|
T27 |
14 |
|
T1 |
1265 |
|
T16 |
40398 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10892568 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
597301 |
1 |
|
|
T27 |
1 |
|
T1 |
42 |
|
T16 |
4046 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6814162 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
52 |
| auto[1] |
4675707 |
1 |
|
|
T27 |
13 |
|
T1 |
1100 |
|
T16 |
40692 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2058741 |
1 |
|
|
T27 |
6 |
|
T1 |
443 |
|
T16 |
18256 |
| auto[1] |
auto[0] |
auto[1] |
302039 |
1 |
|
|
T1 |
14 |
|
T16 |
2032 |
|
T17 |
65 |
| auto[1] |
auto[1] |
auto[0] |
2019665 |
1 |
|
|
T27 |
6 |
|
T1 |
615 |
|
T16 |
18390 |
| auto[1] |
auto[1] |
auto[1] |
295262 |
1 |
|
|
T27 |
1 |
|
T1 |
28 |
|
T16 |
2014 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6833103 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
63 |
| auto[1] |
4656766 |
1 |
|
|
T27 |
2 |
|
T1 |
941 |
|
T16 |
40127 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10898794 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
591075 |
1 |
|
|
T27 |
1 |
|
T1 |
43 |
|
T16 |
4546 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6859795 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
39 |
| auto[1] |
4630074 |
1 |
|
|
T27 |
26 |
|
T1 |
1073 |
|
T16 |
42112 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2012581 |
1 |
|
|
T27 |
25 |
|
T1 |
581 |
|
T16 |
19198 |
| auto[1] |
auto[0] |
auto[1] |
294872 |
1 |
|
|
T27 |
1 |
|
T1 |
23 |
|
T16 |
2412 |
| auto[1] |
auto[1] |
auto[0] |
2026418 |
1 |
|
|
T1 |
449 |
|
T16 |
18368 |
|
T17 |
362 |
| auto[1] |
auto[1] |
auto[1] |
296203 |
1 |
|
|
T1 |
20 |
|
T16 |
2134 |
|
T17 |
92 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6839417 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
49 |
| auto[1] |
4650452 |
1 |
|
|
T27 |
16 |
|
T1 |
940 |
|
T16 |
40465 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10892738 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
63 |
| auto[1] |
597131 |
1 |
|
|
T27 |
2 |
|
T1 |
49 |
|
T16 |
4147 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6815408 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
30 |
| auto[1] |
4674461 |
1 |
|
|
T27 |
35 |
|
T1 |
1265 |
|
T16 |
39893 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2045459 |
1 |
|
|
T27 |
23 |
|
T1 |
679 |
|
T16 |
17935 |
| auto[1] |
auto[0] |
auto[1] |
299358 |
1 |
|
|
T27 |
1 |
|
T1 |
33 |
|
T16 |
2053 |
| auto[1] |
auto[1] |
auto[0] |
2031871 |
1 |
|
|
T27 |
10 |
|
T1 |
537 |
|
T16 |
17811 |
| auto[1] |
auto[1] |
auto[1] |
297773 |
1 |
|
|
T27 |
1 |
|
T1 |
16 |
|
T16 |
2094 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6812722 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
4677147 |
1 |
|
|
T1 |
1065 |
|
T16 |
40549 |
|
T17 |
922 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10896744 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
593125 |
1 |
|
|
T1 |
29 |
|
T16 |
4136 |
|
T17 |
179 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6840644 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
52 |
| auto[1] |
4649225 |
1 |
|
|
T27 |
13 |
|
T1 |
977 |
|
T16 |
40497 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2027993 |
1 |
|
|
T27 |
13 |
|
T1 |
450 |
|
T16 |
17896 |
| auto[1] |
auto[0] |
auto[1] |
296727 |
1 |
|
|
T1 |
15 |
|
T16 |
2051 |
|
T17 |
66 |
| auto[1] |
auto[1] |
auto[0] |
2028107 |
1 |
|
|
T1 |
498 |
|
T16 |
18465 |
|
T17 |
446 |
| auto[1] |
auto[1] |
auto[1] |
296398 |
1 |
|
|
T1 |
14 |
|
T16 |
2085 |
|
T17 |
113 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6844657 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
46 |
| auto[1] |
4645212 |
1 |
|
|
T27 |
19 |
|
T1 |
1102 |
|
T16 |
39866 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10897769 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
63 |
| auto[1] |
592100 |
1 |
|
|
T27 |
2 |
|
T1 |
40 |
|
T16 |
4067 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6843929 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
36 |
| auto[1] |
4645940 |
1 |
|
|
T27 |
29 |
|
T1 |
1074 |
|
T16 |
40149 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2046840 |
1 |
|
|
T27 |
16 |
|
T1 |
544 |
|
T16 |
18166 |
| auto[1] |
auto[0] |
auto[1] |
298999 |
1 |
|
|
T27 |
2 |
|
T1 |
21 |
|
T16 |
1973 |
| auto[1] |
auto[1] |
auto[0] |
2007000 |
1 |
|
|
T27 |
11 |
|
T1 |
490 |
|
T16 |
17916 |
| auto[1] |
auto[1] |
auto[1] |
293101 |
1 |
|
|
T1 |
19 |
|
T16 |
2094 |
|
T17 |
58 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6823115 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
51 |
| auto[1] |
4666754 |
1 |
|
|
T27 |
14 |
|
T1 |
970 |
|
T16 |
42103 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10897659 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
592210 |
1 |
|
|
T1 |
44 |
|
T16 |
3957 |
|
T17 |
188 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6840340 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
43 |
| auto[1] |
4649529 |
1 |
|
|
T27 |
22 |
|
T1 |
1114 |
|
T16 |
39721 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2020489 |
1 |
|
|
T27 |
22 |
|
T1 |
580 |
|
T16 |
17271 |
| auto[1] |
auto[0] |
auto[1] |
294043 |
1 |
|
|
T1 |
22 |
|
T16 |
1819 |
|
T17 |
78 |
| auto[1] |
auto[1] |
auto[0] |
2036830 |
1 |
|
|
T1 |
490 |
|
T16 |
18493 |
|
T17 |
453 |
| auto[1] |
auto[1] |
auto[1] |
298167 |
1 |
|
|
T1 |
22 |
|
T16 |
2138 |
|
T17 |
110 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6849186 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
48 |
| auto[1] |
4640683 |
1 |
|
|
T27 |
17 |
|
T1 |
1012 |
|
T16 |
40929 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10894832 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
595037 |
1 |
|
|
T1 |
35 |
|
T16 |
4091 |
|
T17 |
183 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6835374 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
45 |
| auto[1] |
4654495 |
1 |
|
|
T27 |
20 |
|
T1 |
1087 |
|
T16 |
40215 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2030697 |
1 |
|
|
T27 |
20 |
|
T1 |
591 |
|
T16 |
18369 |
| auto[1] |
auto[0] |
auto[1] |
297238 |
1 |
|
|
T1 |
18 |
|
T16 |
2138 |
|
T17 |
103 |
| auto[1] |
auto[1] |
auto[0] |
2028761 |
1 |
|
|
T1 |
461 |
|
T16 |
17755 |
|
T17 |
377 |
| auto[1] |
auto[1] |
auto[1] |
297799 |
1 |
|
|
T1 |
17 |
|
T16 |
1953 |
|
T17 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6864176 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
4625693 |
1 |
|
|
T1 |
1018 |
|
T16 |
39293 |
|
T17 |
776 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10896291 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
593578 |
1 |
|
|
T1 |
58 |
|
T16 |
4099 |
|
T17 |
182 |