Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6847974 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
60 |
| auto[1] |
4641895 |
1 |
|
|
T27 |
5 |
|
T1 |
1207 |
|
T16 |
40550 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10901357 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
588512 |
1 |
|
|
T1 |
35 |
|
T16 |
4349 |
|
T17 |
140 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6869575 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
57 |
| auto[1] |
4620294 |
1 |
|
|
T27 |
8 |
|
T1 |
1072 |
|
T16 |
41992 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2014464 |
1 |
|
|
T27 |
8 |
|
T1 |
518 |
|
T16 |
19017 |
| auto[1] |
auto[0] |
auto[1] |
293569 |
1 |
|
|
T1 |
20 |
|
T16 |
2168 |
|
T17 |
55 |
| auto[1] |
auto[1] |
auto[0] |
2017318 |
1 |
|
|
T1 |
519 |
|
T16 |
18626 |
|
T17 |
355 |
| auto[1] |
auto[1] |
auto[1] |
294943 |
1 |
|
|
T1 |
15 |
|
T16 |
2181 |
|
T17 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |