Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6819014 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
58 |
| auto[1] |
4670855 |
1 |
|
|
T27 |
7 |
|
T1 |
1074 |
|
T16 |
42356 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10900089 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
589780 |
1 |
|
|
T27 |
1 |
|
T1 |
30 |
|
T16 |
4208 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6855241 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
34 |
| auto[1] |
4634628 |
1 |
|
|
T27 |
31 |
|
T1 |
1112 |
|
T16 |
40882 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2019956 |
1 |
|
|
T27 |
30 |
|
T1 |
589 |
|
T16 |
16986 |
| auto[1] |
auto[0] |
auto[1] |
294387 |
1 |
|
|
T27 |
1 |
|
T1 |
16 |
|
T16 |
1866 |
| auto[1] |
auto[1] |
auto[0] |
2024892 |
1 |
|
|
T1 |
493 |
|
T16 |
19688 |
|
T17 |
243 |
| auto[1] |
auto[1] |
auto[1] |
295393 |
1 |
|
|
T1 |
14 |
|
T16 |
2342 |
|
T17 |
70 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |