Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6824976 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
4664893 |
1 |
|
|
T1 |
1199 |
|
T16 |
38981 |
|
T17 |
446 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10897044 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
592825 |
1 |
|
|
T1 |
50 |
|
T16 |
4098 |
|
T17 |
143 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6841808 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
48 |
| auto[1] |
4648061 |
1 |
|
|
T27 |
17 |
|
T1 |
1233 |
|
T16 |
40640 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2047862 |
1 |
|
|
T27 |
17 |
|
T1 |
529 |
|
T16 |
19448 |
| auto[1] |
auto[0] |
auto[1] |
300113 |
1 |
|
|
T1 |
20 |
|
T16 |
2280 |
|
T17 |
100 |
| auto[1] |
auto[1] |
auto[0] |
2007374 |
1 |
|
|
T1 |
654 |
|
T16 |
17094 |
|
T17 |
171 |
| auto[1] |
auto[1] |
auto[1] |
292712 |
1 |
|
|
T1 |
30 |
|
T16 |
1818 |
|
T17 |
43 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |