Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6831695 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
4658174 |
1 |
|
|
T1 |
988 |
|
T16 |
43210 |
|
T17 |
1056 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10890904 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
598965 |
1 |
|
|
T1 |
41 |
|
T16 |
4424 |
|
T17 |
176 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6801601 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
58 |
| auto[1] |
4688268 |
1 |
|
|
T27 |
7 |
|
T1 |
1221 |
|
T16 |
42039 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2041950 |
1 |
|
|
T27 |
7 |
|
T1 |
633 |
|
T16 |
17519 |
| auto[1] |
auto[0] |
auto[1] |
298516 |
1 |
|
|
T1 |
21 |
|
T16 |
1992 |
|
T17 |
58 |
| auto[1] |
auto[1] |
auto[0] |
2047353 |
1 |
|
|
T1 |
547 |
|
T16 |
20096 |
|
T17 |
448 |
| auto[1] |
auto[1] |
auto[1] |
300449 |
1 |
|
|
T1 |
20 |
|
T16 |
2432 |
|
T17 |
118 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |