Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6831609 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
60 |
| auto[1] |
4658260 |
1 |
|
|
T27 |
5 |
|
T1 |
1014 |
|
T16 |
40932 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10894002 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
595867 |
1 |
|
|
T27 |
1 |
|
T1 |
52 |
|
T16 |
4577 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6818838 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
54 |
| auto[1] |
4671031 |
1 |
|
|
T27 |
11 |
|
T1 |
1139 |
|
T16 |
42509 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2033702 |
1 |
|
|
T27 |
10 |
|
T1 |
541 |
|
T16 |
19346 |
| auto[1] |
auto[0] |
auto[1] |
296926 |
1 |
|
|
T27 |
1 |
|
T1 |
29 |
|
T16 |
2391 |
| auto[1] |
auto[1] |
auto[0] |
2041462 |
1 |
|
|
T1 |
546 |
|
T16 |
18586 |
|
T17 |
290 |
| auto[1] |
auto[1] |
auto[1] |
298941 |
1 |
|
|
T1 |
23 |
|
T16 |
2186 |
|
T17 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |