Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6844908 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
53 |
| auto[1] |
4644961 |
1 |
|
|
T27 |
12 |
|
T1 |
1134 |
|
T16 |
41090 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9542425 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
1947444 |
1 |
|
|
T1 |
228 |
|
T16 |
14791 |
|
T17 |
307 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6843027 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
4646842 |
1 |
|
|
T27 |
3 |
|
T1 |
1147 |
|
T16 |
40880 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1357786 |
1 |
|
|
T27 |
3 |
|
T1 |
434 |
|
T16 |
13212 |
| auto[1] |
auto[0] |
auto[1] |
978539 |
1 |
|
|
T1 |
107 |
|
T16 |
7527 |
|
T17 |
139 |
| auto[1] |
auto[1] |
auto[0] |
1341612 |
1 |
|
|
T1 |
485 |
|
T16 |
12877 |
|
T17 |
152 |
| auto[1] |
auto[1] |
auto[1] |
968905 |
1 |
|
|
T1 |
121 |
|
T16 |
7264 |
|
T17 |
168 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |