Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6835811 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
51 |
| auto[1] |
4654058 |
1 |
|
|
T27 |
14 |
|
T1 |
1094 |
|
T16 |
41389 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9531969 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
1957900 |
1 |
|
|
T1 |
195 |
|
T16 |
13672 |
|
T17 |
390 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6815840 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
56 |
| auto[1] |
4674029 |
1 |
|
|
T27 |
9 |
|
T1 |
1096 |
|
T16 |
39668 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1356417 |
1 |
|
|
T27 |
9 |
|
T1 |
477 |
|
T16 |
12644 |
| auto[1] |
auto[0] |
auto[1] |
977283 |
1 |
|
|
T1 |
89 |
|
T16 |
6691 |
|
T17 |
191 |
| auto[1] |
auto[1] |
auto[0] |
1359712 |
1 |
|
|
T1 |
424 |
|
T16 |
13352 |
|
T17 |
243 |
| auto[1] |
auto[1] |
auto[1] |
980617 |
1 |
|
|
T1 |
106 |
|
T16 |
6981 |
|
T17 |
199 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |