Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6791891 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
55 |
| auto[1] |
4697978 |
1 |
|
|
T27 |
10 |
|
T1 |
1035 |
|
T16 |
40540 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9533549 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
58 |
| auto[1] |
1956320 |
1 |
|
|
T27 |
7 |
|
T1 |
215 |
|
T16 |
14063 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6835941 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
51 |
| auto[1] |
4653928 |
1 |
|
|
T27 |
14 |
|
T1 |
912 |
|
T16 |
39838 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1334078 |
1 |
|
|
T27 |
7 |
|
T1 |
397 |
|
T16 |
13074 |
| auto[1] |
auto[0] |
auto[1] |
971147 |
1 |
|
|
T27 |
7 |
|
T1 |
105 |
|
T16 |
6906 |
| auto[1] |
auto[1] |
auto[0] |
1363530 |
1 |
|
|
T1 |
300 |
|
T16 |
12701 |
|
T17 |
277 |
| auto[1] |
auto[1] |
auto[1] |
985173 |
1 |
|
|
T1 |
110 |
|
T16 |
7157 |
|
T17 |
274 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |