Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6830813 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
4659056 |
1 |
|
|
T1 |
1336 |
|
T16 |
42127 |
|
T17 |
1023 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9528873 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
1960996 |
1 |
|
|
T1 |
129 |
|
T16 |
14156 |
|
T17 |
257 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6818079 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
60 |
| auto[1] |
4671790 |
1 |
|
|
T27 |
5 |
|
T1 |
859 |
|
T16 |
40527 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1350954 |
1 |
|
|
T27 |
5 |
|
T1 |
302 |
|
T16 |
12725 |
| auto[1] |
auto[0] |
auto[1] |
980325 |
1 |
|
|
T1 |
45 |
|
T16 |
6942 |
|
T17 |
128 |
| auto[1] |
auto[1] |
auto[0] |
1359840 |
1 |
|
|
T1 |
428 |
|
T16 |
13646 |
|
T17 |
134 |
| auto[1] |
auto[1] |
auto[1] |
980671 |
1 |
|
|
T1 |
84 |
|
T16 |
7214 |
|
T17 |
129 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |