Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6864902 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
57 |
| auto[1] |
4624967 |
1 |
|
|
T27 |
8 |
|
T1 |
1114 |
|
T16 |
39854 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9545738 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
52 |
| auto[1] |
1944131 |
1 |
|
|
T27 |
13 |
|
T1 |
231 |
|
T16 |
14703 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6860972 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
43 |
| auto[1] |
4628897 |
1 |
|
|
T27 |
22 |
|
T1 |
1112 |
|
T16 |
41274 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1348391 |
1 |
|
|
T27 |
9 |
|
T1 |
398 |
|
T16 |
13704 |
| auto[1] |
auto[0] |
auto[1] |
970435 |
1 |
|
|
T27 |
13 |
|
T1 |
132 |
|
T16 |
7380 |
| auto[1] |
auto[1] |
auto[0] |
1336375 |
1 |
|
|
T1 |
483 |
|
T16 |
12867 |
|
T17 |
165 |
| auto[1] |
auto[1] |
auto[1] |
973696 |
1 |
|
|
T1 |
99 |
|
T16 |
7323 |
|
T17 |
182 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |