Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6831276 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
59 |
| auto[1] |
4658593 |
1 |
|
|
T27 |
6 |
|
T1 |
1341 |
|
T16 |
39782 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2044202 |
1 |
|
|
T27 |
6 |
|
T1 |
682 |
|
T16 |
18624 |
| auto[1] |
auto[0] |
auto[1] |
298345 |
1 |
|
|
T1 |
28 |
|
T16 |
2152 |
|
T17 |
83 |
| auto[1] |
auto[1] |
auto[0] |
2020813 |
1 |
|
|
T1 |
601 |
|
T16 |
17059 |
|
T17 |
361 |
| auto[1] |
auto[1] |
auto[1] |
295233 |
1 |
|
|
T1 |
30 |
|
T16 |
1947 |
|
T17 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |