Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6832468 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
46 |
| auto[1] |
4657401 |
1 |
|
|
T27 |
19 |
|
T1 |
1094 |
|
T16 |
40857 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9539947 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
1949922 |
1 |
|
|
T1 |
300 |
|
T16 |
14534 |
|
T17 |
340 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6829447 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
54 |
| auto[1] |
4660422 |
1 |
|
|
T27 |
11 |
|
T1 |
1159 |
|
T16 |
41474 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1358085 |
1 |
|
|
T27 |
11 |
|
T1 |
416 |
|
T16 |
13520 |
| auto[1] |
auto[0] |
auto[1] |
979699 |
1 |
|
|
T1 |
168 |
|
T16 |
7144 |
|
T17 |
149 |
| auto[1] |
auto[1] |
auto[0] |
1352415 |
1 |
|
|
T1 |
443 |
|
T16 |
13420 |
|
T17 |
201 |
| auto[1] |
auto[1] |
auto[1] |
970223 |
1 |
|
|
T1 |
132 |
|
T16 |
7390 |
|
T17 |
191 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |