Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6825453 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
4664416 |
1 |
|
|
T1 |
1079 |
|
T16 |
42301 |
|
T17 |
999 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9537816 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
1952053 |
1 |
|
|
T27 |
3 |
|
T1 |
193 |
|
T16 |
15129 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6852859 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
51 |
| auto[1] |
4637010 |
1 |
|
|
T27 |
14 |
|
T1 |
1031 |
|
T16 |
41912 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1338027 |
1 |
|
|
T27 |
11 |
|
T1 |
453 |
|
T16 |
12744 |
| auto[1] |
auto[0] |
auto[1] |
973195 |
1 |
|
|
T27 |
3 |
|
T1 |
129 |
|
T16 |
7130 |
| auto[1] |
auto[1] |
auto[0] |
1346930 |
1 |
|
|
T1 |
385 |
|
T16 |
14039 |
|
T17 |
320 |
| auto[1] |
auto[1] |
auto[1] |
978858 |
1 |
|
|
T1 |
64 |
|
T16 |
7999 |
|
T17 |
302 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |