Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6833255 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
4656614 |
1 |
|
|
T27 |
3 |
|
T1 |
896 |
|
T16 |
41243 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9538979 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
59 |
| auto[1] |
1950890 |
1 |
|
|
T27 |
6 |
|
T1 |
335 |
|
T16 |
13529 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6842856 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
54 |
| auto[1] |
4647013 |
1 |
|
|
T27 |
11 |
|
T1 |
1185 |
|
T16 |
38481 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1348352 |
1 |
|
|
T27 |
5 |
|
T1 |
475 |
|
T16 |
12348 |
| auto[1] |
auto[0] |
auto[1] |
973582 |
1 |
|
|
T27 |
6 |
|
T1 |
189 |
|
T16 |
6727 |
| auto[1] |
auto[1] |
auto[0] |
1347771 |
1 |
|
|
T1 |
375 |
|
T16 |
12604 |
|
T17 |
182 |
| auto[1] |
auto[1] |
auto[1] |
977308 |
1 |
|
|
T1 |
146 |
|
T16 |
6802 |
|
T17 |
152 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |