Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6824937 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
63 |
| auto[1] |
4664932 |
1 |
|
|
T27 |
2 |
|
T1 |
1147 |
|
T16 |
40595 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9536162 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
1953707 |
1 |
|
|
T27 |
3 |
|
T1 |
261 |
|
T16 |
14333 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6836269 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
51 |
| auto[1] |
4653600 |
1 |
|
|
T27 |
14 |
|
T1 |
1196 |
|
T16 |
41664 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1347115 |
1 |
|
|
T27 |
11 |
|
T1 |
452 |
|
T16 |
13344 |
| auto[1] |
auto[0] |
auto[1] |
976474 |
1 |
|
|
T27 |
3 |
|
T1 |
125 |
|
T16 |
6906 |
| auto[1] |
auto[1] |
auto[0] |
1352778 |
1 |
|
|
T1 |
483 |
|
T16 |
13987 |
|
T17 |
127 |
| auto[1] |
auto[1] |
auto[1] |
977233 |
1 |
|
|
T1 |
136 |
|
T16 |
7427 |
|
T17 |
157 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |