Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6840409 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
54 |
| auto[1] |
4649460 |
1 |
|
|
T27 |
11 |
|
T1 |
1123 |
|
T16 |
38829 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9542748 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
48 |
| auto[1] |
1947121 |
1 |
|
|
T27 |
17 |
|
T1 |
183 |
|
T16 |
13456 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6849512 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
47 |
| auto[1] |
4640357 |
1 |
|
|
T27 |
18 |
|
T1 |
955 |
|
T16 |
39592 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1359651 |
1 |
|
|
T27 |
1 |
|
T1 |
341 |
|
T16 |
13291 |
| auto[1] |
auto[0] |
auto[1] |
984635 |
1 |
|
|
T27 |
17 |
|
T1 |
111 |
|
T16 |
6985 |
| auto[1] |
auto[1] |
auto[0] |
1333585 |
1 |
|
|
T1 |
431 |
|
T16 |
12845 |
|
T17 |
199 |
| auto[1] |
auto[1] |
auto[1] |
962486 |
1 |
|
|
T1 |
72 |
|
T16 |
6471 |
|
T17 |
247 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |