Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6867204 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
51 |
| auto[1] |
4622665 |
1 |
|
|
T27 |
14 |
|
T1 |
1265 |
|
T16 |
40398 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9534370 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
1955499 |
1 |
|
|
T27 |
3 |
|
T1 |
300 |
|
T16 |
13824 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6828753 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
52 |
| auto[1] |
4661116 |
1 |
|
|
T27 |
13 |
|
T1 |
1274 |
|
T16 |
39357 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1362220 |
1 |
|
|
T27 |
7 |
|
T1 |
434 |
|
T16 |
13042 |
| auto[1] |
auto[0] |
auto[1] |
983048 |
1 |
|
|
T1 |
113 |
|
T16 |
7144 |
|
T17 |
359 |
| auto[1] |
auto[1] |
auto[0] |
1343397 |
1 |
|
|
T27 |
3 |
|
T1 |
540 |
|
T16 |
12491 |
| auto[1] |
auto[1] |
auto[1] |
972451 |
1 |
|
|
T27 |
3 |
|
T1 |
187 |
|
T16 |
6680 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |