Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6833103 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
63 |
| auto[1] |
4656766 |
1 |
|
|
T27 |
2 |
|
T1 |
941 |
|
T16 |
40127 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9542344 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
54 |
| auto[1] |
1947525 |
1 |
|
|
T27 |
11 |
|
T1 |
316 |
|
T16 |
14093 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6853926 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
52 |
| auto[1] |
4635943 |
1 |
|
|
T27 |
13 |
|
T1 |
1133 |
|
T16 |
40771 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1345155 |
1 |
|
|
T27 |
2 |
|
T1 |
485 |
|
T16 |
13543 |
| auto[1] |
auto[0] |
auto[1] |
978385 |
1 |
|
|
T27 |
11 |
|
T1 |
191 |
|
T16 |
7275 |
| auto[1] |
auto[1] |
auto[0] |
1343263 |
1 |
|
|
T1 |
332 |
|
T16 |
13135 |
|
T17 |
232 |
| auto[1] |
auto[1] |
auto[1] |
969140 |
1 |
|
|
T1 |
125 |
|
T16 |
6818 |
|
T17 |
197 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |