Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6839417 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
49 |
| auto[1] |
4650452 |
1 |
|
|
T27 |
16 |
|
T1 |
940 |
|
T16 |
40465 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9535193 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
56 |
| auto[1] |
1954676 |
1 |
|
|
T27 |
9 |
|
T1 |
274 |
|
T16 |
15035 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6837858 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
49 |
| auto[1] |
4652011 |
1 |
|
|
T27 |
16 |
|
T1 |
1215 |
|
T16 |
42428 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1352403 |
1 |
|
|
T27 |
4 |
|
T1 |
557 |
|
T16 |
13778 |
| auto[1] |
auto[0] |
auto[1] |
978207 |
1 |
|
|
T27 |
6 |
|
T1 |
167 |
|
T16 |
7446 |
| auto[1] |
auto[1] |
auto[0] |
1344932 |
1 |
|
|
T27 |
3 |
|
T1 |
384 |
|
T16 |
13615 |
| auto[1] |
auto[1] |
auto[1] |
976469 |
1 |
|
|
T27 |
3 |
|
T1 |
107 |
|
T16 |
7589 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |