Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6828973 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
46 |
| auto[1] |
4660896 |
1 |
|
|
T27 |
19 |
|
T1 |
759 |
|
T16 |
40585 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10896220 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
593649 |
1 |
|
|
T1 |
55 |
|
T16 |
4124 |
|
T17 |
134 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6841284 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
61 |
| auto[1] |
4648585 |
1 |
|
|
T27 |
4 |
|
T1 |
1362 |
|
T16 |
40765 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2023320 |
1 |
|
|
T1 |
859 |
|
T16 |
19114 |
|
T17 |
372 |
| auto[1] |
auto[0] |
auto[1] |
295556 |
1 |
|
|
T1 |
38 |
|
T16 |
2182 |
|
T17 |
89 |
| auto[1] |
auto[1] |
auto[0] |
2031616 |
1 |
|
|
T27 |
4 |
|
T1 |
448 |
|
T16 |
17527 |
| auto[1] |
auto[1] |
auto[1] |
298093 |
1 |
|
|
T1 |
17 |
|
T16 |
1942 |
|
T17 |
45 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |