Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6812722 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
4677147 |
1 |
|
|
T1 |
1065 |
|
T16 |
40549 |
|
T17 |
922 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9545085 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
63 |
| auto[1] |
1944784 |
1 |
|
|
T27 |
2 |
|
T1 |
239 |
|
T16 |
13417 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6868727 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
49 |
| auto[1] |
4621142 |
1 |
|
|
T27 |
16 |
|
T1 |
1143 |
|
T16 |
38708 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1331403 |
1 |
|
|
T27 |
14 |
|
T1 |
466 |
|
T16 |
12470 |
| auto[1] |
auto[0] |
auto[1] |
970904 |
1 |
|
|
T27 |
2 |
|
T1 |
111 |
|
T16 |
6839 |
| auto[1] |
auto[1] |
auto[0] |
1344955 |
1 |
|
|
T1 |
438 |
|
T16 |
12821 |
|
T17 |
299 |
| auto[1] |
auto[1] |
auto[1] |
973880 |
1 |
|
|
T1 |
128 |
|
T16 |
6578 |
|
T17 |
318 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |