Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6844657 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
46 |
| auto[1] |
4645212 |
1 |
|
|
T27 |
19 |
|
T1 |
1102 |
|
T16 |
39866 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9543237 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
1946632 |
1 |
|
|
T1 |
243 |
|
T16 |
14067 |
|
T17 |
445 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6845611 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
56 |
| auto[1] |
4644258 |
1 |
|
|
T27 |
9 |
|
T1 |
1154 |
|
T16 |
40110 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1350899 |
1 |
|
|
T27 |
3 |
|
T1 |
428 |
|
T16 |
13363 |
| auto[1] |
auto[0] |
auto[1] |
973423 |
1 |
|
|
T1 |
126 |
|
T16 |
7298 |
|
T17 |
279 |
| auto[1] |
auto[1] |
auto[0] |
1346727 |
1 |
|
|
T27 |
6 |
|
T1 |
483 |
|
T16 |
12680 |
| auto[1] |
auto[1] |
auto[1] |
973209 |
1 |
|
|
T1 |
117 |
|
T16 |
6769 |
|
T17 |
166 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |