Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6823115 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
51 |
| auto[1] |
4666754 |
1 |
|
|
T27 |
14 |
|
T1 |
970 |
|
T16 |
42103 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9538686 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
60 |
| auto[1] |
1951183 |
1 |
|
|
T27 |
5 |
|
T1 |
298 |
|
T16 |
14400 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6828815 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
57 |
| auto[1] |
4661054 |
1 |
|
|
T27 |
8 |
|
T1 |
1092 |
|
T16 |
41109 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1353109 |
1 |
|
|
T27 |
3 |
|
T1 |
424 |
|
T16 |
13366 |
| auto[1] |
auto[0] |
auto[1] |
975985 |
1 |
|
|
T27 |
5 |
|
T1 |
144 |
|
T16 |
7083 |
| auto[1] |
auto[1] |
auto[0] |
1356762 |
1 |
|
|
T1 |
370 |
|
T16 |
13343 |
|
T17 |
320 |
| auto[1] |
auto[1] |
auto[1] |
975198 |
1 |
|
|
T1 |
154 |
|
T16 |
7317 |
|
T17 |
283 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |