Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6821059 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
46 |
| auto[1] |
4668810 |
1 |
|
|
T27 |
19 |
|
T1 |
1227 |
|
T16 |
41628 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10893612 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
596257 |
1 |
|
|
T27 |
1 |
|
T1 |
47 |
|
T16 |
4627 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6819908 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
34 |
| auto[1] |
4669961 |
1 |
|
|
T27 |
31 |
|
T1 |
1120 |
|
T16 |
43357 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2042707 |
1 |
|
|
T27 |
23 |
|
T1 |
439 |
|
T16 |
19282 |
| auto[1] |
auto[0] |
auto[1] |
299417 |
1 |
|
|
T27 |
1 |
|
T1 |
17 |
|
T16 |
2268 |
| auto[1] |
auto[1] |
auto[0] |
2030997 |
1 |
|
|
T27 |
7 |
|
T1 |
634 |
|
T16 |
19448 |
| auto[1] |
auto[1] |
auto[1] |
296840 |
1 |
|
|
T1 |
30 |
|
T16 |
2359 |
|
T17 |
90 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |