Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6838637 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
58 |
| auto[1] |
4651232 |
1 |
|
|
T27 |
7 |
|
T1 |
1124 |
|
T16 |
40994 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10896874 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
592995 |
1 |
|
|
T1 |
48 |
|
T16 |
4248 |
|
T17 |
149 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6844165 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
50 |
| auto[1] |
4645704 |
1 |
|
|
T27 |
15 |
|
T1 |
1130 |
|
T16 |
41274 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2028834 |
1 |
|
|
T27 |
11 |
|
T1 |
491 |
|
T16 |
18428 |
| auto[1] |
auto[0] |
auto[1] |
296303 |
1 |
|
|
T1 |
20 |
|
T16 |
2115 |
|
T17 |
41 |
| auto[1] |
auto[1] |
auto[0] |
2023875 |
1 |
|
|
T27 |
4 |
|
T1 |
591 |
|
T16 |
18598 |
| auto[1] |
auto[1] |
auto[1] |
296692 |
1 |
|
|
T1 |
28 |
|
T16 |
2133 |
|
T17 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |