Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6814704 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
4675165 |
1 |
|
|
T27 |
3 |
|
T1 |
1133 |
|
T16 |
40932 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10895940 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
593929 |
1 |
|
|
T1 |
36 |
|
T16 |
4050 |
|
T17 |
167 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6844424 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
45 |
| auto[1] |
4645445 |
1 |
|
|
T27 |
20 |
|
T1 |
1182 |
|
T16 |
39963 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2006844 |
1 |
|
|
T27 |
20 |
|
T1 |
544 |
|
T16 |
18177 |
| auto[1] |
auto[0] |
auto[1] |
294024 |
1 |
|
|
T1 |
15 |
|
T16 |
2055 |
|
T17 |
61 |
| auto[1] |
auto[1] |
auto[0] |
2044672 |
1 |
|
|
T1 |
602 |
|
T16 |
17736 |
|
T17 |
439 |
| auto[1] |
auto[1] |
auto[1] |
299905 |
1 |
|
|
T1 |
21 |
|
T16 |
1995 |
|
T17 |
106 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |