Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6835282 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
4654587 |
1 |
|
|
T27 |
3 |
|
T1 |
1217 |
|
T16 |
40282 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10896149 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
65 |
| auto[1] |
593720 |
1 |
|
|
T1 |
38 |
|
T16 |
4308 |
|
T17 |
160 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6836223 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
57 |
| auto[1] |
4653646 |
1 |
|
|
T27 |
8 |
|
T1 |
1114 |
|
T16 |
41010 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2036874 |
1 |
|
|
T27 |
8 |
|
T1 |
472 |
|
T16 |
18265 |
| auto[1] |
auto[0] |
auto[1] |
297687 |
1 |
|
|
T1 |
14 |
|
T16 |
2225 |
|
T17 |
52 |
| auto[1] |
auto[1] |
auto[0] |
2023052 |
1 |
|
|
T1 |
604 |
|
T16 |
18437 |
|
T17 |
411 |
| auto[1] |
auto[1] |
auto[1] |
296033 |
1 |
|
|
T1 |
24 |
|
T16 |
2083 |
|
T17 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |