Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6812516 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
57 |
| auto[1] |
4677353 |
1 |
|
|
T27 |
8 |
|
T1 |
1111 |
|
T16 |
42664 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10896410 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
593459 |
1 |
|
|
T27 |
1 |
|
T1 |
29 |
|
T16 |
4251 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6833117 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
37 |
| auto[1] |
4656752 |
1 |
|
|
T27 |
28 |
|
T1 |
1051 |
|
T16 |
41375 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2029250 |
1 |
|
|
T27 |
23 |
|
T1 |
502 |
|
T16 |
17816 |
| auto[1] |
auto[0] |
auto[1] |
297205 |
1 |
|
|
T27 |
1 |
|
T1 |
13 |
|
T16 |
2071 |
| auto[1] |
auto[1] |
auto[0] |
2034043 |
1 |
|
|
T27 |
4 |
|
T1 |
520 |
|
T16 |
19308 |
| auto[1] |
auto[1] |
auto[1] |
296254 |
1 |
|
|
T1 |
16 |
|
T16 |
2180 |
|
T17 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |