Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6857085 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
62 |
| auto[1] |
4632784 |
1 |
|
|
T27 |
3 |
|
T1 |
1370 |
|
T16 |
40932 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10895359 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
64 |
| auto[1] |
594510 |
1 |
|
|
T27 |
1 |
|
T1 |
35 |
|
T16 |
4216 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6833608 |
1 |
|
|
T25 |
36670 |
|
T26 |
164 |
|
T27 |
38 |
| auto[1] |
4656261 |
1 |
|
|
T27 |
27 |
|
T1 |
1076 |
|
T16 |
40877 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2042191 |
1 |
|
|
T27 |
26 |
|
T1 |
342 |
|
T16 |
18615 |
| auto[1] |
auto[0] |
auto[1] |
298718 |
1 |
|
|
T27 |
1 |
|
T1 |
14 |
|
T16 |
2122 |
| auto[1] |
auto[1] |
auto[0] |
2019560 |
1 |
|
|
T1 |
699 |
|
T16 |
18046 |
|
T17 |
163 |
| auto[1] |
auto[1] |
auto[1] |
295792 |
1 |
|
|
T1 |
21 |
|
T16 |
2094 |
|
T17 |
36 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |