Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 938
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T759 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4011135916 Mar 19 02:33:45 PM PDT 24 Mar 19 02:33:46 PM PDT 24 12092206 ps
T760 /workspace/coverage/cover_reg_top/42.gpio_intr_test.773220757 Mar 19 02:34:11 PM PDT 24 Mar 19 02:34:12 PM PDT 24 47323665 ps
T761 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2620177594 Mar 19 02:33:58 PM PDT 24 Mar 19 02:34:01 PM PDT 24 44463722 ps
T762 /workspace/coverage/cover_reg_top/19.gpio_intr_test.4062463103 Mar 19 02:34:03 PM PDT 24 Mar 19 02:34:04 PM PDT 24 44095743 ps
T763 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1565360897 Mar 19 02:33:18 PM PDT 24 Mar 19 02:33:20 PM PDT 24 36542904 ps
T87 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2244098444 Mar 19 02:34:02 PM PDT 24 Mar 19 02:34:04 PM PDT 24 28302872 ps
T764 /workspace/coverage/cover_reg_top/22.gpio_intr_test.4237768276 Mar 19 02:34:03 PM PDT 24 Mar 19 02:34:04 PM PDT 24 10859806 ps
T765 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3898382581 Mar 19 02:33:34 PM PDT 24 Mar 19 02:33:35 PM PDT 24 14987680 ps
T766 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1179164443 Mar 19 02:33:00 PM PDT 24 Mar 19 02:33:02 PM PDT 24 28823019 ps
T767 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1288631218 Mar 19 02:32:54 PM PDT 24 Mar 19 02:32:55 PM PDT 24 77443593 ps
T768 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3342146031 Mar 19 02:33:47 PM PDT 24 Mar 19 02:33:48 PM PDT 24 10634091 ps
T769 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3292065486 Mar 19 02:33:26 PM PDT 24 Mar 19 02:33:29 PM PDT 24 12778595 ps
T770 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3205027711 Mar 19 02:32:53 PM PDT 24 Mar 19 02:32:54 PM PDT 24 304785999 ps
T771 /workspace/coverage/cover_reg_top/5.gpio_intr_test.642392783 Mar 19 02:33:24 PM PDT 24 Mar 19 02:33:25 PM PDT 24 16141317 ps
T772 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.660729305 Mar 19 02:33:10 PM PDT 24 Mar 19 02:33:14 PM PDT 24 1928034518 ps
T773 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1651278949 Mar 19 02:32:45 PM PDT 24 Mar 19 02:32:45 PM PDT 24 11134934 ps
T774 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2082193153 Mar 19 02:33:37 PM PDT 24 Mar 19 02:33:38 PM PDT 24 13707129 ps
T775 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.573339753 Mar 19 02:34:03 PM PDT 24 Mar 19 02:34:05 PM PDT 24 156033210 ps
T776 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2006434674 Mar 19 02:33:37 PM PDT 24 Mar 19 02:33:38 PM PDT 24 56823532 ps
T777 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3698532719 Mar 19 02:32:52 PM PDT 24 Mar 19 02:32:55 PM PDT 24 196957516 ps
T778 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.775892464 Mar 19 02:34:03 PM PDT 24 Mar 19 02:34:04 PM PDT 24 12008065 ps
T779 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2171658702 Mar 19 02:34:15 PM PDT 24 Mar 19 02:34:15 PM PDT 24 31577608 ps
T780 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1187857831 Mar 19 02:33:45 PM PDT 24 Mar 19 02:33:47 PM PDT 24 395805781 ps
T781 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3236476685 Mar 19 02:34:07 PM PDT 24 Mar 19 02:34:08 PM PDT 24 162780505 ps
T88 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3007386271 Mar 19 02:32:46 PM PDT 24 Mar 19 02:32:47 PM PDT 24 113269963 ps
T782 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.797474268 Mar 19 02:33:47 PM PDT 24 Mar 19 02:33:48 PM PDT 24 70816552 ps
T783 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2119631323 Mar 19 02:33:28 PM PDT 24 Mar 19 02:33:30 PM PDT 24 31463740 ps
T784 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2019490501 Mar 19 02:34:12 PM PDT 24 Mar 19 02:34:13 PM PDT 24 31129569 ps
T785 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3066533199 Mar 19 02:33:35 PM PDT 24 Mar 19 02:33:36 PM PDT 24 12645001 ps
T786 /workspace/coverage/cover_reg_top/48.gpio_intr_test.17958076 Mar 19 02:34:12 PM PDT 24 Mar 19 02:34:13 PM PDT 24 44707495 ps
T787 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2790547250 Mar 19 02:33:11 PM PDT 24 Mar 19 02:33:12 PM PDT 24 62353456 ps
T45 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2834653860 Mar 19 02:34:03 PM PDT 24 Mar 19 02:34:05 PM PDT 24 531606957 ps
T788 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1624966504 Mar 19 02:34:13 PM PDT 24 Mar 19 02:34:14 PM PDT 24 36022950 ps
T789 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1949245247 Mar 19 02:33:27 PM PDT 24 Mar 19 02:33:29 PM PDT 24 14454341 ps
T790 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2929563630 Mar 19 02:32:54 PM PDT 24 Mar 19 02:32:55 PM PDT 24 44374961 ps
T791 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1330062624 Mar 19 02:33:25 PM PDT 24 Mar 19 02:33:28 PM PDT 24 36460167 ps
T792 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3508027953 Mar 19 02:34:02 PM PDT 24 Mar 19 02:34:04 PM PDT 24 53732738 ps
T793 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2835181841 Mar 19 02:33:53 PM PDT 24 Mar 19 02:33:54 PM PDT 24 23170584 ps
T794 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2388979953 Mar 19 02:34:04 PM PDT 24 Mar 19 02:34:05 PM PDT 24 14863227 ps
T795 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2259414332 Mar 19 02:34:14 PM PDT 24 Mar 19 02:34:15 PM PDT 24 27603236 ps
T89 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1724647192 Mar 19 02:33:46 PM PDT 24 Mar 19 02:33:47 PM PDT 24 33708079 ps
T796 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1569801429 Mar 19 02:33:12 PM PDT 24 Mar 19 02:33:16 PM PDT 24 17873813 ps
T797 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1949813030 Mar 19 02:33:10 PM PDT 24 Mar 19 02:33:11 PM PDT 24 47355181 ps
T798 /workspace/coverage/cover_reg_top/46.gpio_intr_test.789041426 Mar 19 02:34:11 PM PDT 24 Mar 19 02:34:12 PM PDT 24 18768241 ps
T799 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.934551530 Mar 19 02:34:04 PM PDT 24 Mar 19 02:34:05 PM PDT 24 61622530 ps
T800 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3761116213 Mar 19 02:33:45 PM PDT 24 Mar 19 02:33:47 PM PDT 24 80370243 ps
T801 /workspace/coverage/cover_reg_top/33.gpio_intr_test.949676986 Mar 19 02:34:11 PM PDT 24 Mar 19 02:34:12 PM PDT 24 54672603 ps
T802 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.999787497 Mar 19 02:33:00 PM PDT 24 Mar 19 02:33:02 PM PDT 24 244777154 ps
T803 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3138806111 Mar 19 02:33:01 PM PDT 24 Mar 19 02:33:03 PM PDT 24 491853165 ps
T804 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1707859519 Mar 19 02:34:03 PM PDT 24 Mar 19 02:34:05 PM PDT 24 109410167 ps
T805 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3678380836 Mar 19 02:32:48 PM PDT 24 Mar 19 02:32:49 PM PDT 24 109399604 ps
T806 /workspace/coverage/cover_reg_top/39.gpio_intr_test.651992638 Mar 19 02:34:11 PM PDT 24 Mar 19 02:34:12 PM PDT 24 19674320 ps
T807 /workspace/coverage/cover_reg_top/49.gpio_intr_test.605758703 Mar 19 02:34:22 PM PDT 24 Mar 19 02:34:22 PM PDT 24 53590782 ps
T808 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.745625161 Mar 19 02:34:02 PM PDT 24 Mar 19 02:34:04 PM PDT 24 18093581 ps
T809 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3645579979 Mar 19 02:32:40 PM PDT 24 Mar 19 02:32:41 PM PDT 24 13437609 ps
T810 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1744808473 Mar 19 02:34:04 PM PDT 24 Mar 19 02:34:05 PM PDT 24 85128466 ps
T102 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1007248747 Mar 19 02:33:25 PM PDT 24 Mar 19 02:33:28 PM PDT 24 211884036 ps
T90 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2273166906 Mar 19 02:32:44 PM PDT 24 Mar 19 02:32:45 PM PDT 24 52072146 ps
T811 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2785359664 Mar 19 02:32:49 PM PDT 24 Mar 19 02:32:50 PM PDT 24 76198706 ps
T812 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.99999525 Mar 19 02:34:02 PM PDT 24 Mar 19 02:34:06 PM PDT 24 1521567178 ps
T813 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2748804132 Mar 19 02:33:57 PM PDT 24 Mar 19 02:33:59 PM PDT 24 20738248 ps
T814 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2993237890 Mar 19 02:32:53 PM PDT 24 Mar 19 02:32:54 PM PDT 24 16610136 ps
T815 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1101899674 Mar 19 02:33:09 PM PDT 24 Mar 19 02:33:11 PM PDT 24 69205555 ps
T816 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1159846025 Mar 19 02:32:59 PM PDT 24 Mar 19 02:33:00 PM PDT 24 35785692 ps
T817 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3891733657 Mar 19 02:34:04 PM PDT 24 Mar 19 02:34:04 PM PDT 24 94905280 ps
T818 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3022372417 Mar 19 02:33:35 PM PDT 24 Mar 19 02:33:35 PM PDT 24 15455595 ps
T819 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1250372484 Mar 19 02:33:20 PM PDT 24 Mar 19 02:33:22 PM PDT 24 101076431 ps
T820 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3687498555 Mar 19 02:34:02 PM PDT 24 Mar 19 02:34:03 PM PDT 24 18202882 ps
T821 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2654386035 Mar 19 02:33:47 PM PDT 24 Mar 19 02:33:48 PM PDT 24 27716253 ps
T822 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1854074349 Mar 19 02:34:05 PM PDT 24 Mar 19 02:34:06 PM PDT 24 40600259 ps
T823 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.22448979 Mar 19 02:33:34 PM PDT 24 Mar 19 02:33:35 PM PDT 24 11386877 ps
T92 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.781116946 Mar 19 02:33:57 PM PDT 24 Mar 19 02:33:58 PM PDT 24 14594850 ps
T824 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1390221221 Mar 19 02:34:11 PM PDT 24 Mar 19 02:34:12 PM PDT 24 15629752 ps
T825 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.547565547 Mar 19 02:33:55 PM PDT 24 Mar 19 02:33:56 PM PDT 24 105120766 ps
T826 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.661942258 Mar 19 02:33:19 PM PDT 24 Mar 19 02:33:21 PM PDT 24 86953383 ps
T827 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3331235219 Mar 19 02:33:44 PM PDT 24 Mar 19 02:33:45 PM PDT 24 46563862 ps
T828 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1125262755 Mar 19 02:33:47 PM PDT 24 Mar 19 02:33:48 PM PDT 24 93869550 ps
T829 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.429176621 Mar 19 02:33:56 PM PDT 24 Mar 19 02:33:58 PM PDT 24 70837598 ps
T830 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1107727212 Mar 19 02:34:03 PM PDT 24 Mar 19 02:34:04 PM PDT 24 28169593 ps
T831 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3480218494 Mar 19 02:33:01 PM PDT 24 Mar 19 02:33:05 PM PDT 24 253659203 ps
T832 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2235933265 Mar 19 02:34:04 PM PDT 24 Mar 19 02:34:04 PM PDT 24 11795153 ps
T833 /workspace/coverage/cover_reg_top/8.gpio_intr_test.307119459 Mar 19 02:33:25 PM PDT 24 Mar 19 02:33:27 PM PDT 24 32968207 ps
T834 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.997709823 Mar 19 02:33:18 PM PDT 24 Mar 19 02:33:19 PM PDT 24 87691577 ps
T835 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2127287613 Mar 19 02:33:25 PM PDT 24 Mar 19 02:33:28 PM PDT 24 175472942 ps
T91 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.908576781 Mar 19 02:32:49 PM PDT 24 Mar 19 02:32:50 PM PDT 24 53007036 ps
T836 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.227579172 Mar 19 02:33:10 PM PDT 24 Mar 19 02:33:11 PM PDT 24 14404161 ps
T837 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2083107205 Mar 19 02:34:04 PM PDT 24 Mar 19 02:34:05 PM PDT 24 32768068 ps
T838 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1571203511 Mar 19 02:33:18 PM PDT 24 Mar 19 02:33:20 PM PDT 24 39974511 ps
T839 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2857846997 Mar 19 02:47:07 PM PDT 24 Mar 19 02:47:09 PM PDT 24 54665239 ps
T840 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2192375776 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 36201205 ps
T841 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2117081757 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:08 PM PDT 24 271153276 ps
T842 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3552854733 Mar 19 02:47:09 PM PDT 24 Mar 19 02:47:10 PM PDT 24 43210113 ps
T843 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2165445198 Mar 19 02:47:16 PM PDT 24 Mar 19 02:47:17 PM PDT 24 767202028 ps
T844 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1107908630 Mar 19 02:47:08 PM PDT 24 Mar 19 02:47:09 PM PDT 24 103261543 ps
T845 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.238896752 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:08 PM PDT 24 166059664 ps
T846 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.49345289 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 389060625 ps
T847 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.69859137 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 42272590 ps
T848 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3563046669 Mar 19 02:47:09 PM PDT 24 Mar 19 02:47:11 PM PDT 24 326443373 ps
T849 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1479235331 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 125455101 ps
T850 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1224327666 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:07 PM PDT 24 74118720 ps
T851 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3362073502 Mar 19 02:47:04 PM PDT 24 Mar 19 02:47:05 PM PDT 24 107146135 ps
T852 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.91287780 Mar 19 02:47:20 PM PDT 24 Mar 19 02:47:21 PM PDT 24 53133283 ps
T853 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3405593550 Mar 19 02:47:04 PM PDT 24 Mar 19 02:47:05 PM PDT 24 49367265 ps
T854 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3329143058 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:07 PM PDT 24 346553560 ps
T855 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3128789132 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:19 PM PDT 24 307838354 ps
T856 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3454738890 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 81560976 ps
T857 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.464548630 Mar 19 02:47:07 PM PDT 24 Mar 19 02:47:08 PM PDT 24 47592919 ps
T858 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4173495194 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:08 PM PDT 24 310836235 ps
T859 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1936926388 Mar 19 02:47:19 PM PDT 24 Mar 19 02:47:20 PM PDT 24 72187809 ps
T860 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2319186816 Mar 19 02:47:07 PM PDT 24 Mar 19 02:47:08 PM PDT 24 172530236 ps
T861 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2915149214 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 304999941 ps
T862 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3601610351 Mar 19 02:47:16 PM PDT 24 Mar 19 02:47:18 PM PDT 24 172797133 ps
T863 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3619522759 Mar 19 02:47:20 PM PDT 24 Mar 19 02:47:21 PM PDT 24 71505946 ps
T864 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2553620761 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 100464045 ps
T865 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.155456676 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:19 PM PDT 24 365675582 ps
T866 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4096960231 Mar 19 02:47:07 PM PDT 24 Mar 19 02:47:09 PM PDT 24 734020505 ps
T867 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2149839179 Mar 19 02:47:08 PM PDT 24 Mar 19 02:47:09 PM PDT 24 30111118 ps
T868 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3382373528 Mar 19 02:47:19 PM PDT 24 Mar 19 02:47:20 PM PDT 24 159324192 ps
T869 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1916555746 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:20 PM PDT 24 109411760 ps
T870 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1104754765 Mar 19 02:47:21 PM PDT 24 Mar 19 02:47:22 PM PDT 24 65477384 ps
T871 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3941609424 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 59142926 ps
T872 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2390266647 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 71091311 ps
T873 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98001314 Mar 19 02:47:03 PM PDT 24 Mar 19 02:47:04 PM PDT 24 42266245 ps
T874 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.661457159 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 64035729 ps
T875 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3756612191 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 196446088 ps
T876 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1223315182 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:20 PM PDT 24 226156728 ps
T877 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1811353376 Mar 19 02:47:07 PM PDT 24 Mar 19 02:47:08 PM PDT 24 93730181 ps
T878 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2997719923 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 70780188 ps
T879 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1951172751 Mar 19 02:47:04 PM PDT 24 Mar 19 02:47:05 PM PDT 24 62429414 ps
T880 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999917272 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 194197927 ps
T881 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.817976063 Mar 19 02:47:08 PM PDT 24 Mar 19 02:47:09 PM PDT 24 78041847 ps
T882 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2135922315 Mar 19 02:47:16 PM PDT 24 Mar 19 02:47:18 PM PDT 24 49024340 ps
T883 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.502855888 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:20 PM PDT 24 329349805 ps
T884 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1961334077 Mar 19 02:47:07 PM PDT 24 Mar 19 02:47:09 PM PDT 24 145002195 ps
T885 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3174154624 Mar 19 02:47:08 PM PDT 24 Mar 19 02:47:10 PM PDT 24 40491285 ps
T886 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3885462742 Mar 19 02:47:08 PM PDT 24 Mar 19 02:47:09 PM PDT 24 84970037 ps
T887 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1868823475 Mar 19 02:47:19 PM PDT 24 Mar 19 02:47:20 PM PDT 24 109101768 ps
T888 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.400999402 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:07 PM PDT 24 80723035 ps
T889 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3065100036 Mar 19 02:47:16 PM PDT 24 Mar 19 02:47:17 PM PDT 24 46184853 ps
T890 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1517310007 Mar 19 02:47:16 PM PDT 24 Mar 19 02:47:17 PM PDT 24 166545449 ps
T891 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3222682212 Mar 19 02:47:19 PM PDT 24 Mar 19 02:47:20 PM PDT 24 312955312 ps
T892 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.710956629 Mar 19 02:46:59 PM PDT 24 Mar 19 02:47:00 PM PDT 24 34980744 ps
T893 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3677152431 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 41288988 ps
T894 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1456024364 Mar 19 02:47:08 PM PDT 24 Mar 19 02:47:10 PM PDT 24 85656784 ps
T895 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3115484704 Mar 19 02:47:07 PM PDT 24 Mar 19 02:47:08 PM PDT 24 124364325 ps
T896 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2956559079 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 49888536 ps
T897 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1799261827 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 205679058 ps
T898 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1381547258 Mar 19 02:47:02 PM PDT 24 Mar 19 02:47:04 PM PDT 24 328409331 ps
T899 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749258954 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 347828167 ps
T900 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.8727838 Mar 19 02:47:15 PM PDT 24 Mar 19 02:47:17 PM PDT 24 106862847 ps
T901 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3792146932 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 133261063 ps
T902 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.39030553 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 48226294 ps
T903 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3827249299 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 84507458 ps
T904 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2485414118 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 318502439 ps
T905 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1612303252 Mar 19 02:47:10 PM PDT 24 Mar 19 02:47:11 PM PDT 24 65928421 ps
T906 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1969255328 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 133196033 ps
T907 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2497138585 Mar 19 02:47:19 PM PDT 24 Mar 19 02:47:21 PM PDT 24 53247808 ps
T908 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3445512293 Mar 19 02:47:08 PM PDT 24 Mar 19 02:47:10 PM PDT 24 37863800 ps
T909 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.839374192 Mar 19 02:47:03 PM PDT 24 Mar 19 02:47:04 PM PDT 24 97776575 ps
T910 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3478460104 Mar 19 02:47:19 PM PDT 24 Mar 19 02:47:20 PM PDT 24 124923763 ps
T911 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2269418433 Mar 19 02:47:09 PM PDT 24 Mar 19 02:47:10 PM PDT 24 407292313 ps
T912 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2568188423 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 30207482 ps
T913 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3882080014 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 1076184658 ps
T914 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.449492074 Mar 19 02:47:07 PM PDT 24 Mar 19 02:47:09 PM PDT 24 60809085 ps
T915 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2061304789 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 51154620 ps
T916 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3641291811 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 36531143 ps
T917 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1838931749 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 45400386 ps
T918 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.478595761 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 330092090 ps
T919 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3544228952 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:20 PM PDT 24 168636572 ps
T920 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.916732827 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 52170917 ps
T921 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3266442112 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 230040919 ps
T922 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894431963 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 197655944 ps
T923 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2210098 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 38826705 ps
T924 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.640088734 Mar 19 02:47:09 PM PDT 24 Mar 19 02:47:10 PM PDT 24 87324962 ps
T925 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2671860679 Mar 19 02:47:00 PM PDT 24 Mar 19 02:47:01 PM PDT 24 116894513 ps
T926 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1569442329 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 169577657 ps
T927 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3650251179 Mar 19 02:47:09 PM PDT 24 Mar 19 02:47:10 PM PDT 24 200865652 ps
T928 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3842517250 Mar 19 02:47:05 PM PDT 24 Mar 19 02:47:06 PM PDT 24 102139593 ps
T929 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.288501954 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 28477194 ps
T930 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1922650665 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:19 PM PDT 24 38766117 ps
T931 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.660555743 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:20 PM PDT 24 382734869 ps
T932 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2355225493 Mar 19 02:47:04 PM PDT 24 Mar 19 02:47:06 PM PDT 24 183289618 ps
T933 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2986197616 Mar 19 02:47:19 PM PDT 24 Mar 19 02:47:20 PM PDT 24 83893037 ps
T934 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4108922062 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 116290500 ps
T935 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2266742835 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:08 PM PDT 24 116353761 ps
T936 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2388341600 Mar 19 02:47:06 PM PDT 24 Mar 19 02:47:07 PM PDT 24 63498531 ps
T937 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037978729 Mar 19 02:47:19 PM PDT 24 Mar 19 02:47:20 PM PDT 24 271109818 ps
T938 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1115056711 Mar 19 02:47:07 PM PDT 24 Mar 19 02:47:08 PM PDT 24 72034851 ps

Test location /workspace/coverage/default/35.gpio_stress_all.1104562740
Short name T16
Test name
Test status
Simulation time 12991084723 ps
CPU time 180.75 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:44:14 PM PDT 24
Peak memory 198156 kb
Host smart-add3542f-ebea-4f01-8f9a-b7bad2856b28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104562740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1104562740
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4071267339
Short name T57
Test name
Test status
Simulation time 52017110 ps
CPU time 2.16 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 198040 kb
Host smart-6a235992-45db-4350-87b8-abd17a806fee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071267339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4071267339
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.928723923
Short name T28
Test name
Test status
Simulation time 310020512236 ps
CPU time 1553.32 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 03:07:25 PM PDT 24
Peak memory 198212 kb
Host smart-d0e8e70d-e7aa-425a-9370-90642015293e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=928723923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.928723923
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.441559281
Short name T34
Test name
Test status
Simulation time 93211898 ps
CPU time 0.99 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:39 PM PDT 24
Peak memory 214844 kb
Host smart-3fb6096d-6931-46a2-a74a-fce151a852de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441559281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.441559281
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2637775839
Short name T1
Test name
Test status
Simulation time 2133477947 ps
CPU time 6.07 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:51 PM PDT 24
Peak memory 197972 kb
Host smart-0113b3bf-8501-4b3c-801d-5a077dd77359
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637775839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2637775839
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2624799747
Short name T79
Test name
Test status
Simulation time 31545072 ps
CPU time 0.76 seconds
Started Mar 19 02:32:54 PM PDT 24
Finished Mar 19 02:32:55 PM PDT 24
Peak memory 196012 kb
Host smart-90b7dbab-6d1b-4d89-b5b2-2c0f3b219983
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624799747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2624799747
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.567498941
Short name T42
Test name
Test status
Simulation time 222942579 ps
CPU time 1.53 seconds
Started Mar 19 02:33:44 PM PDT 24
Finished Mar 19 02:33:45 PM PDT 24
Peak memory 197876 kb
Host smart-3b662c39-d5cb-46b2-8c8a-cfc17daf8a7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567498941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.567498941
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2913415938
Short name T150
Test name
Test status
Simulation time 218520527 ps
CPU time 0.6 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:08 PM PDT 24
Peak memory 194056 kb
Host smart-088e56b5-f942-48f6-8fc7-60f2cbc45d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913415938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2913415938
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3007386271
Short name T88
Test name
Test status
Simulation time 113269963 ps
CPU time 0.87 seconds
Started Mar 19 02:32:46 PM PDT 24
Finished Mar 19 02:32:47 PM PDT 24
Peak memory 196220 kb
Host smart-3cc66d19-4332-4e6b-a9ba-adcc303d0281
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007386271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3007386271
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1524211685
Short name T78
Test name
Test status
Simulation time 21045420 ps
CPU time 0.82 seconds
Started Mar 19 02:33:36 PM PDT 24
Finished Mar 19 02:33:37 PM PDT 24
Peak memory 196312 kb
Host smart-6c31481a-b811-475d-9c9b-5b1b46030510
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524211685 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1524211685
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1007248747
Short name T102
Test name
Test status
Simulation time 211884036 ps
CPU time 1.46 seconds
Started Mar 19 02:33:25 PM PDT 24
Finished Mar 19 02:33:28 PM PDT 24
Peak memory 198036 kb
Host smart-f908fa75-5547-4074-99dd-25351a04a0ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007248747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1007248747
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3854744736
Short name T745
Test name
Test status
Simulation time 79721272 ps
CPU time 3.05 seconds
Started Mar 19 02:32:47 PM PDT 24
Finished Mar 19 02:32:51 PM PDT 24
Peak memory 197932 kb
Host smart-f63ab428-3935-40f2-9d0e-73189f698139
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854744736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3854744736
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2273166906
Short name T90
Test name
Test status
Simulation time 52072146 ps
CPU time 0.65 seconds
Started Mar 19 02:32:44 PM PDT 24
Finished Mar 19 02:32:45 PM PDT 24
Peak memory 195092 kb
Host smart-180f0acd-a381-4c17-92a7-367eab079263
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273166906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2273166906
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1180002513
Short name T740
Test name
Test status
Simulation time 18936199 ps
CPU time 0.72 seconds
Started Mar 19 02:32:45 PM PDT 24
Finished Mar 19 02:32:46 PM PDT 24
Peak memory 198012 kb
Host smart-5c601286-a000-479e-b2e5-f77d568bb81c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180002513 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1180002513
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.4218710647
Short name T85
Test name
Test status
Simulation time 14070204 ps
CPU time 0.59 seconds
Started Mar 19 02:32:40 PM PDT 24
Finished Mar 19 02:32:41 PM PDT 24
Peak memory 194632 kb
Host smart-9e37b4bf-ee68-4b56-be41-4b892236c40f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218710647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.4218710647
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2805869451
Short name T723
Test name
Test status
Simulation time 23736775 ps
CPU time 0.62 seconds
Started Mar 19 02:32:46 PM PDT 24
Finished Mar 19 02:32:47 PM PDT 24
Peak memory 194324 kb
Host smart-5c04f2d0-1e44-443c-8f54-f9433545b4b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805869451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2805869451
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3645579979
Short name T809
Test name
Test status
Simulation time 13437609 ps
CPU time 0.68 seconds
Started Mar 19 02:32:40 PM PDT 24
Finished Mar 19 02:32:41 PM PDT 24
Peak memory 194836 kb
Host smart-d9a496d8-e0d0-4dff-83c8-a6e77766fb90
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645579979 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3645579979
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3727365617
Short name T732
Test name
Test status
Simulation time 149393383 ps
CPU time 1.69 seconds
Started Mar 19 02:32:49 PM PDT 24
Finished Mar 19 02:32:51 PM PDT 24
Peak memory 198040 kb
Host smart-ac4804fe-eb30-4377-a48a-fe4ff01e1bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727365617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3727365617
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2785359664
Short name T811
Test name
Test status
Simulation time 76198706 ps
CPU time 1.21 seconds
Started Mar 19 02:32:49 PM PDT 24
Finished Mar 19 02:32:50 PM PDT 24
Peak memory 198044 kb
Host smart-4b0f3faa-3522-4dfa-84e5-81d70cd8e4f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785359664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2785359664
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.908576781
Short name T91
Test name
Test status
Simulation time 53007036 ps
CPU time 0.75 seconds
Started Mar 19 02:32:49 PM PDT 24
Finished Mar 19 02:32:50 PM PDT 24
Peak memory 195380 kb
Host smart-cc1caa92-de1f-4b9d-8f79-6aabb147dc62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908576781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.908576781
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1812215051
Short name T757
Test name
Test status
Simulation time 255651723 ps
CPU time 2.13 seconds
Started Mar 19 02:32:54 PM PDT 24
Finished Mar 19 02:32:56 PM PDT 24
Peak memory 196592 kb
Host smart-e3c1bdd0-db15-409a-8407-55ae2a09fff4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812215051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1812215051
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.91810159
Short name T739
Test name
Test status
Simulation time 53375789 ps
CPU time 0.63 seconds
Started Mar 19 02:32:54 PM PDT 24
Finished Mar 19 02:32:55 PM PDT 24
Peak memory 194808 kb
Host smart-e472a852-03ce-4ff7-a7ec-e89434933fc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91810159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.91810159
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1949066774
Short name T716
Test name
Test status
Simulation time 64673540 ps
CPU time 0.78 seconds
Started Mar 19 02:32:47 PM PDT 24
Finished Mar 19 02:32:48 PM PDT 24
Peak memory 197948 kb
Host smart-259eae36-9006-4776-95bf-51dfd3f06f8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949066774 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1949066774
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1651278949
Short name T773
Test name
Test status
Simulation time 11134934 ps
CPU time 0.59 seconds
Started Mar 19 02:32:45 PM PDT 24
Finished Mar 19 02:32:45 PM PDT 24
Peak memory 195216 kb
Host smart-bf084472-10de-49a4-a598-ee3c614ec599
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651278949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1651278949
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2993237890
Short name T814
Test name
Test status
Simulation time 16610136 ps
CPU time 0.65 seconds
Started Mar 19 02:32:53 PM PDT 24
Finished Mar 19 02:32:54 PM PDT 24
Peak memory 193708 kb
Host smart-18a91f16-4464-4f65-ba9d-cb0f022a4d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993237890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2993237890
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3678380836
Short name T805
Test name
Test status
Simulation time 109399604 ps
CPU time 0.82 seconds
Started Mar 19 02:32:48 PM PDT 24
Finished Mar 19 02:32:49 PM PDT 24
Peak memory 196384 kb
Host smart-d987e573-dc7a-427a-bb23-8e3deb7c54ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678380836 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3678380836
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3698532719
Short name T777
Test name
Test status
Simulation time 196957516 ps
CPU time 2.2 seconds
Started Mar 19 02:32:52 PM PDT 24
Finished Mar 19 02:32:55 PM PDT 24
Peak memory 198020 kb
Host smart-a9a09ce3-1e9c-4a78-8f81-b7644e75df91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698532719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3698532719
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3205027711
Short name T770
Test name
Test status
Simulation time 304785999 ps
CPU time 1.22 seconds
Started Mar 19 02:32:53 PM PDT 24
Finished Mar 19 02:32:54 PM PDT 24
Peak memory 198056 kb
Host smart-dc65ec17-da48-4eda-87cd-5ffc0b0258da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205027711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3205027711
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3295262193
Short name T753
Test name
Test status
Simulation time 52251088 ps
CPU time 0.82 seconds
Started Mar 19 02:33:34 PM PDT 24
Finished Mar 19 02:33:35 PM PDT 24
Peak memory 198088 kb
Host smart-de38c6d8-d0e8-4eed-8823-022ac753840c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295262193 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3295262193
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.22448979
Short name T823
Test name
Test status
Simulation time 11386877 ps
CPU time 0.55 seconds
Started Mar 19 02:33:34 PM PDT 24
Finished Mar 19 02:33:35 PM PDT 24
Peak memory 193292 kb
Host smart-40d1cc3d-97b2-4bec-8690-58bca1a9d89f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22448979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_
csr_rw.22448979
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3066533199
Short name T785
Test name
Test status
Simulation time 12645001 ps
CPU time 0.59 seconds
Started Mar 19 02:33:35 PM PDT 24
Finished Mar 19 02:33:36 PM PDT 24
Peak memory 193660 kb
Host smart-13119515-5f26-4a72-8af3-0d314aa2eb37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066533199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3066533199
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4106191861
Short name T738
Test name
Test status
Simulation time 462530929 ps
CPU time 2.93 seconds
Started Mar 19 02:33:37 PM PDT 24
Finished Mar 19 02:33:40 PM PDT 24
Peak memory 198072 kb
Host smart-8806a4fb-f762-45c6-8d01-c7f7631c6f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106191861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4106191861
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3479843189
Short name T41
Test name
Test status
Simulation time 269102809 ps
CPU time 1.14 seconds
Started Mar 19 02:33:36 PM PDT 24
Finished Mar 19 02:33:37 PM PDT 24
Peak memory 197960 kb
Host smart-49d513ea-1d32-40f8-85d2-0899c5cb0123
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479843189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3479843189
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1850472412
Short name T748
Test name
Test status
Simulation time 20719212 ps
CPU time 0.82 seconds
Started Mar 19 02:33:35 PM PDT 24
Finished Mar 19 02:33:36 PM PDT 24
Peak memory 198000 kb
Host smart-35099970-ae70-42e7-a141-40a5098c2179
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850472412 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1850472412
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3022372417
Short name T818
Test name
Test status
Simulation time 15455595 ps
CPU time 0.62 seconds
Started Mar 19 02:33:35 PM PDT 24
Finished Mar 19 02:33:35 PM PDT 24
Peak memory 195464 kb
Host smart-c88a1c6d-a9a9-4e92-9ab7-6be2c420c87a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022372417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3022372417
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2006434674
Short name T776
Test name
Test status
Simulation time 56823532 ps
CPU time 0.6 seconds
Started Mar 19 02:33:37 PM PDT 24
Finished Mar 19 02:33:38 PM PDT 24
Peak memory 193684 kb
Host smart-3090d121-4072-4062-bbab-f83da20f2002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006434674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2006434674
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3883467737
Short name T99
Test name
Test status
Simulation time 20441208 ps
CPU time 0.85 seconds
Started Mar 19 02:33:36 PM PDT 24
Finished Mar 19 02:33:37 PM PDT 24
Peak memory 197184 kb
Host smart-b556e0a0-fd74-4275-bc99-8e71271eb524
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883467737 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3883467737
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.564675513
Short name T758
Test name
Test status
Simulation time 135312264 ps
CPU time 2.82 seconds
Started Mar 19 02:33:37 PM PDT 24
Finished Mar 19 02:33:39 PM PDT 24
Peak memory 198036 kb
Host smart-61f1943e-bd69-414a-a1b8-7338742ceb4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564675513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.564675513
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1332256620
Short name T43
Test name
Test status
Simulation time 90828126 ps
CPU time 0.87 seconds
Started Mar 19 02:33:36 PM PDT 24
Finished Mar 19 02:33:37 PM PDT 24
Peak memory 197272 kb
Host smart-1dc6f6f3-c6ac-48c9-babd-d65494dbeef8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332256620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1332256620
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.797474268
Short name T782
Test name
Test status
Simulation time 70816552 ps
CPU time 0.91 seconds
Started Mar 19 02:33:47 PM PDT 24
Finished Mar 19 02:33:48 PM PDT 24
Peak memory 197964 kb
Host smart-cf72af3a-a8bf-4f61-bb39-386491c74be5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797474268 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.797474268
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3898382581
Short name T765
Test name
Test status
Simulation time 14987680 ps
CPU time 0.59 seconds
Started Mar 19 02:33:34 PM PDT 24
Finished Mar 19 02:33:35 PM PDT 24
Peak memory 194636 kb
Host smart-4b61883a-b501-493b-8b87-a752d73e91a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898382581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3898382581
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3342146031
Short name T768
Test name
Test status
Simulation time 10634091 ps
CPU time 0.59 seconds
Started Mar 19 02:33:47 PM PDT 24
Finished Mar 19 02:33:48 PM PDT 24
Peak memory 193620 kb
Host smart-13bf0db4-0156-47c6-be19-3066a0923525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342146031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3342146031
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4126032565
Short name T98
Test name
Test status
Simulation time 17019069 ps
CPU time 0.77 seconds
Started Mar 19 02:33:44 PM PDT 24
Finished Mar 19 02:33:45 PM PDT 24
Peak memory 196092 kb
Host smart-4ecfe720-38df-47c9-b809-03a5cd39b4a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126032565 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4126032565
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1187857831
Short name T780
Test name
Test status
Simulation time 395805781 ps
CPU time 2.05 seconds
Started Mar 19 02:33:45 PM PDT 24
Finished Mar 19 02:33:47 PM PDT 24
Peak memory 198012 kb
Host smart-74733706-714f-4b8d-92f0-d52fda3a99db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187857831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1187857831
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.940227872
Short name T746
Test name
Test status
Simulation time 64925670 ps
CPU time 0.94 seconds
Started Mar 19 02:33:44 PM PDT 24
Finished Mar 19 02:33:45 PM PDT 24
Peak memory 198024 kb
Host smart-62aee864-1f64-4f59-a6aa-9f2b6af1a542
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940227872 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.940227872
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1724647192
Short name T89
Test name
Test status
Simulation time 33708079 ps
CPU time 0.65 seconds
Started Mar 19 02:33:46 PM PDT 24
Finished Mar 19 02:33:47 PM PDT 24
Peak memory 194876 kb
Host smart-a9b152ea-c23a-4803-a652-a8031d58682e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724647192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1724647192
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1109272580
Short name T737
Test name
Test status
Simulation time 40915333 ps
CPU time 0.58 seconds
Started Mar 19 02:33:46 PM PDT 24
Finished Mar 19 02:33:47 PM PDT 24
Peak memory 193660 kb
Host smart-620f481c-4c38-4fd3-b8f8-3e3a6e8be6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109272580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1109272580
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3761116213
Short name T800
Test name
Test status
Simulation time 80370243 ps
CPU time 0.83 seconds
Started Mar 19 02:33:45 PM PDT 24
Finished Mar 19 02:33:47 PM PDT 24
Peak memory 196256 kb
Host smart-3f4a1a93-8c0d-45b7-8cf4-508da0f575de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761116213 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3761116213
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1125262755
Short name T828
Test name
Test status
Simulation time 93869550 ps
CPU time 1.41 seconds
Started Mar 19 02:33:47 PM PDT 24
Finished Mar 19 02:33:48 PM PDT 24
Peak memory 198036 kb
Host smart-187d3bd8-7661-4e70-9522-032a435fd44c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125262755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1125262755
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3331235219
Short name T827
Test name
Test status
Simulation time 46563862 ps
CPU time 0.92 seconds
Started Mar 19 02:33:44 PM PDT 24
Finished Mar 19 02:33:45 PM PDT 24
Peak memory 197252 kb
Host smart-ffa7f786-fecf-4bbc-8166-eef7e42e57cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331235219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3331235219
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3235949882
Short name T756
Test name
Test status
Simulation time 16323463 ps
CPU time 0.81 seconds
Started Mar 19 02:33:50 PM PDT 24
Finished Mar 19 02:33:52 PM PDT 24
Peak memory 198024 kb
Host smart-74514ecf-e4d7-4502-ad32-65bf41c3abed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235949882 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3235949882
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2654386035
Short name T821
Test name
Test status
Simulation time 27716253 ps
CPU time 0.58 seconds
Started Mar 19 02:33:47 PM PDT 24
Finished Mar 19 02:33:48 PM PDT 24
Peak memory 194768 kb
Host smart-31787dd3-b277-4680-b930-2a2744755e80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654386035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2654386035
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4011135916
Short name T759
Test name
Test status
Simulation time 12092206 ps
CPU time 0.67 seconds
Started Mar 19 02:33:45 PM PDT 24
Finished Mar 19 02:33:46 PM PDT 24
Peak memory 193772 kb
Host smart-5fd05a2e-3a41-4d02-9469-fd4df3d7b7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011135916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4011135916
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1381084043
Short name T96
Test name
Test status
Simulation time 115010218 ps
CPU time 0.87 seconds
Started Mar 19 02:33:43 PM PDT 24
Finished Mar 19 02:33:45 PM PDT 24
Peak memory 196448 kb
Host smart-a42f11e0-dcd7-4f53-aa4f-472c6e4198ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381084043 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1381084043
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2025115973
Short name T736
Test name
Test status
Simulation time 106019065 ps
CPU time 1.33 seconds
Started Mar 19 02:33:46 PM PDT 24
Finished Mar 19 02:33:47 PM PDT 24
Peak memory 198004 kb
Host smart-6be2b062-fe41-4f02-a3b4-4c161ac8dd0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025115973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2025115973
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3154683403
Short name T31
Test name
Test status
Simulation time 410020821 ps
CPU time 0.88 seconds
Started Mar 19 02:33:48 PM PDT 24
Finished Mar 19 02:33:49 PM PDT 24
Peak memory 197196 kb
Host smart-e4f53018-a8eb-4812-ab7f-8d90c16bab95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154683403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3154683403
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1833829095
Short name T713
Test name
Test status
Simulation time 50071382 ps
CPU time 0.65 seconds
Started Mar 19 02:33:54 PM PDT 24
Finished Mar 19 02:33:55 PM PDT 24
Peak memory 196556 kb
Host smart-06282d2e-bc95-4e10-8d2d-6a25ad04a034
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833829095 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1833829095
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1566057787
Short name T84
Test name
Test status
Simulation time 56436868 ps
CPU time 0.62 seconds
Started Mar 19 02:33:53 PM PDT 24
Finished Mar 19 02:33:54 PM PDT 24
Peak memory 195608 kb
Host smart-82053eb9-d829-49a8-a49e-f5ac36d613a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566057787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1566057787
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1733826272
Short name T725
Test name
Test status
Simulation time 37508745 ps
CPU time 0.58 seconds
Started Mar 19 02:33:54 PM PDT 24
Finished Mar 19 02:33:56 PM PDT 24
Peak memory 194312 kb
Host smart-f07b4aaa-50cf-4635-b17a-0502372901dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733826272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1733826272
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2835181841
Short name T793
Test name
Test status
Simulation time 23170584 ps
CPU time 0.67 seconds
Started Mar 19 02:33:53 PM PDT 24
Finished Mar 19 02:33:54 PM PDT 24
Peak memory 194692 kb
Host smart-83fa52be-743f-4f1c-a247-c78f21d2e7b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835181841 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2835181841
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2620177594
Short name T761
Test name
Test status
Simulation time 44463722 ps
CPU time 2.25 seconds
Started Mar 19 02:33:58 PM PDT 24
Finished Mar 19 02:34:01 PM PDT 24
Peak memory 198040 kb
Host smart-534a2fd2-41ec-41de-8774-c3a2c8ec01f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620177594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2620177594
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3978205131
Short name T40
Test name
Test status
Simulation time 107202366 ps
CPU time 1.41 seconds
Started Mar 19 02:33:57 PM PDT 24
Finished Mar 19 02:33:58 PM PDT 24
Peak memory 198032 kb
Host smart-4f5b3db9-30ba-42a8-8ac2-231422ebdacf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978205131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3978205131
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.547565547
Short name T825
Test name
Test status
Simulation time 105120766 ps
CPU time 0.95 seconds
Started Mar 19 02:33:55 PM PDT 24
Finished Mar 19 02:33:56 PM PDT 24
Peak memory 197872 kb
Host smart-1c494859-90b4-4018-9f39-36a38a58fa0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547565547 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.547565547
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.781116946
Short name T92
Test name
Test status
Simulation time 14594850 ps
CPU time 0.61 seconds
Started Mar 19 02:33:57 PM PDT 24
Finished Mar 19 02:33:58 PM PDT 24
Peak memory 194912 kb
Host smart-1f221b41-6096-400e-ae5e-a0f794e7ce30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781116946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.781116946
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3508027953
Short name T792
Test name
Test status
Simulation time 53732738 ps
CPU time 0.61 seconds
Started Mar 19 02:34:02 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 194304 kb
Host smart-c056c870-cc7d-4896-91a7-ec695598bfbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508027953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3508027953
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2748804132
Short name T813
Test name
Test status
Simulation time 20738248 ps
CPU time 0.7 seconds
Started Mar 19 02:33:57 PM PDT 24
Finished Mar 19 02:33:59 PM PDT 24
Peak memory 195728 kb
Host smart-a1c96a16-c297-4ba1-8a9e-9b61daeeca5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748804132 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2748804132
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1707859519
Short name T804
Test name
Test status
Simulation time 109410167 ps
CPU time 1.69 seconds
Started Mar 19 02:34:03 PM PDT 24
Finished Mar 19 02:34:05 PM PDT 24
Peak memory 198064 kb
Host smart-9e7c8e0a-0efd-4350-a694-8ee3940c85fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707859519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1707859519
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.429176621
Short name T829
Test name
Test status
Simulation time 70837598 ps
CPU time 1.12 seconds
Started Mar 19 02:33:56 PM PDT 24
Finished Mar 19 02:33:58 PM PDT 24
Peak memory 198000 kb
Host smart-085ccfe5-0194-4d36-b82c-1c8ef4135eff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429176621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.429176621
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1744808473
Short name T810
Test name
Test status
Simulation time 85128466 ps
CPU time 0.75 seconds
Started Mar 19 02:34:04 PM PDT 24
Finished Mar 19 02:34:05 PM PDT 24
Peak memory 197996 kb
Host smart-e8a9fc9b-a002-42e5-8c28-354d1c889185
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744808473 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1744808473
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.775892464
Short name T778
Test name
Test status
Simulation time 12008065 ps
CPU time 0.61 seconds
Started Mar 19 02:34:03 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 195264 kb
Host smart-cf84e51c-711a-4020-8198-a79c57f7655e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775892464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.775892464
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2388979953
Short name T794
Test name
Test status
Simulation time 14863227 ps
CPU time 0.64 seconds
Started Mar 19 02:34:04 PM PDT 24
Finished Mar 19 02:34:05 PM PDT 24
Peak memory 194348 kb
Host smart-9b788982-7ccd-4507-8d6c-5367ac206292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388979953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2388979953
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1021589038
Short name T97
Test name
Test status
Simulation time 104291346 ps
CPU time 0.89 seconds
Started Mar 19 02:34:02 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 197248 kb
Host smart-ecdb8c96-48a3-4050-961f-827c8e1963cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021589038 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1021589038
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.934551530
Short name T799
Test name
Test status
Simulation time 61622530 ps
CPU time 1.64 seconds
Started Mar 19 02:34:04 PM PDT 24
Finished Mar 19 02:34:05 PM PDT 24
Peak memory 197996 kb
Host smart-de6f7338-e8d4-4a35-a0ff-6361045d976e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934551530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.934551530
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2834653860
Short name T45
Test name
Test status
Simulation time 531606957 ps
CPU time 1.51 seconds
Started Mar 19 02:34:03 PM PDT 24
Finished Mar 19 02:34:05 PM PDT 24
Peak memory 198032 kb
Host smart-bd7984b8-3e8b-4919-afbf-e3629346c55c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834653860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2834653860
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.573339753
Short name T775
Test name
Test status
Simulation time 156033210 ps
CPU time 1.47 seconds
Started Mar 19 02:34:03 PM PDT 24
Finished Mar 19 02:34:05 PM PDT 24
Peak memory 198128 kb
Host smart-1afe8bc4-2508-446a-b6b3-dd99feefc593
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573339753 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.573339753
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2244098444
Short name T87
Test name
Test status
Simulation time 28302872 ps
CPU time 0.64 seconds
Started Mar 19 02:34:02 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 194764 kb
Host smart-72aba642-f002-48ea-8ec0-e21782bb651e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244098444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2244098444
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1854074349
Short name T822
Test name
Test status
Simulation time 40600259 ps
CPU time 0.61 seconds
Started Mar 19 02:34:05 PM PDT 24
Finished Mar 19 02:34:06 PM PDT 24
Peak memory 194312 kb
Host smart-6778c0e2-9d6a-4f6a-ba66-e6920543167b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854074349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1854074349
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1107727212
Short name T830
Test name
Test status
Simulation time 28169593 ps
CPU time 0.77 seconds
Started Mar 19 02:34:03 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 196772 kb
Host smart-0d63fb3d-f4ce-4b1a-a034-df7e923826e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107727212 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1107727212
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2483357516
Short name T750
Test name
Test status
Simulation time 125327222 ps
CPU time 1.54 seconds
Started Mar 19 02:34:02 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 198048 kb
Host smart-094b8a20-52eb-44fa-a6cb-82320076189c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483357516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2483357516
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3236476685
Short name T781
Test name
Test status
Simulation time 162780505 ps
CPU time 0.89 seconds
Started Mar 19 02:34:07 PM PDT 24
Finished Mar 19 02:34:08 PM PDT 24
Peak memory 196952 kb
Host smart-66209a9c-cda4-4f9f-8b3e-91ccb0e77213
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236476685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3236476685
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2083107205
Short name T837
Test name
Test status
Simulation time 32768068 ps
CPU time 0.82 seconds
Started Mar 19 02:34:04 PM PDT 24
Finished Mar 19 02:34:05 PM PDT 24
Peak memory 197952 kb
Host smart-b76139a6-b473-4f0e-ac2b-3befeb8a874a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083107205 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2083107205
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2178315511
Short name T100
Test name
Test status
Simulation time 46960802 ps
CPU time 0.65 seconds
Started Mar 19 02:34:03 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 195388 kb
Host smart-6b1cc473-8318-4b8d-b308-d6f3451f1642
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178315511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2178315511
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.4062463103
Short name T762
Test name
Test status
Simulation time 44095743 ps
CPU time 0.57 seconds
Started Mar 19 02:34:03 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 193660 kb
Host smart-2d468879-a55f-405f-8d02-fce817a6f0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062463103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.4062463103
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.745625161
Short name T808
Test name
Test status
Simulation time 18093581 ps
CPU time 0.74 seconds
Started Mar 19 02:34:02 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 196408 kb
Host smart-a194f731-6607-4d7a-9b40-16565e0b1644
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745625161 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.745625161
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.99999525
Short name T812
Test name
Test status
Simulation time 1521567178 ps
CPU time 3.41 seconds
Started Mar 19 02:34:02 PM PDT 24
Finished Mar 19 02:34:06 PM PDT 24
Peak memory 198064 kb
Host smart-4b2abba2-6a53-4a51-a6a0-56a136c3fe14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99999525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.99999525
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2828026020
Short name T33
Test name
Test status
Simulation time 462018864 ps
CPU time 1.2 seconds
Started Mar 19 02:34:05 PM PDT 24
Finished Mar 19 02:34:06 PM PDT 24
Peak memory 198072 kb
Host smart-b40bd0a5-7579-48cc-a4d4-4771f8be3959
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828026020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2828026020
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3480218494
Short name T831
Test name
Test status
Simulation time 253659203 ps
CPU time 3.55 seconds
Started Mar 19 02:33:01 PM PDT 24
Finished Mar 19 02:33:05 PM PDT 24
Peak memory 197952 kb
Host smart-45a769d2-683c-4c08-924b-a6f8b57720d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480218494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3480218494
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4208940015
Short name T81
Test name
Test status
Simulation time 86430731 ps
CPU time 0.65 seconds
Started Mar 19 02:32:58 PM PDT 24
Finished Mar 19 02:32:59 PM PDT 24
Peak memory 195172 kb
Host smart-183df429-9418-4d1e-96c2-3228a23e990d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208940015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.4208940015
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2445120231
Short name T755
Test name
Test status
Simulation time 24284991 ps
CPU time 0.89 seconds
Started Mar 19 02:33:02 PM PDT 24
Finished Mar 19 02:33:05 PM PDT 24
Peak memory 198016 kb
Host smart-a2725ea2-8f82-4c00-a7d3-c20eb11c4688
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445120231 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2445120231
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2929563630
Short name T790
Test name
Test status
Simulation time 44374961 ps
CPU time 0.58 seconds
Started Mar 19 02:32:54 PM PDT 24
Finished Mar 19 02:32:55 PM PDT 24
Peak memory 195236 kb
Host smart-b6427b79-f2cd-4cd7-8e85-c92ca0b324e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929563630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2929563630
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1159846025
Short name T816
Test name
Test status
Simulation time 35785692 ps
CPU time 0.58 seconds
Started Mar 19 02:32:59 PM PDT 24
Finished Mar 19 02:33:00 PM PDT 24
Peak memory 194272 kb
Host smart-09cfca81-ebff-4614-ac85-469e382e1b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159846025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1159846025
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1288631218
Short name T767
Test name
Test status
Simulation time 77443593 ps
CPU time 0.8 seconds
Started Mar 19 02:32:54 PM PDT 24
Finished Mar 19 02:32:55 PM PDT 24
Peak memory 196192 kb
Host smart-2ce1b21b-43aa-4f3f-8fca-1d57cc30585d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288631218 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1288631218
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3138806111
Short name T803
Test name
Test status
Simulation time 491853165 ps
CPU time 1.7 seconds
Started Mar 19 02:33:01 PM PDT 24
Finished Mar 19 02:33:03 PM PDT 24
Peak memory 197996 kb
Host smart-0a50e755-f063-4060-99af-01fe68621936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138806111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3138806111
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.999787497
Short name T802
Test name
Test status
Simulation time 244777154 ps
CPU time 0.89 seconds
Started Mar 19 02:33:00 PM PDT 24
Finished Mar 19 02:33:02 PM PDT 24
Peak memory 197928 kb
Host smart-aa62c42a-1ebd-472d-93e4-17b86a1a3381
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999787497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.999787497
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3602536147
Short name T714
Test name
Test status
Simulation time 101089457 ps
CPU time 0.59 seconds
Started Mar 19 02:34:03 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 193616 kb
Host smart-0408dd41-5c3f-47dd-b703-7ad890b91227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602536147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3602536147
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3687498555
Short name T820
Test name
Test status
Simulation time 18202882 ps
CPU time 0.63 seconds
Started Mar 19 02:34:02 PM PDT 24
Finished Mar 19 02:34:03 PM PDT 24
Peak memory 193676 kb
Host smart-eadbd226-9757-41bc-bac6-7ac833698420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687498555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3687498555
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4237768276
Short name T764
Test name
Test status
Simulation time 10859806 ps
CPU time 0.66 seconds
Started Mar 19 02:34:03 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 194388 kb
Host smart-1c937eb5-9521-420c-b2b7-760391f56542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237768276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4237768276
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2235933265
Short name T832
Test name
Test status
Simulation time 11795153 ps
CPU time 0.63 seconds
Started Mar 19 02:34:04 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 193792 kb
Host smart-0fa7f673-a795-416b-b92d-99a7c5630300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235933265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2235933265
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3891733657
Short name T817
Test name
Test status
Simulation time 94905280 ps
CPU time 0.65 seconds
Started Mar 19 02:34:04 PM PDT 24
Finished Mar 19 02:34:04 PM PDT 24
Peak memory 193704 kb
Host smart-453575ca-aaa8-4392-a132-30ec9d0239e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891733657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3891733657
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.101176923
Short name T743
Test name
Test status
Simulation time 12761561 ps
CPU time 0.65 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:13 PM PDT 24
Peak memory 194396 kb
Host smart-74d5fcba-b47e-4fe4-8103-bce8878c3e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101176923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.101176923
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2974049208
Short name T751
Test name
Test status
Simulation time 31963059 ps
CPU time 0.59 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:12 PM PDT 24
Peak memory 193688 kb
Host smart-4a2c3b7b-9b64-42f9-bf02-eaefefec4bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974049208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2974049208
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4185298174
Short name T727
Test name
Test status
Simulation time 22745367 ps
CPU time 0.61 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:13 PM PDT 24
Peak memory 193624 kb
Host smart-28cf9b1a-7b02-414c-ae2d-55397755e7cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185298174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4185298174
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2586024472
Short name T754
Test name
Test status
Simulation time 17429304 ps
CPU time 0.61 seconds
Started Mar 19 02:34:15 PM PDT 24
Finished Mar 19 02:34:15 PM PDT 24
Peak memory 194376 kb
Host smart-b3b54c3e-a641-410a-8eb0-abf9529f59ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586024472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2586024472
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1470423326
Short name T744
Test name
Test status
Simulation time 17571997 ps
CPU time 0.63 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:13 PM PDT 24
Peak memory 193784 kb
Host smart-eb601611-32a2-413b-b3c8-079ef9d67532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470423326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1470423326
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3831226394
Short name T77
Test name
Test status
Simulation time 33561096 ps
CPU time 0.89 seconds
Started Mar 19 02:32:59 PM PDT 24
Finished Mar 19 02:33:00 PM PDT 24
Peak memory 196180 kb
Host smart-5e366d00-9207-48ea-a858-74571231de9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831226394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3831226394
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.660729305
Short name T772
Test name
Test status
Simulation time 1928034518 ps
CPU time 3.34 seconds
Started Mar 19 02:33:10 PM PDT 24
Finished Mar 19 02:33:14 PM PDT 24
Peak memory 197684 kb
Host smart-f0f57b1f-b0bd-42c3-9146-88abd54c6217
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660729305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.660729305
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1569801429
Short name T796
Test name
Test status
Simulation time 17873813 ps
CPU time 0.68 seconds
Started Mar 19 02:33:12 PM PDT 24
Finished Mar 19 02:33:16 PM PDT 24
Peak memory 195744 kb
Host smart-599dceb8-dc11-4926-a230-1478dac4e81a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569801429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1569801429
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.201905212
Short name T752
Test name
Test status
Simulation time 52035468 ps
CPU time 0.84 seconds
Started Mar 19 02:33:10 PM PDT 24
Finished Mar 19 02:33:11 PM PDT 24
Peak memory 198028 kb
Host smart-922c1314-7e36-4b29-bf18-a6e9fbd656d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201905212 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.201905212
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2571965110
Short name T74
Test name
Test status
Simulation time 30256480 ps
CPU time 0.63 seconds
Started Mar 19 02:33:00 PM PDT 24
Finished Mar 19 02:33:02 PM PDT 24
Peak memory 195036 kb
Host smart-4de53157-0bef-4848-90aa-d78f581cd37f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571965110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2571965110
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2790547250
Short name T787
Test name
Test status
Simulation time 62353456 ps
CPU time 0.6 seconds
Started Mar 19 02:33:11 PM PDT 24
Finished Mar 19 02:33:12 PM PDT 24
Peak memory 194160 kb
Host smart-f8216826-5eeb-4e2c-b499-d728d521ebd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790547250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2790547250
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1179164443
Short name T766
Test name
Test status
Simulation time 28823019 ps
CPU time 0.85 seconds
Started Mar 19 02:33:00 PM PDT 24
Finished Mar 19 02:33:02 PM PDT 24
Peak memory 196452 kb
Host smart-1b3426b3-cae8-4da1-ac27-e8840f02f186
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179164443 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1179164443
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1101899674
Short name T815
Test name
Test status
Simulation time 69205555 ps
CPU time 1.1 seconds
Started Mar 19 02:33:09 PM PDT 24
Finished Mar 19 02:33:11 PM PDT 24
Peak memory 197936 kb
Host smart-2bb01b20-e45f-486f-8768-100a785cb012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101899674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1101899674
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1949813030
Short name T797
Test name
Test status
Simulation time 47355181 ps
CPU time 0.93 seconds
Started Mar 19 02:33:10 PM PDT 24
Finished Mar 19 02:33:11 PM PDT 24
Peak memory 197360 kb
Host smart-5160e42c-5b48-45fe-9ec0-246a669754f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949813030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1949813030
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3672199097
Short name T742
Test name
Test status
Simulation time 33907197 ps
CPU time 0.59 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:13 PM PDT 24
Peak memory 193656 kb
Host smart-def5c931-22d4-4ab2-918a-a3cef3400bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672199097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3672199097
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1390221221
Short name T824
Test name
Test status
Simulation time 15629752 ps
CPU time 0.61 seconds
Started Mar 19 02:34:11 PM PDT 24
Finished Mar 19 02:34:12 PM PDT 24
Peak memory 193632 kb
Host smart-791421e8-969d-4481-b12a-b3d296b6632c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390221221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1390221221
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2019490501
Short name T784
Test name
Test status
Simulation time 31129569 ps
CPU time 0.65 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:13 PM PDT 24
Peak memory 193656 kb
Host smart-495f91a7-f9ae-475f-aab4-d8462c3b3679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019490501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2019490501
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.949676986
Short name T801
Test name
Test status
Simulation time 54672603 ps
CPU time 0.62 seconds
Started Mar 19 02:34:11 PM PDT 24
Finished Mar 19 02:34:12 PM PDT 24
Peak memory 193636 kb
Host smart-f433b6a1-e904-4617-acc7-603b0b62eb64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949676986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.949676986
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.285734957
Short name T720
Test name
Test status
Simulation time 84258126 ps
CPU time 0.59 seconds
Started Mar 19 02:34:11 PM PDT 24
Finished Mar 19 02:34:11 PM PDT 24
Peak memory 194368 kb
Host smart-c8834710-ecf8-4637-8105-5143d473b3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285734957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.285734957
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1624966504
Short name T788
Test name
Test status
Simulation time 36022950 ps
CPU time 0.63 seconds
Started Mar 19 02:34:13 PM PDT 24
Finished Mar 19 02:34:14 PM PDT 24
Peak memory 193804 kb
Host smart-357280a8-7629-4642-bd55-6fc4fe529a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624966504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1624966504
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1770219465
Short name T719
Test name
Test status
Simulation time 39352071 ps
CPU time 0.6 seconds
Started Mar 19 02:34:14 PM PDT 24
Finished Mar 19 02:34:15 PM PDT 24
Peak memory 193620 kb
Host smart-2f2a0ff9-ef13-4444-9ebe-7560f4a83663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770219465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1770219465
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3488769414
Short name T718
Test name
Test status
Simulation time 47160476 ps
CPU time 0.62 seconds
Started Mar 19 02:34:10 PM PDT 24
Finished Mar 19 02:34:11 PM PDT 24
Peak memory 193708 kb
Host smart-38b8fcbb-698d-4362-921b-4fadee445c87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488769414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3488769414
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3875504550
Short name T728
Test name
Test status
Simulation time 20369824 ps
CPU time 0.58 seconds
Started Mar 19 02:34:11 PM PDT 24
Finished Mar 19 02:34:11 PM PDT 24
Peak memory 193660 kb
Host smart-4d6d40cf-d677-4c6b-9439-bdd34b526c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875504550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3875504550
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.651992638
Short name T806
Test name
Test status
Simulation time 19674320 ps
CPU time 0.65 seconds
Started Mar 19 02:34:11 PM PDT 24
Finished Mar 19 02:34:12 PM PDT 24
Peak memory 193712 kb
Host smart-2dfb0388-c36f-4d06-8398-d11323f6e3ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651992638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.651992638
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.227579172
Short name T836
Test name
Test status
Simulation time 14404161 ps
CPU time 0.66 seconds
Started Mar 19 02:33:10 PM PDT 24
Finished Mar 19 02:33:11 PM PDT 24
Peak memory 194436 kb
Host smart-af14c41b-876d-40e2-a79b-1efac122af68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227579172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.227579172
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4129982423
Short name T82
Test name
Test status
Simulation time 204324202 ps
CPU time 2.24 seconds
Started Mar 19 02:33:18 PM PDT 24
Finished Mar 19 02:33:21 PM PDT 24
Peak memory 197944 kb
Host smart-a89e8a86-abea-445f-adf6-7b05f4a1084a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129982423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4129982423
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2151438951
Short name T86
Test name
Test status
Simulation time 15802734 ps
CPU time 0.66 seconds
Started Mar 19 02:33:18 PM PDT 24
Finished Mar 19 02:33:20 PM PDT 24
Peak memory 194824 kb
Host smart-4037b1ea-c308-45dc-a977-a4add16a4308
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151438951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2151438951
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.72749858
Short name T724
Test name
Test status
Simulation time 79641781 ps
CPU time 0.76 seconds
Started Mar 19 02:33:17 PM PDT 24
Finished Mar 19 02:33:19 PM PDT 24
Peak memory 198016 kb
Host smart-c2d025ad-b429-4ce6-9ca0-933b408a341e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72749858 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.72749858
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1919834850
Short name T75
Test name
Test status
Simulation time 50197525 ps
CPU time 0.65 seconds
Started Mar 19 02:33:09 PM PDT 24
Finished Mar 19 02:33:10 PM PDT 24
Peak memory 194932 kb
Host smart-1a4f9e0e-55ed-49bf-bb19-d19cd25ec29a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919834850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1919834850
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2575744274
Short name T721
Test name
Test status
Simulation time 16750866 ps
CPU time 0.61 seconds
Started Mar 19 02:33:18 PM PDT 24
Finished Mar 19 02:33:20 PM PDT 24
Peak memory 193696 kb
Host smart-150d6a80-9b94-4643-87c3-49e6c6ab0f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575744274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2575744274
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2004482278
Short name T80
Test name
Test status
Simulation time 42260981 ps
CPU time 0.93 seconds
Started Mar 19 02:33:09 PM PDT 24
Finished Mar 19 02:33:10 PM PDT 24
Peak memory 197116 kb
Host smart-1291e50f-6f8e-4657-a8de-e5b83dbac4d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004482278 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2004482278
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1571203511
Short name T838
Test name
Test status
Simulation time 39974511 ps
CPU time 1.97 seconds
Started Mar 19 02:33:18 PM PDT 24
Finished Mar 19 02:33:20 PM PDT 24
Peak memory 197988 kb
Host smart-98b874ad-2c11-413e-ac8c-cccd942fd7f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571203511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1571203511
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2127287613
Short name T835
Test name
Test status
Simulation time 175472942 ps
CPU time 1.53 seconds
Started Mar 19 02:33:25 PM PDT 24
Finished Mar 19 02:33:28 PM PDT 24
Peak memory 198036 kb
Host smart-24d73903-171e-465f-8a7f-b89a62d85a7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127287613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2127287613
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2171658702
Short name T779
Test name
Test status
Simulation time 31577608 ps
CPU time 0.61 seconds
Started Mar 19 02:34:15 PM PDT 24
Finished Mar 19 02:34:15 PM PDT 24
Peak memory 193748 kb
Host smart-08fa1785-e579-49aa-b616-c3378c63acae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171658702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2171658702
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1391013597
Short name T741
Test name
Test status
Simulation time 40473423 ps
CPU time 0.64 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:13 PM PDT 24
Peak memory 193776 kb
Host smart-e4b9c8b3-000a-4cf2-ba9f-561af6845e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391013597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1391013597
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.773220757
Short name T760
Test name
Test status
Simulation time 47323665 ps
CPU time 0.61 seconds
Started Mar 19 02:34:11 PM PDT 24
Finished Mar 19 02:34:12 PM PDT 24
Peak memory 193588 kb
Host smart-8aec43a3-4ccc-46b2-a80b-3d6b31a4496a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773220757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.773220757
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1474370548
Short name T729
Test name
Test status
Simulation time 39627240 ps
CPU time 0.63 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:13 PM PDT 24
Peak memory 193784 kb
Host smart-4202e849-ee34-4927-9433-204e30fcb095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474370548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1474370548
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3121328879
Short name T730
Test name
Test status
Simulation time 26486935 ps
CPU time 0.59 seconds
Started Mar 19 02:34:11 PM PDT 24
Finished Mar 19 02:34:12 PM PDT 24
Peak memory 193664 kb
Host smart-7dfb1134-c4db-4671-a665-5549140365bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121328879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3121328879
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2259414332
Short name T795
Test name
Test status
Simulation time 27603236 ps
CPU time 0.59 seconds
Started Mar 19 02:34:14 PM PDT 24
Finished Mar 19 02:34:15 PM PDT 24
Peak memory 193572 kb
Host smart-d81afd8e-f4ea-4d12-ac9d-255deabed45b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259414332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2259414332
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.789041426
Short name T798
Test name
Test status
Simulation time 18768241 ps
CPU time 0.66 seconds
Started Mar 19 02:34:11 PM PDT 24
Finished Mar 19 02:34:12 PM PDT 24
Peak memory 194348 kb
Host smart-510cc14f-20ab-457c-831c-92f43e587640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789041426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.789041426
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1012378397
Short name T726
Test name
Test status
Simulation time 23351032 ps
CPU time 0.6 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:13 PM PDT 24
Peak memory 193688 kb
Host smart-f7f019dc-0756-4b62-af63-b4c8c7508fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012378397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1012378397
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.17958076
Short name T786
Test name
Test status
Simulation time 44707495 ps
CPU time 0.62 seconds
Started Mar 19 02:34:12 PM PDT 24
Finished Mar 19 02:34:13 PM PDT 24
Peak memory 194348 kb
Host smart-ccd5645d-f921-4141-a92e-e351c8fc4f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17958076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.17958076
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.605758703
Short name T807
Test name
Test status
Simulation time 53590782 ps
CPU time 0.62 seconds
Started Mar 19 02:34:22 PM PDT 24
Finished Mar 19 02:34:22 PM PDT 24
Peak memory 193656 kb
Host smart-e6690a45-aede-4b2e-b17f-5f13bd9d16c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605758703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.605758703
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1250372484
Short name T819
Test name
Test status
Simulation time 101076431 ps
CPU time 1.39 seconds
Started Mar 19 02:33:20 PM PDT 24
Finished Mar 19 02:33:22 PM PDT 24
Peak memory 197952 kb
Host smart-db7da075-4317-4e14-b450-7599fe85fb3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250372484 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1250372484
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1565360897
Short name T763
Test name
Test status
Simulation time 36542904 ps
CPU time 0.6 seconds
Started Mar 19 02:33:18 PM PDT 24
Finished Mar 19 02:33:20 PM PDT 24
Peak memory 194732 kb
Host smart-66ba3ef8-ed2f-45f6-a30a-89485df18901
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565360897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1565360897
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.642392783
Short name T771
Test name
Test status
Simulation time 16141317 ps
CPU time 0.62 seconds
Started Mar 19 02:33:24 PM PDT 24
Finished Mar 19 02:33:25 PM PDT 24
Peak memory 194404 kb
Host smart-7f9bd313-0394-494f-80a0-e10a373effd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642392783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.642392783
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3354325606
Short name T94
Test name
Test status
Simulation time 33218859 ps
CPU time 0.71 seconds
Started Mar 19 02:33:18 PM PDT 24
Finished Mar 19 02:33:20 PM PDT 24
Peak memory 194640 kb
Host smart-4efff7d1-ae81-47b9-97ab-8cc5a6614742
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354325606 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3354325606
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1007174067
Short name T747
Test name
Test status
Simulation time 136403500 ps
CPU time 2.56 seconds
Started Mar 19 02:33:18 PM PDT 24
Finished Mar 19 02:33:21 PM PDT 24
Peak memory 198044 kb
Host smart-08ab6054-e0ce-4266-b9e5-da96b737b376
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007174067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1007174067
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.997709823
Short name T834
Test name
Test status
Simulation time 87691577 ps
CPU time 0.94 seconds
Started Mar 19 02:33:18 PM PDT 24
Finished Mar 19 02:33:19 PM PDT 24
Peak memory 197988 kb
Host smart-97bb07ca-aa15-44bb-b22c-417d966c2751
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997709823 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.997709823
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.718192939
Short name T76
Test name
Test status
Simulation time 113760690 ps
CPU time 0.62 seconds
Started Mar 19 02:33:20 PM PDT 24
Finished Mar 19 02:33:21 PM PDT 24
Peak memory 194796 kb
Host smart-565ab18d-2bd0-47c1-be1a-5957fc621432
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718192939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.718192939
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3481820536
Short name T735
Test name
Test status
Simulation time 15760762 ps
CPU time 0.59 seconds
Started Mar 19 02:33:24 PM PDT 24
Finished Mar 19 02:33:25 PM PDT 24
Peak memory 193676 kb
Host smart-88064975-1225-4f22-bd13-ce5265d8b436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481820536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3481820536
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1663454868
Short name T95
Test name
Test status
Simulation time 31245675 ps
CPU time 0.68 seconds
Started Mar 19 02:33:21 PM PDT 24
Finished Mar 19 02:33:22 PM PDT 24
Peak memory 195440 kb
Host smart-289ef6ea-2fb6-4d97-b251-8fe21d1cd4b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663454868 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1663454868
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.661942258
Short name T826
Test name
Test status
Simulation time 86953383 ps
CPU time 1.8 seconds
Started Mar 19 02:33:19 PM PDT 24
Finished Mar 19 02:33:21 PM PDT 24
Peak memory 198068 kb
Host smart-1efaa9fc-7b25-4366-bb43-570710f93156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661942258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.661942258
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1011870143
Short name T46
Test name
Test status
Simulation time 188918204 ps
CPU time 1.45 seconds
Started Mar 19 02:33:19 PM PDT 24
Finished Mar 19 02:33:21 PM PDT 24
Peak memory 198056 kb
Host smart-5e27fe81-e016-4e71-aaea-7201fcffe293
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011870143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1011870143
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.916805248
Short name T722
Test name
Test status
Simulation time 36421067 ps
CPU time 0.95 seconds
Started Mar 19 02:33:26 PM PDT 24
Finished Mar 19 02:33:27 PM PDT 24
Peak memory 198052 kb
Host smart-8aa2f521-b0de-464f-8320-cc1e40fcc883
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916805248 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.916805248
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1251961388
Short name T731
Test name
Test status
Simulation time 18905441 ps
CPU time 0.59 seconds
Started Mar 19 02:33:27 PM PDT 24
Finished Mar 19 02:33:29 PM PDT 24
Peak memory 193304 kb
Host smart-44c96763-4665-40c3-ac3a-9b52a42d9bfc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251961388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1251961388
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1949245247
Short name T789
Test name
Test status
Simulation time 14454341 ps
CPU time 0.59 seconds
Started Mar 19 02:33:27 PM PDT 24
Finished Mar 19 02:33:29 PM PDT 24
Peak memory 193608 kb
Host smart-96edb831-05d4-46da-8eb5-9a5e6d75b76f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949245247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1949245247
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2119631323
Short name T783
Test name
Test status
Simulation time 31463740 ps
CPU time 0.78 seconds
Started Mar 19 02:33:28 PM PDT 24
Finished Mar 19 02:33:30 PM PDT 24
Peak memory 196336 kb
Host smart-1a0198cc-d31e-41d7-8d7a-07cd9b0115e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119631323 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2119631323
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.318723647
Short name T717
Test name
Test status
Simulation time 148878266 ps
CPU time 1.82 seconds
Started Mar 19 02:33:26 PM PDT 24
Finished Mar 19 02:33:30 PM PDT 24
Peak memory 198028 kb
Host smart-92108b2e-dae6-4cfb-b3b2-3a94b17194e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318723647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.318723647
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1953585314
Short name T101
Test name
Test status
Simulation time 499380491 ps
CPU time 0.86 seconds
Started Mar 19 02:33:28 PM PDT 24
Finished Mar 19 02:33:30 PM PDT 24
Peak memory 197892 kb
Host smart-6a1d198e-de3b-45e7-a586-fdd29b785d73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953585314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1953585314
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1488828971
Short name T733
Test name
Test status
Simulation time 20717906 ps
CPU time 0.8 seconds
Started Mar 19 02:33:29 PM PDT 24
Finished Mar 19 02:33:30 PM PDT 24
Peak memory 197952 kb
Host smart-79872011-9d23-4562-b439-95468894416a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488828971 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1488828971
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3292065486
Short name T769
Test name
Test status
Simulation time 12778595 ps
CPU time 0.62 seconds
Started Mar 19 02:33:26 PM PDT 24
Finished Mar 19 02:33:29 PM PDT 24
Peak memory 195460 kb
Host smart-4fd87fd5-4ef7-4c2a-8262-d00816024e59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292065486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3292065486
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.307119459
Short name T833
Test name
Test status
Simulation time 32968207 ps
CPU time 0.66 seconds
Started Mar 19 02:33:25 PM PDT 24
Finished Mar 19 02:33:27 PM PDT 24
Peak memory 193688 kb
Host smart-74397aba-916c-4584-a6e8-40c363b9d3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307119459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.307119459
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.650502918
Short name T93
Test name
Test status
Simulation time 41469415 ps
CPU time 0.95 seconds
Started Mar 19 02:33:27 PM PDT 24
Finished Mar 19 02:33:30 PM PDT 24
Peak memory 196548 kb
Host smart-e0aaeb3d-e7f1-4bdb-9e99-c8258959a110
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650502918 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.650502918
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1330062624
Short name T791
Test name
Test status
Simulation time 36460167 ps
CPU time 1.96 seconds
Started Mar 19 02:33:25 PM PDT 24
Finished Mar 19 02:33:28 PM PDT 24
Peak memory 198020 kb
Host smart-a50aed15-670a-4394-bfd9-99bb5d1cc2bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330062624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1330062624
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.861964373
Short name T32
Test name
Test status
Simulation time 151044656 ps
CPU time 1.52 seconds
Started Mar 19 02:33:26 PM PDT 24
Finished Mar 19 02:33:28 PM PDT 24
Peak memory 198028 kb
Host smart-316424e8-215f-468e-a893-5ad7db712b26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861964373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.861964373
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1060302622
Short name T715
Test name
Test status
Simulation time 111788922 ps
CPU time 1.38 seconds
Started Mar 19 02:33:34 PM PDT 24
Finished Mar 19 02:33:36 PM PDT 24
Peak memory 198024 kb
Host smart-cdd50c0c-5580-4a4b-93c0-454f9d1dc1bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060302622 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1060302622
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2082193153
Short name T774
Test name
Test status
Simulation time 13707129 ps
CPU time 0.58 seconds
Started Mar 19 02:33:37 PM PDT 24
Finished Mar 19 02:33:38 PM PDT 24
Peak memory 193300 kb
Host smart-04ca006b-d75f-4b32-90b2-59a6a0d09fdb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082193153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2082193153
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.588582651
Short name T734
Test name
Test status
Simulation time 22961307 ps
CPU time 0.62 seconds
Started Mar 19 02:33:35 PM PDT 24
Finished Mar 19 02:33:36 PM PDT 24
Peak memory 193744 kb
Host smart-db497a7c-bc5b-49a5-86f8-861d0dff3347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588582651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.588582651
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1359081997
Short name T83
Test name
Test status
Simulation time 18310968 ps
CPU time 0.88 seconds
Started Mar 19 02:33:36 PM PDT 24
Finished Mar 19 02:33:37 PM PDT 24
Peak memory 196536 kb
Host smart-a080e71e-9892-4fda-969b-55e22201431a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359081997 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1359081997
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.826474017
Short name T749
Test name
Test status
Simulation time 41007276 ps
CPU time 2.13 seconds
Started Mar 19 02:33:35 PM PDT 24
Finished Mar 19 02:33:37 PM PDT 24
Peak memory 197956 kb
Host smart-11a84ffe-b8d3-412c-a9b7-ecd2855fa4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826474017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.826474017
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.740287087
Short name T44
Test name
Test status
Simulation time 242497299 ps
CPU time 1.46 seconds
Started Mar 19 02:33:35 PM PDT 24
Finished Mar 19 02:33:36 PM PDT 24
Peak memory 198020 kb
Host smart-47e09624-832f-4a7a-91b5-74a95e4e3dc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740287087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.740287087
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2534098920
Short name T581
Test name
Test status
Simulation time 13193719 ps
CPU time 0.57 seconds
Started Mar 19 02:39:24 PM PDT 24
Finished Mar 19 02:39:25 PM PDT 24
Peak memory 193952 kb
Host smart-0476895c-2544-4b1e-9cc9-b7f14a6b154a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534098920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2534098920
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1266328521
Short name T712
Test name
Test status
Simulation time 28300091 ps
CPU time 0.74 seconds
Started Mar 19 02:39:22 PM PDT 24
Finished Mar 19 02:39:22 PM PDT 24
Peak memory 196044 kb
Host smart-3042fa8d-132f-4e5f-8d24-0809219495ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266328521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1266328521
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2331436311
Short name T349
Test name
Test status
Simulation time 319112670 ps
CPU time 5.05 seconds
Started Mar 19 02:39:27 PM PDT 24
Finished Mar 19 02:39:32 PM PDT 24
Peak memory 196660 kb
Host smart-814f076d-59d4-464b-9a14-712bae114222
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331436311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2331436311
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2689052248
Short name T277
Test name
Test status
Simulation time 222103736 ps
CPU time 0.72 seconds
Started Mar 19 02:39:25 PM PDT 24
Finished Mar 19 02:39:26 PM PDT 24
Peak memory 195524 kb
Host smart-8a9b5ac1-2c1e-4051-9015-00e4789a3e5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689052248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2689052248
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3437192933
Short name T124
Test name
Test status
Simulation time 44496630 ps
CPU time 1.34 seconds
Started Mar 19 02:39:24 PM PDT 24
Finished Mar 19 02:39:26 PM PDT 24
Peak memory 197144 kb
Host smart-d4abb49b-256b-42ce-a152-5a452b70a700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437192933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3437192933
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.71524762
Short name T477
Test name
Test status
Simulation time 92320339 ps
CPU time 1.2 seconds
Started Mar 19 02:39:24 PM PDT 24
Finished Mar 19 02:39:26 PM PDT 24
Peak memory 197112 kb
Host smart-43b40504-0dd3-4d90-a6a7-6dd838da1e21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71524762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.gpio_intr_with_filter_rand_intr_event.71524762
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2222562615
Short name T390
Test name
Test status
Simulation time 271439474 ps
CPU time 3.21 seconds
Started Mar 19 02:39:24 PM PDT 24
Finished Mar 19 02:39:27 PM PDT 24
Peak memory 197104 kb
Host smart-c1e1ff06-db48-4804-a56a-f0ef53d254f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222562615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2222562615
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.759765252
Short name T116
Test name
Test status
Simulation time 40642942 ps
CPU time 0.88 seconds
Started Mar 19 02:39:24 PM PDT 24
Finished Mar 19 02:39:25 PM PDT 24
Peak memory 196728 kb
Host smart-cae7798f-5a85-488f-a4f4-464c6d047e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759765252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.759765252
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3393498189
Short name T626
Test name
Test status
Simulation time 92337543 ps
CPU time 1.1 seconds
Started Mar 19 02:39:24 PM PDT 24
Finished Mar 19 02:39:25 PM PDT 24
Peak memory 195944 kb
Host smart-3f3f0038-e506-4121-a821-54f8b2a6dc15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393498189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3393498189
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.937850245
Short name T577
Test name
Test status
Simulation time 398307366 ps
CPU time 5.19 seconds
Started Mar 19 02:39:24 PM PDT 24
Finished Mar 19 02:39:29 PM PDT 24
Peak memory 197968 kb
Host smart-af164014-c1cf-49d6-8ff2-586254fb1ac1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937850245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.937850245
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1378058692
Short name T35
Test name
Test status
Simulation time 42597865 ps
CPU time 0.86 seconds
Started Mar 19 02:39:25 PM PDT 24
Finished Mar 19 02:39:26 PM PDT 24
Peak memory 213740 kb
Host smart-2b724e64-b268-4ccc-8098-7a89643ff912
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378058692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1378058692
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1980246752
Short name T113
Test name
Test status
Simulation time 36430680 ps
CPU time 1.17 seconds
Started Mar 19 02:39:23 PM PDT 24
Finished Mar 19 02:39:25 PM PDT 24
Peak memory 196256 kb
Host smart-32252517-9f91-4b6e-84e6-796650242ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980246752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1980246752
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2713861691
Short name T495
Test name
Test status
Simulation time 160822276 ps
CPU time 1.27 seconds
Started Mar 19 02:39:22 PM PDT 24
Finished Mar 19 02:39:23 PM PDT 24
Peak memory 197928 kb
Host smart-cf2f1d71-02f4-4a3c-b7ec-f8a71246e791
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713861691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2713861691
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2774035312
Short name T333
Test name
Test status
Simulation time 97234401853 ps
CPU time 162.51 seconds
Started Mar 19 02:39:23 PM PDT 24
Finished Mar 19 02:42:06 PM PDT 24
Peak memory 198116 kb
Host smart-fb522a8e-5efc-4a8a-a384-9f3747a66759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774035312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2774035312
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.2182783574
Short name T60
Test name
Test status
Simulation time 227378436372 ps
CPU time 838.24 seconds
Started Mar 19 02:39:25 PM PDT 24
Finished Mar 19 02:53:23 PM PDT 24
Peak memory 206448 kb
Host smart-da45214b-1599-4394-adf5-5c75c73a5056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2182783574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.2182783574
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2214524790
Short name T631
Test name
Test status
Simulation time 30549311 ps
CPU time 0.61 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:38 PM PDT 24
Peak memory 194636 kb
Host smart-a04bf806-0192-420e-b889-6ec864d05b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214524790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2214524790
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2949526501
Short name T663
Test name
Test status
Simulation time 163606060 ps
CPU time 0.78 seconds
Started Mar 19 02:39:23 PM PDT 24
Finished Mar 19 02:39:24 PM PDT 24
Peak memory 196056 kb
Host smart-fcce76c3-8860-4155-ab5e-68cbfd9e26d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949526501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2949526501
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3151054919
Short name T618
Test name
Test status
Simulation time 3244887920 ps
CPU time 20.07 seconds
Started Mar 19 02:39:23 PM PDT 24
Finished Mar 19 02:39:44 PM PDT 24
Peak memory 197056 kb
Host smart-f8683d91-33c6-4c81-a07a-306860b9f5be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151054919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3151054919
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2203630911
Short name T18
Test name
Test status
Simulation time 1027079345 ps
CPU time 1.09 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:41 PM PDT 24
Peak memory 196680 kb
Host smart-98c514e1-1ede-4348-a7ec-6f909dc36f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203630911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2203630911
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3045750101
Short name T463
Test name
Test status
Simulation time 203980307 ps
CPU time 1.38 seconds
Started Mar 19 02:39:24 PM PDT 24
Finished Mar 19 02:39:26 PM PDT 24
Peak memory 197012 kb
Host smart-ed0f15cc-0078-4336-bb28-ae2c54246c3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045750101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3045750101
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3293111684
Short name T683
Test name
Test status
Simulation time 76975383 ps
CPU time 3.24 seconds
Started Mar 19 02:39:26 PM PDT 24
Finished Mar 19 02:39:29 PM PDT 24
Peak memory 198072 kb
Host smart-b1bb4df7-e921-469a-8292-5d254d22e8b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293111684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3293111684
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.629073495
Short name T19
Test name
Test status
Simulation time 168091560 ps
CPU time 2.14 seconds
Started Mar 19 02:39:26 PM PDT 24
Finished Mar 19 02:39:28 PM PDT 24
Peak memory 198064 kb
Host smart-4a80a9ee-5754-45c2-b5fa-039a0fc27fb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629073495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.629073495
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3323196858
Short name T271
Test name
Test status
Simulation time 129766386 ps
CPU time 0.85 seconds
Started Mar 19 02:39:25 PM PDT 24
Finished Mar 19 02:39:26 PM PDT 24
Peak memory 196236 kb
Host smart-a87290e3-f187-404c-a37d-a75f339060cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323196858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3323196858
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.252840405
Short name T319
Test name
Test status
Simulation time 110629196 ps
CPU time 1.32 seconds
Started Mar 19 02:39:25 PM PDT 24
Finished Mar 19 02:39:26 PM PDT 24
Peak memory 196952 kb
Host smart-a0d17f8e-299e-4b79-9791-29bb2b7ecee9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252840405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.252840405
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3442156145
Short name T238
Test name
Test status
Simulation time 68731555 ps
CPU time 3.16 seconds
Started Mar 19 02:39:35 PM PDT 24
Finished Mar 19 02:39:38 PM PDT 24
Peak memory 197976 kb
Host smart-8aeb0f53-65d4-4756-acbb-8d59d7a936ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442156145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3442156145
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.308791457
Short name T36
Test name
Test status
Simulation time 686099596 ps
CPU time 0.87 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:38 PM PDT 24
Peak memory 213744 kb
Host smart-d23d748f-0ccf-4d9b-a49c-07c42f9c3320
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308791457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.308791457
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.765637134
Short name T620
Test name
Test status
Simulation time 311604124 ps
CPU time 1.25 seconds
Started Mar 19 02:39:25 PM PDT 24
Finished Mar 19 02:39:26 PM PDT 24
Peak memory 196440 kb
Host smart-3bd18ffd-bda8-4d15-9a8e-83fc4ca9c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765637134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.765637134
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2800792385
Short name T515
Test name
Test status
Simulation time 135844877 ps
CPU time 1.28 seconds
Started Mar 19 02:39:25 PM PDT 24
Finished Mar 19 02:39:26 PM PDT 24
Peak memory 197084 kb
Host smart-9d40fdf8-1a6d-4b6d-892d-07f0cacfb09f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800792385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2800792385
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2067257030
Short name T546
Test name
Test status
Simulation time 13746281335 ps
CPU time 92.18 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:41:09 PM PDT 24
Peak memory 198120 kb
Host smart-2f5623ea-eb4d-4436-9c32-7150f8228648
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067257030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2067257030
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.690862876
Short name T37
Test name
Test status
Simulation time 31491904 ps
CPU time 0.56 seconds
Started Mar 19 02:40:03 PM PDT 24
Finished Mar 19 02:40:03 PM PDT 24
Peak memory 193896 kb
Host smart-f6928a77-4e4c-406b-8d4c-0f820c5fe939
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690862876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.690862876
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2863999445
Short name T517
Test name
Test status
Simulation time 43432119 ps
CPU time 0.91 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 196564 kb
Host smart-9785ec79-c07c-41e8-82c6-9b1a67963d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863999445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2863999445
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1025993302
Short name T230
Test name
Test status
Simulation time 650096858 ps
CPU time 18.17 seconds
Started Mar 19 02:40:05 PM PDT 24
Finished Mar 19 02:40:24 PM PDT 24
Peak memory 196696 kb
Host smart-485e6780-c0af-4ea0-9f0d-2755b57666ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025993302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1025993302
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.234932918
Short name T442
Test name
Test status
Simulation time 37144703 ps
CPU time 0.82 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 196688 kb
Host smart-ec528c4b-ced0-440d-9b76-972a36a90056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234932918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.234932918
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2070745917
Short name T537
Test name
Test status
Simulation time 248996233 ps
CPU time 1.29 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 02:40:02 PM PDT 24
Peak memory 196156 kb
Host smart-d1dc6e30-175c-43cf-b747-e2478c961236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070745917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2070745917
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.349828022
Short name T449
Test name
Test status
Simulation time 77764856 ps
CPU time 3.04 seconds
Started Mar 19 02:40:03 PM PDT 24
Finished Mar 19 02:40:06 PM PDT 24
Peak memory 197356 kb
Host smart-3fe0be15-f001-4c4f-a9ce-7e399c18c59e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349828022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.349828022
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1930281995
Short name T312
Test name
Test status
Simulation time 221952655 ps
CPU time 1.42 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 02:40:03 PM PDT 24
Peak memory 196028 kb
Host smart-8267897a-5f04-4331-b231-e0372f432e93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930281995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1930281995
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2503526105
Short name T371
Test name
Test status
Simulation time 108712252 ps
CPU time 0.76 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 195496 kb
Host smart-74cc919f-23b1-4fa0-b800-7d0333d50224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503526105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2503526105
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.447624703
Short name T447
Test name
Test status
Simulation time 31399852 ps
CPU time 1.08 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:01 PM PDT 24
Peak memory 195800 kb
Host smart-9681399d-8e71-47f4-80bc-a4fe830ebed5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447624703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.447624703
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2198620514
Short name T2
Test name
Test status
Simulation time 730060896 ps
CPU time 4.93 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:12 PM PDT 24
Peak memory 197736 kb
Host smart-0cb4cb72-9ecc-49dc-aa6c-86de2c5ba314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198620514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2198620514
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2562379517
Short name T451
Test name
Test status
Simulation time 165004375 ps
CPU time 1.47 seconds
Started Mar 19 02:40:00 PM PDT 24
Finished Mar 19 02:40:01 PM PDT 24
Peak memory 196780 kb
Host smart-0d54a00b-65f4-4fcb-bcfc-cf393d2c4ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562379517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2562379517
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3190014936
Short name T428
Test name
Test status
Simulation time 72601807 ps
CPU time 1.19 seconds
Started Mar 19 02:39:57 PM PDT 24
Finished Mar 19 02:39:58 PM PDT 24
Peak memory 196496 kb
Host smart-63bc7bdd-fa2a-4251-8cc0-04229762da19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190014936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3190014936
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2755296161
Short name T657
Test name
Test status
Simulation time 3150734429 ps
CPU time 44.62 seconds
Started Mar 19 02:39:58 PM PDT 24
Finished Mar 19 02:40:43 PM PDT 24
Peak memory 198240 kb
Host smart-15bcc826-330e-47b1-a557-79905faa6121
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755296161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2755296161
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1400444582
Short name T669
Test name
Test status
Simulation time 199666814891 ps
CPU time 1315.21 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 03:01:56 PM PDT 24
Peak memory 198220 kb
Host smart-6b91dacc-3daf-4140-9807-5caccc603202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1400444582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1400444582
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.858856318
Short name T143
Test name
Test status
Simulation time 87703948 ps
CPU time 0.89 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 02:40:02 PM PDT 24
Peak memory 195296 kb
Host smart-bada56bd-6bc5-4101-bbd8-c22f01f2add8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858856318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.858856318
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1333902415
Short name T287
Test name
Test status
Simulation time 3408215035 ps
CPU time 17.19 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 02:40:19 PM PDT 24
Peak memory 196576 kb
Host smart-f67d4efb-c1ae-4436-95d8-7a9030295309
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333902415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1333902415
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2232575585
Short name T292
Test name
Test status
Simulation time 237349020 ps
CPU time 1.04 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 02:40:03 PM PDT 24
Peak memory 197208 kb
Host smart-870aaf09-39ca-41eb-ad0c-3836345a48f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232575585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2232575585
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1588675644
Short name T508
Test name
Test status
Simulation time 39205613 ps
CPU time 0.68 seconds
Started Mar 19 02:40:03 PM PDT 24
Finished Mar 19 02:40:03 PM PDT 24
Peak memory 194376 kb
Host smart-04405245-aefa-4d53-9a07-4669d7b01525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588675644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1588675644
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3314584107
Short name T625
Test name
Test status
Simulation time 454503991 ps
CPU time 2.62 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:01 PM PDT 24
Peak memory 198092 kb
Host smart-3a68c6bb-b1b8-4c3b-a64f-197090845207
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314584107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3314584107
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4175134029
Short name T354
Test name
Test status
Simulation time 357838294 ps
CPU time 1.37 seconds
Started Mar 19 02:39:58 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 196920 kb
Host smart-fcd0e846-3859-48e0-be5d-ebd28287eb83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175134029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4175134029
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3684988225
Short name T195
Test name
Test status
Simulation time 28549696 ps
CPU time 1.06 seconds
Started Mar 19 02:40:00 PM PDT 24
Finished Mar 19 02:40:01 PM PDT 24
Peak memory 196732 kb
Host smart-247241b0-68c8-47de-a285-97158a7284d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684988225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3684988225
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2657282011
Short name T266
Test name
Test status
Simulation time 140763169 ps
CPU time 0.94 seconds
Started Mar 19 02:39:58 PM PDT 24
Finished Mar 19 02:39:59 PM PDT 24
Peak memory 197184 kb
Host smart-9d9d1c68-3b8e-4501-9565-0d5e1f61d924
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657282011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2657282011
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.772656796
Short name T260
Test name
Test status
Simulation time 314221957 ps
CPU time 1.46 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:01 PM PDT 24
Peak memory 197916 kb
Host smart-191dc940-d7b2-4d9b-b1af-445c60104e40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772656796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.772656796
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2308165098
Short name T52
Test name
Test status
Simulation time 146768410 ps
CPU time 1.21 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 196768 kb
Host smart-14545a8f-c1f5-4541-9088-38e81000e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308165098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2308165098
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2205676925
Short name T237
Test name
Test status
Simulation time 482233399 ps
CPU time 1.21 seconds
Started Mar 19 02:40:04 PM PDT 24
Finished Mar 19 02:40:05 PM PDT 24
Peak memory 195520 kb
Host smart-81ab2ae1-93ba-42af-8001-3a73d986b163
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205676925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2205676925
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2903040085
Short name T128
Test name
Test status
Simulation time 8217255071 ps
CPU time 53.63 seconds
Started Mar 19 02:39:57 PM PDT 24
Finished Mar 19 02:40:51 PM PDT 24
Peak memory 198172 kb
Host smart-35e601f9-93fc-4523-99d8-f631ff2301ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903040085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2903040085
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.2873610116
Short name T30
Test name
Test status
Simulation time 238426708510 ps
CPU time 2017.21 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 03:13:36 PM PDT 24
Peak memory 198144 kb
Host smart-a769a0fd-d16f-4ba0-b735-9294fac93332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2873610116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.2873610116
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1491868076
Short name T274
Test name
Test status
Simulation time 45816533 ps
CPU time 0.6 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 02:40:01 PM PDT 24
Peak memory 193912 kb
Host smart-5ed0895a-47c2-4334-b785-f1002066b7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491868076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1491868076
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1023310550
Short name T695
Test name
Test status
Simulation time 71795469 ps
CPU time 0.87 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 196556 kb
Host smart-ebef083c-3190-4bbf-9793-5ab3a916deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023310550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1023310550
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.256683731
Short name T348
Test name
Test status
Simulation time 210158124 ps
CPU time 3.42 seconds
Started Mar 19 02:40:00 PM PDT 24
Finished Mar 19 02:40:04 PM PDT 24
Peak memory 195916 kb
Host smart-0b378531-8377-434d-aa52-8e2521c66af5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256683731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.256683731
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1496002079
Short name T685
Test name
Test status
Simulation time 1595147169 ps
CPU time 1.28 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 02:40:02 PM PDT 24
Peak memory 197732 kb
Host smart-30b46738-4d45-4c69-a66f-e0422aa5385e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496002079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1496002079
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3688954344
Short name T565
Test name
Test status
Simulation time 161454239 ps
CPU time 1.05 seconds
Started Mar 19 02:40:00 PM PDT 24
Finished Mar 19 02:40:02 PM PDT 24
Peak memory 195972 kb
Host smart-7802ab2f-599b-47a2-ad3f-66b0c3be3199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688954344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3688954344
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1515336858
Short name T66
Test name
Test status
Simulation time 200014698 ps
CPU time 3.86 seconds
Started Mar 19 02:40:04 PM PDT 24
Finished Mar 19 02:40:08 PM PDT 24
Peak memory 198076 kb
Host smart-4c26140a-9830-433e-abae-867da2fb04dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515336858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1515336858
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2441420442
Short name T456
Test name
Test status
Simulation time 1341928920 ps
CPU time 3.65 seconds
Started Mar 19 02:39:58 PM PDT 24
Finished Mar 19 02:40:02 PM PDT 24
Peak memory 196912 kb
Host smart-1bf63e4c-2a89-4177-a9a5-a7c85bce7ab6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441420442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2441420442
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.4015685360
Short name T591
Test name
Test status
Simulation time 293279333 ps
CPU time 0.8 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 196116 kb
Host smart-1015a8cb-d460-4fce-9212-53d4ba710ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015685360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.4015685360
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2262607170
Short name T694
Test name
Test status
Simulation time 295216328 ps
CPU time 1.02 seconds
Started Mar 19 02:40:02 PM PDT 24
Finished Mar 19 02:40:03 PM PDT 24
Peak memory 195924 kb
Host smart-55fb0a9d-1d4c-4896-a7bf-1d5232c15e2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262607170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2262607170
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.609671549
Short name T355
Test name
Test status
Simulation time 71312169 ps
CPU time 1.92 seconds
Started Mar 19 02:40:02 PM PDT 24
Finished Mar 19 02:40:04 PM PDT 24
Peak memory 197892 kb
Host smart-edbf4c01-4bdc-414e-84b1-65082a954dd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609671549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.609671549
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.4181376456
Short name T406
Test name
Test status
Simulation time 54929598 ps
CPU time 1.32 seconds
Started Mar 19 02:40:04 PM PDT 24
Finished Mar 19 02:40:05 PM PDT 24
Peak memory 195468 kb
Host smart-446ac16e-6fc7-4f70-a3cb-c91535d5b753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181376456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.4181376456
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2555408040
Short name T560
Test name
Test status
Simulation time 66237395 ps
CPU time 1.1 seconds
Started Mar 19 02:39:57 PM PDT 24
Finished Mar 19 02:39:58 PM PDT 24
Peak memory 195780 kb
Host smart-cfc0290e-44bc-4664-8805-d65497952f8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555408040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2555408040
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2089170357
Short name T176
Test name
Test status
Simulation time 19056164660 ps
CPU time 161.19 seconds
Started Mar 19 02:40:04 PM PDT 24
Finished Mar 19 02:42:45 PM PDT 24
Peak memory 198208 kb
Host smart-622de463-077c-49f0-9e7d-689045bb3a9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089170357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2089170357
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1047302544
Short name T453
Test name
Test status
Simulation time 23455222 ps
CPU time 0.61 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:08 PM PDT 24
Peak memory 194108 kb
Host smart-7ab84918-c16b-4842-809b-debcd298227d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047302544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1047302544
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1908896339
Short name T473
Test name
Test status
Simulation time 317454959 ps
CPU time 0.68 seconds
Started Mar 19 02:40:02 PM PDT 24
Finished Mar 19 02:40:03 PM PDT 24
Peak memory 194772 kb
Host smart-596d4feb-ae8e-4db2-b335-b85407cda4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908896339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1908896339
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.530280820
Short name T552
Test name
Test status
Simulation time 777761120 ps
CPU time 20.62 seconds
Started Mar 19 02:40:04 PM PDT 24
Finished Mar 19 02:40:25 PM PDT 24
Peak memory 196248 kb
Host smart-aea78477-1ad7-4a46-86ef-4fdbec75b438
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530280820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.530280820
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2856244865
Short name T9
Test name
Test status
Simulation time 82506668 ps
CPU time 1.06 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:09 PM PDT 24
Peak memory 197232 kb
Host smart-d6175fa2-e038-48dd-b0d3-7fd8c61796cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856244865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2856244865
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1455143232
Short name T668
Test name
Test status
Simulation time 120715781 ps
CPU time 0.82 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 196212 kb
Host smart-dcd85db4-3ab0-465b-8076-4c64c31c4026
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455143232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1455143232
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1801319772
Short name T228
Test name
Test status
Simulation time 56464468 ps
CPU time 2.42 seconds
Started Mar 19 02:40:05 PM PDT 24
Finished Mar 19 02:40:08 PM PDT 24
Peak memory 198004 kb
Host smart-d5360586-0bb0-4ad5-8869-54012f153ce6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801319772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1801319772
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2282613503
Short name T703
Test name
Test status
Simulation time 298268227 ps
CPU time 2.98 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:10 PM PDT 24
Peak memory 197120 kb
Host smart-83f78090-fa32-4261-80f0-7350e344ecbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282613503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2282613503
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.149678505
Short name T347
Test name
Test status
Simulation time 31197588 ps
CPU time 1.12 seconds
Started Mar 19 02:39:57 PM PDT 24
Finished Mar 19 02:39:59 PM PDT 24
Peak memory 195780 kb
Host smart-2ce35e1d-0fa3-44b6-b4a5-e9ed3bd1dfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149678505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.149678505
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3233146700
Short name T488
Test name
Test status
Simulation time 91900927 ps
CPU time 1.04 seconds
Started Mar 19 02:40:04 PM PDT 24
Finished Mar 19 02:40:05 PM PDT 24
Peak memory 195920 kb
Host smart-a3eac299-4895-49c6-bb2a-67527910e6d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233146700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3233146700
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1759760645
Short name T481
Test name
Test status
Simulation time 2083420540 ps
CPU time 5.7 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:13 PM PDT 24
Peak memory 197976 kb
Host smart-f7dcabc2-66e2-4604-aef7-aa9f4e68ae13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759760645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1759760645
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1855032171
Short name T14
Test name
Test status
Simulation time 163512374 ps
CPU time 0.91 seconds
Started Mar 19 02:39:58 PM PDT 24
Finished Mar 19 02:39:59 PM PDT 24
Peak memory 195412 kb
Host smart-8cbe395e-bc60-483d-b8aa-eb5402bde537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855032171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1855032171
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.700132131
Short name T499
Test name
Test status
Simulation time 53893075 ps
CPU time 1.13 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 02:40:02 PM PDT 24
Peak memory 195516 kb
Host smart-d6ac7581-a3b7-43fa-88dc-145725743967
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700132131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.700132131
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2214595205
Short name T307
Test name
Test status
Simulation time 16185345669 ps
CPU time 115.75 seconds
Started Mar 19 02:40:06 PM PDT 24
Finished Mar 19 02:42:02 PM PDT 24
Peak memory 198120 kb
Host smart-9deda338-8c4e-4645-93e7-f0b5cd22ab5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214595205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2214595205
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.469714123
Short name T468
Test name
Test status
Simulation time 14081129 ps
CPU time 0.59 seconds
Started Mar 19 02:40:08 PM PDT 24
Finished Mar 19 02:40:09 PM PDT 24
Peak memory 193916 kb
Host smart-b46981a6-8947-4325-8d1e-bfc7becf443d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469714123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.469714123
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2201384976
Short name T120
Test name
Test status
Simulation time 77697144 ps
CPU time 0.84 seconds
Started Mar 19 02:40:06 PM PDT 24
Finished Mar 19 02:40:07 PM PDT 24
Peak memory 196120 kb
Host smart-2f9846b8-82ae-4838-832f-97099de6e8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201384976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2201384976
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2713592118
Short name T678
Test name
Test status
Simulation time 1568601656 ps
CPU time 6.37 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:14 PM PDT 24
Peak memory 196792 kb
Host smart-3aca1ca1-dc74-4f58-b45e-fc6c05e25494
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713592118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2713592118
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2993070055
Short name T27
Test name
Test status
Simulation time 44231788 ps
CPU time 0.83 seconds
Started Mar 19 02:40:06 PM PDT 24
Finished Mar 19 02:40:07 PM PDT 24
Peak memory 196492 kb
Host smart-d9e24f57-42f0-4b49-834c-dea1ae0d7b8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993070055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2993070055
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2074163148
Short name T693
Test name
Test status
Simulation time 330841861 ps
CPU time 1.38 seconds
Started Mar 19 02:40:09 PM PDT 24
Finished Mar 19 02:40:11 PM PDT 24
Peak memory 197016 kb
Host smart-39f9fadb-9862-4f54-8f9d-7327fda1eacd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074163148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2074163148
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3818659449
Short name T409
Test name
Test status
Simulation time 179857646 ps
CPU time 2.11 seconds
Started Mar 19 02:40:06 PM PDT 24
Finished Mar 19 02:40:08 PM PDT 24
Peak memory 198012 kb
Host smart-61d68aaa-2239-4193-9561-ace42c94c94d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818659449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3818659449
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3573946765
Short name T257
Test name
Test status
Simulation time 331687956 ps
CPU time 1.75 seconds
Started Mar 19 02:40:09 PM PDT 24
Finished Mar 19 02:40:11 PM PDT 24
Peak memory 196468 kb
Host smart-bda04778-bc0d-4910-9329-46a09b8349b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573946765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3573946765
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1264521883
Short name T140
Test name
Test status
Simulation time 43997955 ps
CPU time 0.74 seconds
Started Mar 19 02:40:06 PM PDT 24
Finished Mar 19 02:40:07 PM PDT 24
Peak memory 196160 kb
Host smart-d5d64d7d-c1df-45b1-9e26-29dae08318d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264521883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1264521883
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3481416021
Short name T284
Test name
Test status
Simulation time 41499569 ps
CPU time 1.06 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:09 PM PDT 24
Peak memory 195760 kb
Host smart-7d04fd85-1c67-449d-bb00-59a4cf7ce482
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481416021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3481416021
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3939375191
Short name T423
Test name
Test status
Simulation time 230606346 ps
CPU time 4.25 seconds
Started Mar 19 02:40:05 PM PDT 24
Finished Mar 19 02:40:09 PM PDT 24
Peak memory 197916 kb
Host smart-93dd5eca-10dd-45da-a028-730a81c8b59d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939375191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3939375191
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3915635626
Short name T469
Test name
Test status
Simulation time 76624624 ps
CPU time 1.24 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:09 PM PDT 24
Peak memory 195748 kb
Host smart-a56e46e0-a9c2-4d4a-b53e-871a8709f68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915635626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3915635626
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3901245568
Short name T234
Test name
Test status
Simulation time 150760708 ps
CPU time 0.91 seconds
Started Mar 19 02:40:09 PM PDT 24
Finished Mar 19 02:40:10 PM PDT 24
Peak memory 197072 kb
Host smart-0ae96909-f665-4797-89a2-22f9e1441363
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901245568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3901245568
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1158262118
Short name T598
Test name
Test status
Simulation time 15809083698 ps
CPU time 110.48 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:41:58 PM PDT 24
Peak memory 198184 kb
Host smart-e6e5d36b-63e8-4cac-a398-8caa7a84ccee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158262118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1158262118
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2958706689
Short name T59
Test name
Test status
Simulation time 13799198393 ps
CPU time 270.89 seconds
Started Mar 19 02:40:09 PM PDT 24
Finished Mar 19 02:44:40 PM PDT 24
Peak memory 198316 kb
Host smart-87525366-65d2-4f55-a24e-c5432e0a83e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2958706689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2958706689
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1671737340
Short name T47
Test name
Test status
Simulation time 12674535 ps
CPU time 0.59 seconds
Started Mar 19 02:40:08 PM PDT 24
Finished Mar 19 02:40:09 PM PDT 24
Peak memory 194112 kb
Host smart-c42bc2ec-aa05-41c5-865e-aeed76933231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671737340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1671737340
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1896307810
Short name T68
Test name
Test status
Simulation time 25842259 ps
CPU time 0.86 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:08 PM PDT 24
Peak memory 195384 kb
Host smart-ebae4ddc-c500-4d74-92db-a199caafb808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896307810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1896307810
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.558970203
Short name T647
Test name
Test status
Simulation time 258121734 ps
CPU time 14.18 seconds
Started Mar 19 02:40:06 PM PDT 24
Finished Mar 19 02:40:20 PM PDT 24
Peak memory 195456 kb
Host smart-4aee3c46-5476-4d67-965d-9b63856e8793
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558970203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.558970203
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2797592820
Short name T23
Test name
Test status
Simulation time 85171249 ps
CPU time 1.06 seconds
Started Mar 19 02:40:06 PM PDT 24
Finished Mar 19 02:40:07 PM PDT 24
Peak memory 197864 kb
Host smart-a001372b-ff4c-4b19-bdfc-cf77de47be1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797592820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2797592820
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.898046314
Short name T584
Test name
Test status
Simulation time 119060166 ps
CPU time 1.07 seconds
Started Mar 19 02:40:19 PM PDT 24
Finished Mar 19 02:40:21 PM PDT 24
Peak memory 196828 kb
Host smart-57aed22c-fb7f-4930-8415-f9a4f6f8dd40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898046314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.898046314
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3416340799
Short name T666
Test name
Test status
Simulation time 75249493 ps
CPU time 3.03 seconds
Started Mar 19 02:40:13 PM PDT 24
Finished Mar 19 02:40:16 PM PDT 24
Peak memory 198068 kb
Host smart-48173c6a-eff6-4a2e-8954-379e4368cdd3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416340799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3416340799
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4198995339
Short name T276
Test name
Test status
Simulation time 324394551 ps
CPU time 1.72 seconds
Started Mar 19 02:40:08 PM PDT 24
Finished Mar 19 02:40:11 PM PDT 24
Peak memory 196480 kb
Host smart-320a6ea9-b3d7-48ae-9fad-503046ebfc25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198995339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4198995339
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1140302366
Short name T178
Test name
Test status
Simulation time 36032755 ps
CPU time 0.71 seconds
Started Mar 19 02:40:10 PM PDT 24
Finished Mar 19 02:40:11 PM PDT 24
Peak memory 194344 kb
Host smart-544d5ecd-34a5-4f9a-ae0e-3363a84b801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140302366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1140302366
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1503971682
Short name T493
Test name
Test status
Simulation time 26945275 ps
CPU time 0.86 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:09 PM PDT 24
Peak memory 196240 kb
Host smart-89277a4b-0c98-4e2c-a736-18dcb256cb16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503971682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1503971682
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3006727983
Short name T617
Test name
Test status
Simulation time 111775851 ps
CPU time 5.11 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:12 PM PDT 24
Peak memory 197984 kb
Host smart-0f18a282-07d0-439c-9de5-e149a8f4eea8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006727983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3006727983
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2976822474
Short name T675
Test name
Test status
Simulation time 645636176 ps
CPU time 1 seconds
Started Mar 19 02:40:19 PM PDT 24
Finished Mar 19 02:40:20 PM PDT 24
Peak memory 195684 kb
Host smart-b173764d-9e3d-45fe-940d-2d035e7b11c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976822474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2976822474
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1263581499
Short name T107
Test name
Test status
Simulation time 60416152 ps
CPU time 1.15 seconds
Started Mar 19 02:40:11 PM PDT 24
Finished Mar 19 02:40:12 PM PDT 24
Peak memory 195636 kb
Host smart-23219e1e-8847-4d4d-b6e3-61c3753e850b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263581499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1263581499
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.326944846
Short name T232
Test name
Test status
Simulation time 18901065843 ps
CPU time 174.26 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:43:02 PM PDT 24
Peak memory 198236 kb
Host smart-d79df453-ff26-4c20-8747-fe09e49aa49e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326944846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.326944846
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.149714041
Short name T573
Test name
Test status
Simulation time 73370006 ps
CPU time 0.56 seconds
Started Mar 19 02:40:18 PM PDT 24
Finished Mar 19 02:40:20 PM PDT 24
Peak memory 194572 kb
Host smart-a69e0bf1-bcaf-48bc-988c-b0efd74cfbff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149714041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.149714041
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3868455709
Short name T642
Test name
Test status
Simulation time 42593820 ps
CPU time 0.73 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:08 PM PDT 24
Peak memory 195592 kb
Host smart-c9cd2834-07e1-4201-9786-7679914f0424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868455709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3868455709
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3238621713
Short name T25
Test name
Test status
Simulation time 356328718 ps
CPU time 18.79 seconds
Started Mar 19 02:40:10 PM PDT 24
Finished Mar 19 02:40:29 PM PDT 24
Peak memory 196676 kb
Host smart-441f7f12-c7dc-451d-9823-307f9dab845a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238621713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3238621713
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4155680188
Short name T690
Test name
Test status
Simulation time 250104675 ps
CPU time 0.82 seconds
Started Mar 19 02:40:19 PM PDT 24
Finished Mar 19 02:40:20 PM PDT 24
Peak memory 195908 kb
Host smart-0b03b6dd-4839-43ef-94ad-3caa71961bdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155680188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4155680188
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3603417094
Short name T126
Test name
Test status
Simulation time 140388197 ps
CPU time 0.86 seconds
Started Mar 19 02:40:13 PM PDT 24
Finished Mar 19 02:40:14 PM PDT 24
Peak memory 196472 kb
Host smart-570cc17d-1ee5-431e-bcf0-86025aff053a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603417094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3603417094
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2476439173
Short name T243
Test name
Test status
Simulation time 272316997 ps
CPU time 2.85 seconds
Started Mar 19 02:40:10 PM PDT 24
Finished Mar 19 02:40:13 PM PDT 24
Peak memory 198040 kb
Host smart-b4ca7ea8-ee5b-4de9-9b03-10ead10dd31f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476439173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2476439173
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2514985279
Short name T393
Test name
Test status
Simulation time 622327073 ps
CPU time 3.57 seconds
Started Mar 19 02:40:08 PM PDT 24
Finished Mar 19 02:40:12 PM PDT 24
Peak memory 196928 kb
Host smart-e7b0620e-52e0-472e-9835-565cd49cadd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514985279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2514985279
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.573391500
Short name T374
Test name
Test status
Simulation time 172180796 ps
CPU time 0.93 seconds
Started Mar 19 02:40:07 PM PDT 24
Finished Mar 19 02:40:09 PM PDT 24
Peak memory 195796 kb
Host smart-71f1695d-39a6-4eb1-9626-e4a8de2119ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573391500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.573391500
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3174147605
Short name T135
Test name
Test status
Simulation time 42075017 ps
CPU time 1.19 seconds
Started Mar 19 02:40:09 PM PDT 24
Finished Mar 19 02:40:10 PM PDT 24
Peak memory 197356 kb
Host smart-2c09f124-a28d-47b1-8914-ef0b4133e493
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174147605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3174147605
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2842943884
Short name T112
Test name
Test status
Simulation time 190727091 ps
CPU time 3.45 seconds
Started Mar 19 02:40:13 PM PDT 24
Finished Mar 19 02:40:16 PM PDT 24
Peak memory 197960 kb
Host smart-9f1d2d27-ce26-4e49-8ab4-e457ee63125a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842943884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2842943884
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.289313046
Short name T556
Test name
Test status
Simulation time 196443247 ps
CPU time 1.09 seconds
Started Mar 19 02:40:05 PM PDT 24
Finished Mar 19 02:40:07 PM PDT 24
Peak memory 195692 kb
Host smart-8f307fed-7131-4fe6-a61d-5fa70420b81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289313046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.289313046
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2434990039
Short name T596
Test name
Test status
Simulation time 171826838 ps
CPU time 0.97 seconds
Started Mar 19 02:40:18 PM PDT 24
Finished Mar 19 02:40:20 PM PDT 24
Peak memory 195664 kb
Host smart-69fadad1-f33c-4204-b622-bfb97f747df4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434990039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2434990039
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1697555457
Short name T164
Test name
Test status
Simulation time 5043935658 ps
CPU time 123.5 seconds
Started Mar 19 02:40:08 PM PDT 24
Finished Mar 19 02:42:12 PM PDT 24
Peak memory 198416 kb
Host smart-9810f479-2023-4a5f-809a-3f51c96d7582
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697555457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1697555457
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2331763002
Short name T487
Test name
Test status
Simulation time 37374927114 ps
CPU time 298.45 seconds
Started Mar 19 02:40:19 PM PDT 24
Finished Mar 19 02:45:18 PM PDT 24
Peak memory 198168 kb
Host smart-cf60abe2-7403-4b22-a750-5c5ba7a613ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2331763002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2331763002
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.156850029
Short name T707
Test name
Test status
Simulation time 13593528 ps
CPU time 0.58 seconds
Started Mar 19 02:40:14 PM PDT 24
Finished Mar 19 02:40:15 PM PDT 24
Peak memory 194128 kb
Host smart-89346c28-6f0b-455b-b1b8-b84be825f10c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156850029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.156850029
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2674229334
Short name T361
Test name
Test status
Simulation time 15715760 ps
CPU time 0.65 seconds
Started Mar 19 02:40:22 PM PDT 24
Finished Mar 19 02:40:23 PM PDT 24
Peak memory 194664 kb
Host smart-b11fdae9-32d3-48b6-8af3-caf4dbd8594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674229334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2674229334
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.517772646
Short name T219
Test name
Test status
Simulation time 3330221352 ps
CPU time 28.43 seconds
Started Mar 19 02:40:22 PM PDT 24
Finished Mar 19 02:40:51 PM PDT 24
Peak memory 197584 kb
Host smart-cf6eaad8-81b1-4b8c-81ba-0a580761beec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517772646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.517772646
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3503968881
Short name T121
Test name
Test status
Simulation time 223768993 ps
CPU time 0.7 seconds
Started Mar 19 02:40:14 PM PDT 24
Finished Mar 19 02:40:15 PM PDT 24
Peak memory 195512 kb
Host smart-078ccb08-d77e-469c-bb42-35cd8aeb018a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503968881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3503968881
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3127615843
Short name T341
Test name
Test status
Simulation time 56090769 ps
CPU time 0.7 seconds
Started Mar 19 02:40:21 PM PDT 24
Finished Mar 19 02:40:22 PM PDT 24
Peak memory 195176 kb
Host smart-ab35a118-db62-4358-b14e-b29757443b28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127615843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3127615843
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2437050093
Short name T175
Test name
Test status
Simulation time 46173963 ps
CPU time 1.06 seconds
Started Mar 19 02:40:21 PM PDT 24
Finished Mar 19 02:40:22 PM PDT 24
Peak memory 196828 kb
Host smart-629367bb-534e-48d3-ad6e-991640fab69a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437050093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2437050093
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.675768913
Short name T708
Test name
Test status
Simulation time 500696475 ps
CPU time 2.61 seconds
Started Mar 19 02:40:23 PM PDT 24
Finished Mar 19 02:40:26 PM PDT 24
Peak memory 197088 kb
Host smart-930c468e-71dd-434a-92a7-8888c089e246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675768913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
675768913
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.4037832924
Short name T12
Test name
Test status
Simulation time 288398406 ps
CPU time 1.35 seconds
Started Mar 19 02:40:17 PM PDT 24
Finished Mar 19 02:40:19 PM PDT 24
Peak memory 196868 kb
Host smart-ac1a883b-af41-4a14-8438-376181a6bad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037832924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.4037832924
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1419946030
Short name T343
Test name
Test status
Simulation time 60860661 ps
CPU time 1.23 seconds
Started Mar 19 02:40:23 PM PDT 24
Finished Mar 19 02:40:24 PM PDT 24
Peak memory 197016 kb
Host smart-09e6a8e1-6137-45c0-929d-e87b69e47542
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419946030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1419946030
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2338117362
Short name T417
Test name
Test status
Simulation time 216305136 ps
CPU time 1.82 seconds
Started Mar 19 02:40:22 PM PDT 24
Finished Mar 19 02:40:25 PM PDT 24
Peak memory 197972 kb
Host smart-7e8a4901-deb8-4df4-8453-76370590b208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338117362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2338117362
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3600000002
Short name T250
Test name
Test status
Simulation time 215117627 ps
CPU time 0.97 seconds
Started Mar 19 02:40:09 PM PDT 24
Finished Mar 19 02:40:10 PM PDT 24
Peak memory 195980 kb
Host smart-295f42ff-c68f-4875-8753-d29c2b7cf3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600000002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3600000002
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1897269295
Short name T193
Test name
Test status
Simulation time 226514656 ps
CPU time 1.26 seconds
Started Mar 19 02:40:09 PM PDT 24
Finished Mar 19 02:40:11 PM PDT 24
Peak memory 196484 kb
Host smart-0f6a489b-4c07-4e92-9b3e-7e8728e916de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897269295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1897269295
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1333077784
Short name T638
Test name
Test status
Simulation time 3373607185 ps
CPU time 94.91 seconds
Started Mar 19 02:40:21 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 198120 kb
Host smart-3e239699-b30e-403e-800a-cebb0d0cc665
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333077784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1333077784
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3002498062
Short name T64
Test name
Test status
Simulation time 46986909251 ps
CPU time 637.77 seconds
Started Mar 19 02:40:22 PM PDT 24
Finished Mar 19 02:51:00 PM PDT 24
Peak memory 198188 kb
Host smart-b079e7b2-09d3-41d9-9cd9-4f35ac7be346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3002498062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3002498062
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.88804159
Short name T664
Test name
Test status
Simulation time 64315610 ps
CPU time 0.59 seconds
Started Mar 19 02:40:27 PM PDT 24
Finished Mar 19 02:40:28 PM PDT 24
Peak memory 193952 kb
Host smart-2fa5eaaf-d429-4fb2-b6bc-35074c867447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88804159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.88804159
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1035322108
Short name T497
Test name
Test status
Simulation time 144066808 ps
CPU time 0.99 seconds
Started Mar 19 02:40:21 PM PDT 24
Finished Mar 19 02:40:22 PM PDT 24
Peak memory 196480 kb
Host smart-d61c8395-f7e3-43e3-bc3b-b682ebf57210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035322108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1035322108
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.4209597668
Short name T599
Test name
Test status
Simulation time 315122056 ps
CPU time 9.4 seconds
Started Mar 19 02:40:29 PM PDT 24
Finished Mar 19 02:40:38 PM PDT 24
Peak memory 196768 kb
Host smart-d3176a4b-0f6e-4eec-92f0-e0b43ad52aee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209597668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4209597668
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3007379141
Short name T22
Test name
Test status
Simulation time 57079983 ps
CPU time 0.89 seconds
Started Mar 19 02:40:32 PM PDT 24
Finished Mar 19 02:40:34 PM PDT 24
Peak memory 196040 kb
Host smart-34d334a0-6f39-4617-84bd-e826c4d16091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007379141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3007379141
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3624517395
Short name T465
Test name
Test status
Simulation time 76402324 ps
CPU time 0.66 seconds
Started Mar 19 02:40:22 PM PDT 24
Finished Mar 19 02:40:23 PM PDT 24
Peak memory 194124 kb
Host smart-504e748e-b370-4120-a035-d9c7f107a02a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624517395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3624517395
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3999907135
Short name T395
Test name
Test status
Simulation time 37814020 ps
CPU time 1.13 seconds
Started Mar 19 02:40:23 PM PDT 24
Finished Mar 19 02:40:24 PM PDT 24
Peak memory 197104 kb
Host smart-0421a340-e012-4fd0-af11-3a5bd199a7f1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999907135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3999907135
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2120612735
Short name T461
Test name
Test status
Simulation time 140721344 ps
CPU time 2.93 seconds
Started Mar 19 02:40:21 PM PDT 24
Finished Mar 19 02:40:25 PM PDT 24
Peak memory 195888 kb
Host smart-af3a5c32-6c72-422d-95b5-45bb4777139c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120612735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2120612735
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1436133953
Short name T156
Test name
Test status
Simulation time 79723653 ps
CPU time 0.79 seconds
Started Mar 19 02:40:15 PM PDT 24
Finished Mar 19 02:40:16 PM PDT 24
Peak memory 196124 kb
Host smart-a3f2b557-d36f-419f-b5d0-d669f11c05ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436133953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1436133953
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2316928230
Short name T279
Test name
Test status
Simulation time 142317073 ps
CPU time 1.37 seconds
Started Mar 19 02:40:20 PM PDT 24
Finished Mar 19 02:40:22 PM PDT 24
Peak memory 197020 kb
Host smart-ae04c1b7-f2f9-41c3-aa6b-2588e4d14224
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316928230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2316928230
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1905748266
Short name T357
Test name
Test status
Simulation time 28793335 ps
CPU time 1.54 seconds
Started Mar 19 02:40:32 PM PDT 24
Finished Mar 19 02:40:34 PM PDT 24
Peak memory 197964 kb
Host smart-8a3d7c7f-c43a-4eeb-8118-78b2716f5b9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905748266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1905748266
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3088770604
Short name T610
Test name
Test status
Simulation time 146918588 ps
CPU time 0.88 seconds
Started Mar 19 02:40:25 PM PDT 24
Finished Mar 19 02:40:26 PM PDT 24
Peak memory 196472 kb
Host smart-e0964d57-7123-476b-9d58-60eff8911be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088770604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3088770604
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.821422987
Short name T674
Test name
Test status
Simulation time 173381632 ps
CPU time 1.36 seconds
Started Mar 19 02:40:22 PM PDT 24
Finished Mar 19 02:40:23 PM PDT 24
Peak memory 196544 kb
Host smart-1badac8b-d409-4f72-aa21-af99775a4d69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821422987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.821422987
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2587162545
Short name T6
Test name
Test status
Simulation time 31702019925 ps
CPU time 82.39 seconds
Started Mar 19 02:40:27 PM PDT 24
Finished Mar 19 02:41:50 PM PDT 24
Peak memory 198136 kb
Host smart-7419000f-5826-43ff-8aab-bbbe589cb620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587162545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2587162545
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.20901213
Short name T523
Test name
Test status
Simulation time 47985655 ps
CPU time 0.55 seconds
Started Mar 19 02:40:28 PM PDT 24
Finished Mar 19 02:40:29 PM PDT 24
Peak memory 192768 kb
Host smart-ab6755d4-c75f-4806-8a59-6fa56d0b8c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20901213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.20901213
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2736571776
Short name T606
Test name
Test status
Simulation time 48429551 ps
CPU time 0.8 seconds
Started Mar 19 02:40:26 PM PDT 24
Finished Mar 19 02:40:27 PM PDT 24
Peak memory 195948 kb
Host smart-d11aa75f-ec44-41f8-a576-225cd2bb3478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736571776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2736571776
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2179434708
Short name T285
Test name
Test status
Simulation time 865672858 ps
CPU time 7.18 seconds
Started Mar 19 02:40:26 PM PDT 24
Finished Mar 19 02:40:34 PM PDT 24
Peak memory 196740 kb
Host smart-f67ef068-276b-4a71-a707-d29a499de444
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179434708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2179434708
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.4058785183
Short name T457
Test name
Test status
Simulation time 326820627 ps
CPU time 1.02 seconds
Started Mar 19 02:40:28 PM PDT 24
Finished Mar 19 02:40:29 PM PDT 24
Peak memory 196580 kb
Host smart-076e5aaa-8803-4dce-a693-d8ec8a305785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058785183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.4058785183
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3306968102
Short name T110
Test name
Test status
Simulation time 48851522 ps
CPU time 1.43 seconds
Started Mar 19 02:40:27 PM PDT 24
Finished Mar 19 02:40:29 PM PDT 24
Peak memory 195844 kb
Host smart-17865208-6ef5-4d1f-ba21-273e80439c75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306968102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3306968102
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.855736315
Short name T199
Test name
Test status
Simulation time 286745863 ps
CPU time 2.93 seconds
Started Mar 19 02:40:29 PM PDT 24
Finished Mar 19 02:40:32 PM PDT 24
Peak memory 198052 kb
Host smart-fba0599d-db62-40a1-92f9-53e6a4b09300
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855736315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.855736315
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1633564522
Short name T216
Test name
Test status
Simulation time 407202773 ps
CPU time 3.07 seconds
Started Mar 19 02:40:32 PM PDT 24
Finished Mar 19 02:40:35 PM PDT 24
Peak memory 196976 kb
Host smart-82e047ed-7bf8-445c-975d-952ee70a889b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633564522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1633564522
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3625599774
Short name T711
Test name
Test status
Simulation time 74873121 ps
CPU time 0.72 seconds
Started Mar 19 02:40:25 PM PDT 24
Finished Mar 19 02:40:26 PM PDT 24
Peak memory 196132 kb
Host smart-2e5a2ab8-fc2a-4ea6-a4f1-06f206dd836f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625599774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3625599774
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1475835723
Short name T489
Test name
Test status
Simulation time 41958571 ps
CPU time 1.14 seconds
Started Mar 19 02:40:26 PM PDT 24
Finished Mar 19 02:40:28 PM PDT 24
Peak memory 195796 kb
Host smart-0b3d35e4-c09f-4aec-adf3-361a9b9b06ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475835723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1475835723
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1455013271
Short name T528
Test name
Test status
Simulation time 536921672 ps
CPU time 2.24 seconds
Started Mar 19 02:40:24 PM PDT 24
Finished Mar 19 02:40:27 PM PDT 24
Peak memory 197960 kb
Host smart-7b74e5b5-fdec-4344-8cc6-780ba8019800
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455013271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1455013271
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2140313189
Short name T282
Test name
Test status
Simulation time 70116180 ps
CPU time 1.31 seconds
Started Mar 19 02:40:32 PM PDT 24
Finished Mar 19 02:40:34 PM PDT 24
Peak memory 197964 kb
Host smart-b0a7631c-593d-45ac-adc1-afe920e12b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140313189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2140313189
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.202636933
Short name T687
Test name
Test status
Simulation time 111497693 ps
CPU time 0.81 seconds
Started Mar 19 02:40:33 PM PDT 24
Finished Mar 19 02:40:34 PM PDT 24
Peak memory 194128 kb
Host smart-43ac5761-860e-43d8-968b-74c3d76d4f69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202636933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.202636933
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.169125765
Short name T567
Test name
Test status
Simulation time 4389412762 ps
CPU time 48.56 seconds
Started Mar 19 02:40:27 PM PDT 24
Finished Mar 19 02:41:16 PM PDT 24
Peak memory 198100 kb
Host smart-f05a5303-8618-40b2-85c7-12eac9daf8d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169125765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.169125765
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3256237163
Short name T658
Test name
Test status
Simulation time 25597704 ps
CPU time 0.56 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:41 PM PDT 24
Peak memory 193472 kb
Host smart-0163f7d0-d8ed-4161-b4e8-86ccf7f19367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256237163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3256237163
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2229009988
Short name T180
Test name
Test status
Simulation time 81727385 ps
CPU time 0.71 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:38 PM PDT 24
Peak memory 195172 kb
Host smart-bf3b707e-e41b-428b-a347-5fd1c126966e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229009988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2229009988
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1508795783
Short name T612
Test name
Test status
Simulation time 2809138498 ps
CPU time 27.4 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:40:05 PM PDT 24
Peak memory 198080 kb
Host smart-f7335650-2bb5-499a-8167-69bce1e315d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508795783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1508795783
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3133139672
Short name T440
Test name
Test status
Simulation time 63115740 ps
CPU time 0.91 seconds
Started Mar 19 02:39:35 PM PDT 24
Finished Mar 19 02:39:36 PM PDT 24
Peak memory 196176 kb
Host smart-bc97ee55-b634-4dca-bebc-c8219ad492bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133139672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3133139672
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3658951270
Short name T73
Test name
Test status
Simulation time 372076038 ps
CPU time 1.35 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:39 PM PDT 24
Peak memory 195704 kb
Host smart-eff44a1f-c599-4e6b-b4d6-58ba9517076e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658951270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3658951270
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.371312845
Short name T69
Test name
Test status
Simulation time 76875952 ps
CPU time 3.26 seconds
Started Mar 19 02:39:39 PM PDT 24
Finished Mar 19 02:39:42 PM PDT 24
Peak memory 198032 kb
Host smart-eb3e31aa-6ebf-48ad-8314-b005670d6165
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371312845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.371312845
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2809959221
Short name T492
Test name
Test status
Simulation time 190166495 ps
CPU time 3.36 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:44 PM PDT 24
Peak memory 197092 kb
Host smart-0dab0107-29bf-4e12-922c-a85c64344fa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809959221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2809959221
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1763891516
Short name T524
Test name
Test status
Simulation time 910448984 ps
CPU time 1.17 seconds
Started Mar 19 02:39:36 PM PDT 24
Finished Mar 19 02:39:37 PM PDT 24
Peak memory 196552 kb
Host smart-64abd078-61d0-4dab-9c09-248d24f7bf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763891516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1763891516
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.561020155
Short name T233
Test name
Test status
Simulation time 19608320 ps
CPU time 0.69 seconds
Started Mar 19 02:39:36 PM PDT 24
Finished Mar 19 02:39:36 PM PDT 24
Peak memory 194444 kb
Host smart-2fe55de2-70f1-48b0-b6b0-25da06c6fe46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561020155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.561020155
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3487947913
Short name T522
Test name
Test status
Simulation time 434223859 ps
CPU time 5.1 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:46 PM PDT 24
Peak memory 197936 kb
Host smart-c69589cc-4b63-4fa8-86d2-f5496b87f1b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487947913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3487947913
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.2808373571
Short name T470
Test name
Test status
Simulation time 121316602 ps
CPU time 1.2 seconds
Started Mar 19 02:39:38 PM PDT 24
Finished Mar 19 02:39:39 PM PDT 24
Peak memory 196444 kb
Host smart-3062f4d6-b81f-4636-97c9-9b9200baaf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808373571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2808373571
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3894614853
Short name T655
Test name
Test status
Simulation time 181362325 ps
CPU time 1 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:42 PM PDT 24
Peak memory 197064 kb
Host smart-ce1c5353-3841-4bf2-a241-051e6c78a7aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894614853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3894614853
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3204087933
Short name T700
Test name
Test status
Simulation time 5042906433 ps
CPU time 128.39 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:41:45 PM PDT 24
Peak memory 198184 kb
Host smart-0cf6f1ee-6901-4a0d-9b05-0b425fddad57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204087933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3204087933
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2133763811
Short name T394
Test name
Test status
Simulation time 54761036 ps
CPU time 0.58 seconds
Started Mar 19 02:40:24 PM PDT 24
Finished Mar 19 02:40:25 PM PDT 24
Peak memory 193928 kb
Host smart-0b611865-6fd0-465f-909e-3af11aa397d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133763811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2133763811
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1790595902
Short name T13
Test name
Test status
Simulation time 45938979 ps
CPU time 0.89 seconds
Started Mar 19 02:40:25 PM PDT 24
Finished Mar 19 02:40:26 PM PDT 24
Peak memory 196584 kb
Host smart-7c4be53c-e0e8-46ac-b8ab-965ecac3a30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790595902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1790595902
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1304521477
Short name T275
Test name
Test status
Simulation time 802200493 ps
CPU time 22.82 seconds
Started Mar 19 02:40:28 PM PDT 24
Finished Mar 19 02:40:51 PM PDT 24
Peak memory 196724 kb
Host smart-78bd2894-5340-46be-b8c2-aabcb254442d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304521477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1304521477
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2500140119
Short name T21
Test name
Test status
Simulation time 62272760 ps
CPU time 0.85 seconds
Started Mar 19 02:40:25 PM PDT 24
Finished Mar 19 02:40:26 PM PDT 24
Peak memory 196056 kb
Host smart-0a0b678e-de93-46ce-a11f-fa97f4aa37d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500140119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2500140119
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4139729034
Short name T308
Test name
Test status
Simulation time 65912356 ps
CPU time 1.11 seconds
Started Mar 19 02:40:29 PM PDT 24
Finished Mar 19 02:40:31 PM PDT 24
Peak memory 196688 kb
Host smart-5763c0b9-9926-4807-bb97-e7d09a59ef6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139729034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4139729034
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.231567603
Short name T682
Test name
Test status
Simulation time 86388814 ps
CPU time 3.04 seconds
Started Mar 19 02:40:26 PM PDT 24
Finished Mar 19 02:40:30 PM PDT 24
Peak memory 198120 kb
Host smart-0bc074d4-6905-4d06-86c4-c74f98cd40a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231567603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.231567603
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3486573413
Short name T702
Test name
Test status
Simulation time 1022337260 ps
CPU time 1.91 seconds
Started Mar 19 02:40:29 PM PDT 24
Finished Mar 19 02:40:31 PM PDT 24
Peak memory 195768 kb
Host smart-f1f3d401-1373-4278-925d-67763bc1c332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486573413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3486573413
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.4134714738
Short name T54
Test name
Test status
Simulation time 31809971 ps
CPU time 1.1 seconds
Started Mar 19 02:40:26 PM PDT 24
Finished Mar 19 02:40:28 PM PDT 24
Peak memory 196812 kb
Host smart-99ac9bad-ef99-470a-8b8f-f11416c63c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134714738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.4134714738
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3594697285
Short name T439
Test name
Test status
Simulation time 85940350 ps
CPU time 1.07 seconds
Started Mar 19 02:40:28 PM PDT 24
Finished Mar 19 02:40:30 PM PDT 24
Peak memory 195996 kb
Host smart-a6af0abe-d151-4f4c-a5c2-c73b9586448a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594697285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3594697285
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.813874065
Short name T295
Test name
Test status
Simulation time 876275524 ps
CPU time 2.26 seconds
Started Mar 19 02:40:29 PM PDT 24
Finished Mar 19 02:40:32 PM PDT 24
Peak memory 197964 kb
Host smart-f56f2303-cdf3-4d99-82dd-68793853874e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813874065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.813874065
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.684402532
Short name T490
Test name
Test status
Simulation time 88223450 ps
CPU time 0.79 seconds
Started Mar 19 02:40:25 PM PDT 24
Finished Mar 19 02:40:26 PM PDT 24
Peak memory 195172 kb
Host smart-f115ede3-9007-416e-9662-87d1c19d75c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684402532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.684402532
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.6444034
Short name T498
Test name
Test status
Simulation time 143643318 ps
CPU time 1.14 seconds
Started Mar 19 02:40:24 PM PDT 24
Finished Mar 19 02:40:26 PM PDT 24
Peak memory 196476 kb
Host smart-8d7e367a-c834-419a-a327-dba7e8b4315e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6444034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.6444034
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3816560497
Short name T437
Test name
Test status
Simulation time 6617348503 ps
CPU time 68.37 seconds
Started Mar 19 02:40:26 PM PDT 24
Finished Mar 19 02:41:35 PM PDT 24
Peak memory 191768 kb
Host smart-096017ae-d8c0-4ecb-9ee6-0286caeba60f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816560497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3816560497
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1364401607
Short name T304
Test name
Test status
Simulation time 14530426 ps
CPU time 0.57 seconds
Started Mar 19 02:40:37 PM PDT 24
Finished Mar 19 02:40:38 PM PDT 24
Peak memory 194100 kb
Host smart-52abfd8d-47ee-4767-b059-9b4557d0c5a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364401607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1364401607
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.405947637
Short name T511
Test name
Test status
Simulation time 52195527 ps
CPU time 0.87 seconds
Started Mar 19 02:40:27 PM PDT 24
Finished Mar 19 02:40:29 PM PDT 24
Peak memory 196520 kb
Host smart-44528b91-4bc0-4ed2-b1eb-72757f6a00f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405947637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.405947637
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3433860329
Short name T420
Test name
Test status
Simulation time 2214636751 ps
CPU time 14.39 seconds
Started Mar 19 02:40:36 PM PDT 24
Finished Mar 19 02:40:50 PM PDT 24
Peak memory 196288 kb
Host smart-89fee58a-326e-41c0-ae1a-aed4f8ffba74
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433860329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3433860329
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2878327773
Short name T589
Test name
Test status
Simulation time 63594517 ps
CPU time 0.77 seconds
Started Mar 19 02:40:37 PM PDT 24
Finished Mar 19 02:40:37 PM PDT 24
Peak memory 195904 kb
Host smart-2aee8621-9695-47db-9c9b-d579aa377b62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878327773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2878327773
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.470281442
Short name T566
Test name
Test status
Simulation time 517033109 ps
CPU time 1.21 seconds
Started Mar 19 02:40:26 PM PDT 24
Finished Mar 19 02:40:28 PM PDT 24
Peak memory 196744 kb
Host smart-59a46c18-824f-4939-abc0-350d2af15adb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470281442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.470281442
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3654599140
Short name T429
Test name
Test status
Simulation time 389724879 ps
CPU time 3.43 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:40:42 PM PDT 24
Peak memory 197504 kb
Host smart-bc73bad2-78f2-431c-8d85-a7e671c907b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654599140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3654599140
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.908528282
Short name T593
Test name
Test status
Simulation time 115812299 ps
CPU time 2.68 seconds
Started Mar 19 02:40:35 PM PDT 24
Finished Mar 19 02:40:38 PM PDT 24
Peak memory 195796 kb
Host smart-c2accecf-cb2c-4ad7-9385-3925faabb88e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908528282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
908528282
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2697518892
Short name T127
Test name
Test status
Simulation time 42367661 ps
CPU time 0.92 seconds
Started Mar 19 02:40:26 PM PDT 24
Finished Mar 19 02:40:27 PM PDT 24
Peak memory 195928 kb
Host smart-838316e7-d1ce-4410-8618-dbffe5099c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697518892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2697518892
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.906609974
Short name T645
Test name
Test status
Simulation time 24728212 ps
CPU time 0.76 seconds
Started Mar 19 02:40:32 PM PDT 24
Finished Mar 19 02:40:33 PM PDT 24
Peak memory 195364 kb
Host smart-0ceb3598-a4bb-4860-af08-b48da6449187
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906609974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.906609974
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3532549231
Short name T388
Test name
Test status
Simulation time 2107036972 ps
CPU time 5.86 seconds
Started Mar 19 02:40:40 PM PDT 24
Finished Mar 19 02:40:47 PM PDT 24
Peak memory 198020 kb
Host smart-57c1a03c-f2a2-4b72-b47e-9dd25f54ec5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532549231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3532549231
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1420479389
Short name T641
Test name
Test status
Simulation time 41177094 ps
CPU time 0.9 seconds
Started Mar 19 02:40:25 PM PDT 24
Finished Mar 19 02:40:26 PM PDT 24
Peak memory 195424 kb
Host smart-fa6bac97-393e-4601-a7bc-4c46207e8ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420479389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1420479389
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.750894230
Short name T311
Test name
Test status
Simulation time 106491467 ps
CPU time 1.02 seconds
Started Mar 19 02:40:26 PM PDT 24
Finished Mar 19 02:40:28 PM PDT 24
Peak memory 195612 kb
Host smart-5b205739-626e-4e42-9f87-cc64466a6284
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750894230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.750894230
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.676319409
Short name T8
Test name
Test status
Simulation time 5180114920 ps
CPU time 33.65 seconds
Started Mar 19 02:40:36 PM PDT 24
Finished Mar 19 02:41:10 PM PDT 24
Peak memory 198168 kb
Host smart-34b9588b-1bc0-42d9-85b6-71f9a0013f86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676319409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.676319409
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.274439965
Short name T544
Test name
Test status
Simulation time 38276618 ps
CPU time 0.58 seconds
Started Mar 19 02:40:36 PM PDT 24
Finished Mar 19 02:40:37 PM PDT 24
Peak memory 193920 kb
Host smart-11e4a099-9ecf-4269-b969-fc3760eaafc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274439965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.274439965
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1362674057
Short name T283
Test name
Test status
Simulation time 74902986 ps
CPU time 0.92 seconds
Started Mar 19 02:40:37 PM PDT 24
Finished Mar 19 02:40:38 PM PDT 24
Peak memory 197112 kb
Host smart-f86207eb-c8c7-4612-b3f6-8776f8352939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362674057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1362674057
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.4173108553
Short name T689
Test name
Test status
Simulation time 779961807 ps
CPU time 13.29 seconds
Started Mar 19 02:40:36 PM PDT 24
Finished Mar 19 02:40:50 PM PDT 24
Peak memory 196856 kb
Host smart-ff8755c0-f3ee-41ab-af29-f03ad4737749
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173108553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.4173108553
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1398850498
Short name T543
Test name
Test status
Simulation time 55095760 ps
CPU time 0.99 seconds
Started Mar 19 02:40:34 PM PDT 24
Finished Mar 19 02:40:35 PM PDT 24
Peak memory 197920 kb
Host smart-fa8cbd8a-2e57-4eb3-9609-986e757286a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398850498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1398850498
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3461820167
Short name T494
Test name
Test status
Simulation time 211642190 ps
CPU time 1.36 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:40:40 PM PDT 24
Peak memory 197136 kb
Host smart-29447ff7-c258-4f78-a927-1429c4eebe19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461820167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3461820167
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2767964095
Short name T413
Test name
Test status
Simulation time 166333157 ps
CPU time 3.27 seconds
Started Mar 19 02:40:35 PM PDT 24
Finished Mar 19 02:40:38 PM PDT 24
Peak memory 197856 kb
Host smart-fdc456b4-9d8d-4863-a3df-99ca423aeb21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767964095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2767964095
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1302859153
Short name T141
Test name
Test status
Simulation time 106476625 ps
CPU time 2.56 seconds
Started Mar 19 02:40:37 PM PDT 24
Finished Mar 19 02:40:40 PM PDT 24
Peak memory 197052 kb
Host smart-cd5420f2-809a-417e-8e70-0d21cb8922fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302859153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1302859153
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.4065434506
Short name T564
Test name
Test status
Simulation time 65522799 ps
CPU time 1.28 seconds
Started Mar 19 02:40:39 PM PDT 24
Finished Mar 19 02:40:41 PM PDT 24
Peak memory 198096 kb
Host smart-cf0a4fb6-520a-4b8b-875b-dd924ea2cd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065434506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.4065434506
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3087002338
Short name T572
Test name
Test status
Simulation time 13243973 ps
CPU time 0.67 seconds
Started Mar 19 02:40:36 PM PDT 24
Finished Mar 19 02:40:36 PM PDT 24
Peak memory 195156 kb
Host smart-d8a4e4ff-b87a-4317-8c95-48b4c194a962
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087002338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3087002338
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4083168570
Short name T117
Test name
Test status
Simulation time 281600660 ps
CPU time 2.59 seconds
Started Mar 19 02:40:40 PM PDT 24
Finished Mar 19 02:40:43 PM PDT 24
Peak memory 197732 kb
Host smart-84291031-d906-4a45-9bfa-aaed089c0ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083168570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.4083168570
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.891343525
Short name T300
Test name
Test status
Simulation time 433425909 ps
CPU time 1.39 seconds
Started Mar 19 02:40:35 PM PDT 24
Finished Mar 19 02:40:37 PM PDT 24
Peak memory 195640 kb
Host smart-8b3f2464-16ee-402e-b8a0-11f94b064457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891343525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.891343525
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2541362493
Short name T684
Test name
Test status
Simulation time 354693107 ps
CPU time 1.3 seconds
Started Mar 19 02:40:35 PM PDT 24
Finished Mar 19 02:40:36 PM PDT 24
Peak memory 195492 kb
Host smart-084b8d48-17dc-427e-80af-b56657bdde91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541362493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2541362493
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.798125774
Short name T303
Test name
Test status
Simulation time 16046290298 ps
CPU time 53.04 seconds
Started Mar 19 02:40:37 PM PDT 24
Finished Mar 19 02:41:30 PM PDT 24
Peak memory 198188 kb
Host smart-d3132019-e0a1-4a30-bb29-4c6004d7097c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798125774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.798125774
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2325298652
Short name T644
Test name
Test status
Simulation time 144934968868 ps
CPU time 453.59 seconds
Started Mar 19 02:40:36 PM PDT 24
Finished Mar 19 02:48:10 PM PDT 24
Peak memory 198172 kb
Host smart-42ba04b1-f0c3-4a8c-92e8-e0d80f0cd4e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2325298652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2325298652
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.823796998
Short name T471
Test name
Test status
Simulation time 42996142 ps
CPU time 0.56 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:40:39 PM PDT 24
Peak memory 194540 kb
Host smart-2c22b392-edc3-4dcf-b754-d359480d2566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823796998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.823796998
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3624663332
Short name T549
Test name
Test status
Simulation time 114470697 ps
CPU time 0.78 seconds
Started Mar 19 02:40:40 PM PDT 24
Finished Mar 19 02:40:41 PM PDT 24
Peak memory 195184 kb
Host smart-db86275c-1106-47ec-926b-c9bd9f05cf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624663332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3624663332
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.344410197
Short name T187
Test name
Test status
Simulation time 3611342041 ps
CPU time 26.93 seconds
Started Mar 19 02:40:36 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 196936 kb
Host smart-7d7fabb4-0acb-4e26-a437-b3470fa416e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344410197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.344410197
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3735873330
Short name T559
Test name
Test status
Simulation time 135969880 ps
CPU time 0.89 seconds
Started Mar 19 02:40:36 PM PDT 24
Finished Mar 19 02:40:37 PM PDT 24
Peak memory 197204 kb
Host smart-76eb792e-28ba-4805-8aad-5572e94dee1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735873330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3735873330
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1473921635
Short name T661
Test name
Test status
Simulation time 54350376 ps
CPU time 0.75 seconds
Started Mar 19 02:40:37 PM PDT 24
Finished Mar 19 02:40:38 PM PDT 24
Peak memory 195084 kb
Host smart-66d40947-7891-49b2-bbbf-bc556fe71283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473921635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1473921635
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3646447700
Short name T188
Test name
Test status
Simulation time 25581916 ps
CPU time 1.1 seconds
Started Mar 19 02:40:39 PM PDT 24
Finished Mar 19 02:40:41 PM PDT 24
Peak memory 197080 kb
Host smart-c802c822-5451-446b-811d-ff020694c8ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646447700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3646447700
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1575734874
Short name T137
Test name
Test status
Simulation time 373219841 ps
CPU time 2.11 seconds
Started Mar 19 02:40:37 PM PDT 24
Finished Mar 19 02:40:40 PM PDT 24
Peak memory 196456 kb
Host smart-eef85d41-cebb-462e-b1b2-b6a600a31eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575734874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1575734874
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1069074555
Short name T455
Test name
Test status
Simulation time 216330927 ps
CPU time 1.09 seconds
Started Mar 19 02:40:36 PM PDT 24
Finished Mar 19 02:40:37 PM PDT 24
Peak memory 196524 kb
Host smart-8293ef4b-904f-4587-83bf-2c77dbc4bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069074555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1069074555
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3351416732
Short name T326
Test name
Test status
Simulation time 37260197 ps
CPU time 0.94 seconds
Started Mar 19 02:40:39 PM PDT 24
Finished Mar 19 02:40:40 PM PDT 24
Peak memory 196688 kb
Host smart-1fca4c6f-2bf8-4dfe-8183-908abcf58675
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351416732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3351416732
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4056400001
Short name T583
Test name
Test status
Simulation time 77215082 ps
CPU time 1.5 seconds
Started Mar 19 02:40:35 PM PDT 24
Finished Mar 19 02:40:36 PM PDT 24
Peak memory 198024 kb
Host smart-b0e7fd73-b7dd-44cd-ac5a-157568b45fca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056400001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4056400001
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2904171447
Short name T586
Test name
Test status
Simulation time 107804766 ps
CPU time 0.8 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:40:39 PM PDT 24
Peak memory 195300 kb
Host smart-9ea791f1-c680-4b03-92eb-9fff425a5474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904171447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2904171447
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.459590427
Short name T649
Test name
Test status
Simulation time 50311238 ps
CPU time 1.32 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:40:40 PM PDT 24
Peak memory 196684 kb
Host smart-4e9c6ea3-90d3-47bc-a95f-9345c51c4d07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459590427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.459590427
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.4183417191
Short name T570
Test name
Test status
Simulation time 108646305344 ps
CPU time 170.88 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:43:29 PM PDT 24
Peak memory 198212 kb
Host smart-c0c8656e-bd08-453c-9c4c-6680d4beba84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183417191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.4183417191
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3482444942
Short name T177
Test name
Test status
Simulation time 31555159 ps
CPU time 0.59 seconds
Started Mar 19 02:40:47 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 194588 kb
Host smart-ad12c71f-3796-44ed-8102-5e41b6eaf7d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482444942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3482444942
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3005683948
Short name T220
Test name
Test status
Simulation time 36625416 ps
CPU time 0.89 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:40:39 PM PDT 24
Peak memory 195216 kb
Host smart-b35fea9e-3a76-434a-a1fe-c867cb774366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005683948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3005683948
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2869125206
Short name T434
Test name
Test status
Simulation time 178574000 ps
CPU time 10.09 seconds
Started Mar 19 02:40:39 PM PDT 24
Finished Mar 19 02:40:50 PM PDT 24
Peak memory 196252 kb
Host smart-78f00154-59aa-4d3c-8dd3-bf53141b807c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869125206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2869125206
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.692395691
Short name T268
Test name
Test status
Simulation time 85108194 ps
CPU time 0.93 seconds
Started Mar 19 02:40:44 PM PDT 24
Finished Mar 19 02:40:46 PM PDT 24
Peak memory 197104 kb
Host smart-622cbc8f-821b-43f5-87c4-65e7e383a98e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692395691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.692395691
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.19195115
Short name T632
Test name
Test status
Simulation time 348410027 ps
CPU time 0.97 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:40:40 PM PDT 24
Peak memory 196060 kb
Host smart-95b6cd09-f47a-4935-94e9-67bc346ac0f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19195115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.19195115
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2748568943
Short name T288
Test name
Test status
Simulation time 86687028 ps
CPU time 3.54 seconds
Started Mar 19 02:40:40 PM PDT 24
Finished Mar 19 02:40:44 PM PDT 24
Peak memory 198100 kb
Host smart-c1815b62-39cc-4652-a6f0-eb25c6d33e71
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748568943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2748568943
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2941959689
Short name T241
Test name
Test status
Simulation time 492548836 ps
CPU time 3.37 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:40:42 PM PDT 24
Peak memory 197864 kb
Host smart-d5e74031-4e93-41b8-9bd6-68da9ad48a03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941959689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2941959689
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3729984753
Short name T106
Test name
Test status
Simulation time 39285205 ps
CPU time 0.87 seconds
Started Mar 19 02:40:35 PM PDT 24
Finished Mar 19 02:40:36 PM PDT 24
Peak memory 196628 kb
Host smart-19140b3b-015e-4ef2-ae0f-e3ed6a5f9151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729984753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3729984753
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3800501693
Short name T155
Test name
Test status
Simulation time 23353671 ps
CPU time 0.93 seconds
Started Mar 19 02:40:38 PM PDT 24
Finished Mar 19 02:40:39 PM PDT 24
Peak memory 196032 kb
Host smart-36ceb389-5c3f-4468-a706-6f4c29546ca1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800501693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3800501693
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.100600769
Short name T254
Test name
Test status
Simulation time 127489636 ps
CPU time 6.19 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:52 PM PDT 24
Peak memory 197992 kb
Host smart-4c678459-dc54-423f-9c62-3dee5904e596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100600769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.100600769
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2744092193
Short name T136
Test name
Test status
Simulation time 75989332 ps
CPU time 1.35 seconds
Started Mar 19 02:40:37 PM PDT 24
Finished Mar 19 02:40:38 PM PDT 24
Peak memory 195516 kb
Host smart-6cdfe027-cc5e-4e6d-aa43-1f58b70c0396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744092193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2744092193
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2040525193
Short name T154
Test name
Test status
Simulation time 680799067 ps
CPU time 1.24 seconds
Started Mar 19 02:40:34 PM PDT 24
Finished Mar 19 02:40:35 PM PDT 24
Peak memory 195740 kb
Host smart-c58ba71f-0219-47c3-b6ee-de3f2bc2cfab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040525193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2040525193
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4242742259
Short name T210
Test name
Test status
Simulation time 28222270652 ps
CPU time 213.41 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:44:19 PM PDT 24
Peak memory 198180 kb
Host smart-ecac31ad-c490-49ef-a75b-becdd30f5ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242742259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4242742259
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2236733232
Short name T432
Test name
Test status
Simulation time 15587882 ps
CPU time 0.59 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:46 PM PDT 24
Peak memory 195656 kb
Host smart-a3677ca5-2223-4e5a-b463-69cf2a5459c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236733232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2236733232
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1545254163
Short name T145
Test name
Test status
Simulation time 58997186 ps
CPU time 0.74 seconds
Started Mar 19 02:40:47 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 195248 kb
Host smart-f21a1c5b-878d-4adc-afe1-a280efad0697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545254163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1545254163
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1921428587
Short name T72
Test name
Test status
Simulation time 7244238726 ps
CPU time 20.21 seconds
Started Mar 19 02:40:48 PM PDT 24
Finished Mar 19 02:41:08 PM PDT 24
Peak memory 197556 kb
Host smart-e2b5f600-c611-466f-929d-de637e5ab9a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921428587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1921428587
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2359820248
Short name T676
Test name
Test status
Simulation time 64770056 ps
CPU time 0.99 seconds
Started Mar 19 02:40:46 PM PDT 24
Finished Mar 19 02:40:47 PM PDT 24
Peak memory 196524 kb
Host smart-7b721020-ba47-4693-a4a9-d45ccf97b5be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359820248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2359820248
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3730834702
Short name T458
Test name
Test status
Simulation time 44304256 ps
CPU time 0.9 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:46 PM PDT 24
Peak memory 196552 kb
Host smart-e3e02340-a4c5-4bf4-8aae-531d656b93e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730834702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3730834702
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.53663516
Short name T198
Test name
Test status
Simulation time 75875966 ps
CPU time 2.37 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:47 PM PDT 24
Peak memory 196496 kb
Host smart-3b6fe966-d8b5-41c0-a5d3-13b03f8e64e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53663516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.53663516
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.805133912
Short name T389
Test name
Test status
Simulation time 37448111 ps
CPU time 0.7 seconds
Started Mar 19 02:40:44 PM PDT 24
Finished Mar 19 02:40:45 PM PDT 24
Peak memory 194296 kb
Host smart-ecb50823-cdf5-4c32-b036-dbed63f759da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805133912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.805133912
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2508451331
Short name T157
Test name
Test status
Simulation time 34465659 ps
CPU time 1.23 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:47 PM PDT 24
Peak memory 195856 kb
Host smart-b86cd7cf-5535-49ee-8f37-b9a84eb5fccb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508451331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2508451331
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2350085491
Short name T379
Test name
Test status
Simulation time 162968069 ps
CPU time 2.66 seconds
Started Mar 19 02:40:46 PM PDT 24
Finished Mar 19 02:40:49 PM PDT 24
Peak memory 197332 kb
Host smart-8fda1c54-9023-4402-9285-240136d3f159
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350085491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2350085491
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1905196372
Short name T410
Test name
Test status
Simulation time 59187909 ps
CPU time 1.57 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:46 PM PDT 24
Peak memory 197976 kb
Host smart-e1ba3be5-7a8a-492f-ac5b-01361f5a51c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905196372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1905196372
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.471313258
Short name T185
Test name
Test status
Simulation time 111439550 ps
CPU time 0.77 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:46 PM PDT 24
Peak memory 195160 kb
Host smart-0a797c09-aaf0-4aae-816b-cf7e25bda744
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471313258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.471313258
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.953013965
Short name T152
Test name
Test status
Simulation time 1661239481 ps
CPU time 38.52 seconds
Started Mar 19 02:40:44 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 198076 kb
Host smart-dc334494-7269-43e0-9c20-b280aa70f50b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953013965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.953013965
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2560133387
Short name T640
Test name
Test status
Simulation time 14339546 ps
CPU time 0.6 seconds
Started Mar 19 02:40:47 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 194612 kb
Host smart-aa0226d5-5dd4-46ac-a013-1c66723f9237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560133387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2560133387
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3074648831
Short name T261
Test name
Test status
Simulation time 162961709 ps
CPU time 0.67 seconds
Started Mar 19 02:40:46 PM PDT 24
Finished Mar 19 02:40:47 PM PDT 24
Peak memory 194112 kb
Host smart-b36d9487-82c4-48e3-9e3f-eac3b02fd927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074648831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3074648831
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3822989432
Short name T602
Test name
Test status
Simulation time 186608082 ps
CPU time 9.83 seconds
Started Mar 19 02:40:48 PM PDT 24
Finished Mar 19 02:40:58 PM PDT 24
Peak memory 197996 kb
Host smart-81fcd8ff-2fbe-4e91-8ab8-5a02bc6cc68c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822989432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3822989432
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3459199966
Short name T436
Test name
Test status
Simulation time 132906342 ps
CPU time 1.03 seconds
Started Mar 19 02:40:43 PM PDT 24
Finished Mar 19 02:40:45 PM PDT 24
Peak memory 196648 kb
Host smart-e11d06fe-8de9-420f-9c19-e48feffbba0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459199966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3459199966
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3156059427
Short name T397
Test name
Test status
Simulation time 153668698 ps
CPU time 0.9 seconds
Started Mar 19 02:40:46 PM PDT 24
Finished Mar 19 02:40:47 PM PDT 24
Peak memory 195532 kb
Host smart-78636753-8506-41c8-aa4e-13358c5413da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156059427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3156059427
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4116053818
Short name T553
Test name
Test status
Simulation time 641991499 ps
CPU time 3.29 seconds
Started Mar 19 02:40:44 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 198108 kb
Host smart-15d65911-caf6-483f-ba28-f41865d353a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116053818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4116053818
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.552107585
Short name T600
Test name
Test status
Simulation time 89077053 ps
CPU time 2.06 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:47 PM PDT 24
Peak memory 195784 kb
Host smart-8dd4bd0a-3f52-4d92-9d97-92125ae87a2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552107585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
552107585
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3967230994
Short name T259
Test name
Test status
Simulation time 73113200 ps
CPU time 0.91 seconds
Started Mar 19 02:40:48 PM PDT 24
Finished Mar 19 02:40:49 PM PDT 24
Peak memory 195952 kb
Host smart-875a6c67-b36b-4e81-b8f5-838974ca5722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967230994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3967230994
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3975540568
Short name T571
Test name
Test status
Simulation time 26205433 ps
CPU time 1.01 seconds
Started Mar 19 02:40:43 PM PDT 24
Finished Mar 19 02:40:45 PM PDT 24
Peak memory 195908 kb
Host smart-be34c171-a85d-4376-b700-28ac68b8ca29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975540568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3975540568
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_smoke.2333789288
Short name T201
Test name
Test status
Simulation time 85192420 ps
CPU time 1.2 seconds
Started Mar 19 02:40:48 PM PDT 24
Finished Mar 19 02:40:49 PM PDT 24
Peak memory 195856 kb
Host smart-80773ab4-27e9-458e-ae61-28e2c23e2ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333789288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2333789288
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.291514319
Short name T464
Test name
Test status
Simulation time 30851712 ps
CPU time 1.05 seconds
Started Mar 19 02:40:43 PM PDT 24
Finished Mar 19 02:40:44 PM PDT 24
Peak memory 196408 kb
Host smart-805b4a28-3efe-49d0-8b91-5202fb329e9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291514319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.291514319
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2173783054
Short name T318
Test name
Test status
Simulation time 13547486831 ps
CPU time 187.99 seconds
Started Mar 19 02:40:46 PM PDT 24
Finished Mar 19 02:43:54 PM PDT 24
Peak memory 198148 kb
Host smart-3d973517-6c8d-4d78-944c-ba1818bdd11f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173783054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2173783054
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.69176131
Short name T545
Test name
Test status
Simulation time 32969528 ps
CPU time 0.56 seconds
Started Mar 19 02:40:49 PM PDT 24
Finished Mar 19 02:40:49 PM PDT 24
Peak memory 193908 kb
Host smart-3e99c83d-5fca-45b5-b782-fa913b29d6ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69176131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.69176131
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.687868844
Short name T55
Test name
Test status
Simulation time 33334063 ps
CPU time 0.74 seconds
Started Mar 19 02:40:44 PM PDT 24
Finished Mar 19 02:40:46 PM PDT 24
Peak memory 196076 kb
Host smart-7f26bad3-8b44-4a97-9069-066367c8bb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687868844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.687868844
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2840895735
Short name T356
Test name
Test status
Simulation time 99688148 ps
CPU time 5.29 seconds
Started Mar 19 02:40:46 PM PDT 24
Finished Mar 19 02:40:51 PM PDT 24
Peak memory 197044 kb
Host smart-1ff415f1-e6a8-48c5-bd7b-0fea31178d09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840895735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2840895735
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1250846831
Short name T24
Test name
Test status
Simulation time 75348419 ps
CPU time 0.73 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:46 PM PDT 24
Peak memory 194648 kb
Host smart-6d743cc1-7992-4910-a03f-7846bbf081e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250846831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1250846831
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.297752167
Short name T479
Test name
Test status
Simulation time 60218039 ps
CPU time 0.8 seconds
Started Mar 19 02:40:46 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 195608 kb
Host smart-2083f796-bace-4b2f-a781-01cc41438b33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297752167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.297752167
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2479717377
Short name T181
Test name
Test status
Simulation time 1111383542 ps
CPU time 2.54 seconds
Started Mar 19 02:40:46 PM PDT 24
Finished Mar 19 02:40:49 PM PDT 24
Peak memory 198092 kb
Host smart-0aef8691-5cea-43e0-811b-f7cbe74ac092
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479717377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2479717377
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.4115364315
Short name T209
Test name
Test status
Simulation time 416406681 ps
CPU time 1.84 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:47 PM PDT 24
Peak memory 196776 kb
Host smart-04453c8b-20b5-460f-b123-be5a5348fec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115364315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.4115364315
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.747538057
Short name T214
Test name
Test status
Simulation time 23984854 ps
CPU time 0.91 seconds
Started Mar 19 02:40:49 PM PDT 24
Finished Mar 19 02:40:50 PM PDT 24
Peak memory 195872 kb
Host smart-d819aa97-01a1-4712-9e19-50042d37719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747538057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.747538057
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3113724516
Short name T174
Test name
Test status
Simulation time 29334971 ps
CPU time 0.72 seconds
Started Mar 19 02:40:47 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 194432 kb
Host smart-3c324e36-d937-4701-8c30-bf8cae66ec98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113724516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3113724516
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2038877927
Short name T272
Test name
Test status
Simulation time 138182375 ps
CPU time 1.71 seconds
Started Mar 19 02:40:46 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 197696 kb
Host smart-a55d723f-1bb5-491d-bd35-a03be5294293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038877927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2038877927
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.551468035
Short name T419
Test name
Test status
Simulation time 258061319 ps
CPU time 1.18 seconds
Started Mar 19 02:40:47 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 196412 kb
Host smart-74cfbb0d-fb42-4487-925e-659f7ff9d163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551468035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.551468035
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2946888194
Short name T396
Test name
Test status
Simulation time 65280846 ps
CPU time 1.22 seconds
Started Mar 19 02:40:47 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 195604 kb
Host smart-177dcdf4-cb54-4946-a034-10d064145377
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946888194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2946888194
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2035731870
Short name T10
Test name
Test status
Simulation time 101921526268 ps
CPU time 143.57 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:43:09 PM PDT 24
Peak memory 198176 kb
Host smart-72034d67-7bfc-4ed3-8c55-4b2a800bb465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035731870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2035731870
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1494019327
Short name T551
Test name
Test status
Simulation time 670848148560 ps
CPU time 3074.59 seconds
Started Mar 19 02:40:48 PM PDT 24
Finished Mar 19 03:32:03 PM PDT 24
Peak memory 198248 kb
Host smart-1cf70c6c-809a-4a02-b18d-8cb2c4b6e6a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1494019327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1494019327
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.420411382
Short name T578
Test name
Test status
Simulation time 24238541 ps
CPU time 0.6 seconds
Started Mar 19 02:40:53 PM PDT 24
Finished Mar 19 02:40:54 PM PDT 24
Peak memory 194088 kb
Host smart-0b2169a1-0558-4d64-8171-c04f7f359005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420411382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.420411382
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3767527447
Short name T138
Test name
Test status
Simulation time 93136474 ps
CPU time 0.89 seconds
Started Mar 19 02:40:49 PM PDT 24
Finished Mar 19 02:40:50 PM PDT 24
Peak memory 195992 kb
Host smart-51395b06-b7c3-4610-8e51-8bc8b66fd7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767527447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3767527447
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3243213732
Short name T244
Test name
Test status
Simulation time 569216200 ps
CPU time 16.92 seconds
Started Mar 19 02:40:53 PM PDT 24
Finished Mar 19 02:41:10 PM PDT 24
Peak memory 197988 kb
Host smart-7c0ed475-34f0-4c6c-ac5d-f7a3168894d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243213732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3243213732
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1662204397
Short name T414
Test name
Test status
Simulation time 37044532 ps
CPU time 0.7 seconds
Started Mar 19 02:40:53 PM PDT 24
Finished Mar 19 02:40:54 PM PDT 24
Peak memory 194856 kb
Host smart-4ea9c748-0bec-46ff-882f-4809af7d9563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662204397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1662204397
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.10380791
Short name T550
Test name
Test status
Simulation time 60188907 ps
CPU time 1.13 seconds
Started Mar 19 02:40:43 PM PDT 24
Finished Mar 19 02:40:45 PM PDT 24
Peak memory 195912 kb
Host smart-463acb1c-68e7-49cc-84a8-f0d345e26bc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10380791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.10380791
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2178704092
Short name T448
Test name
Test status
Simulation time 323140238 ps
CPU time 3.29 seconds
Started Mar 19 02:40:47 PM PDT 24
Finished Mar 19 02:40:51 PM PDT 24
Peak memory 197980 kb
Host smart-a0e7fd94-f3c4-45d4-8175-059aa2be8de0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178704092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2178704092
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1445041825
Short name T595
Test name
Test status
Simulation time 83892445 ps
CPU time 2.51 seconds
Started Mar 19 02:40:47 PM PDT 24
Finished Mar 19 02:40:50 PM PDT 24
Peak memory 197204 kb
Host smart-5cc04b65-04f8-4eec-8aa0-cf8b2e914e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445041825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1445041825
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3255783065
Short name T153
Test name
Test status
Simulation time 16880370 ps
CPU time 0.71 seconds
Started Mar 19 02:40:45 PM PDT 24
Finished Mar 19 02:40:46 PM PDT 24
Peak memory 195012 kb
Host smart-6e9ca343-502f-4bff-8da5-0252b6b8d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255783065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3255783065
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2530983367
Short name T476
Test name
Test status
Simulation time 40370060 ps
CPU time 1.29 seconds
Started Mar 19 02:40:48 PM PDT 24
Finished Mar 19 02:40:49 PM PDT 24
Peak memory 197040 kb
Host smart-34ab70af-e7b0-41eb-9568-0826b4f8f7c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530983367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2530983367
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2511534563
Short name T4
Test name
Test status
Simulation time 357131917 ps
CPU time 5.09 seconds
Started Mar 19 02:40:54 PM PDT 24
Finished Mar 19 02:40:59 PM PDT 24
Peak memory 198044 kb
Host smart-53dc34f9-1b85-4f78-932f-f32cb467092e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511534563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2511534563
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2518639467
Short name T253
Test name
Test status
Simulation time 45671461 ps
CPU time 1.15 seconds
Started Mar 19 02:40:49 PM PDT 24
Finished Mar 19 02:40:50 PM PDT 24
Peak memory 196184 kb
Host smart-9180e691-8158-4f40-9175-ec8b0536ee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518639467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2518639467
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.220621898
Short name T624
Test name
Test status
Simulation time 41746339 ps
CPU time 0.81 seconds
Started Mar 19 02:40:48 PM PDT 24
Finished Mar 19 02:40:48 PM PDT 24
Peak memory 195924 kb
Host smart-8521b072-a2c2-48a3-ad3b-5cb97fb9ba2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220621898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.220621898
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2294481563
Short name T226
Test name
Test status
Simulation time 31671932698 ps
CPU time 104.61 seconds
Started Mar 19 02:41:00 PM PDT 24
Finished Mar 19 02:42:46 PM PDT 24
Peak memory 198120 kb
Host smart-4cb376fb-39de-41b6-9f97-b0d732b20b2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294481563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2294481563
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2950104002
Short name T514
Test name
Test status
Simulation time 15511986 ps
CPU time 0.6 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:01 PM PDT 24
Peak memory 194096 kb
Host smart-0fb87947-46de-49a4-8b24-2016f8bf42b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950104002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2950104002
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2303771286
Short name T246
Test name
Test status
Simulation time 47803019 ps
CPU time 0.86 seconds
Started Mar 19 02:40:53 PM PDT 24
Finished Mar 19 02:40:54 PM PDT 24
Peak memory 196352 kb
Host smart-31d91f9d-b66a-4b81-b502-d9204ff5d189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303771286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2303771286
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1181005789
Short name T239
Test name
Test status
Simulation time 1969814528 ps
CPU time 23.63 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:25 PM PDT 24
Peak memory 195472 kb
Host smart-6d40cb2a-3ba8-447b-bbdf-16bbb54ede82
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181005789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1181005789
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3292528253
Short name T301
Test name
Test status
Simulation time 31916200 ps
CPU time 0.73 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:02 PM PDT 24
Peak memory 195312 kb
Host smart-bbdd9093-3359-4a37-8546-1debe59890ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292528253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3292528253
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.4123547770
Short name T105
Test name
Test status
Simulation time 233460498 ps
CPU time 1.31 seconds
Started Mar 19 02:41:00 PM PDT 24
Finished Mar 19 02:41:02 PM PDT 24
Peak memory 198068 kb
Host smart-baf839b2-26ba-45ba-a18d-114b73ab6914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123547770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.4123547770
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2245196890
Short name T365
Test name
Test status
Simulation time 45514154 ps
CPU time 1.9 seconds
Started Mar 19 02:40:56 PM PDT 24
Finished Mar 19 02:40:58 PM PDT 24
Peak memory 198096 kb
Host smart-0d9878b0-d74d-432b-b7d1-012f63613497
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245196890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2245196890
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.814349055
Short name T320
Test name
Test status
Simulation time 1632323947 ps
CPU time 2.86 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:04 PM PDT 24
Peak memory 198028 kb
Host smart-29e9b53c-4db3-42ee-8fb2-4c6a27a0d7de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814349055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
814349055
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.944366026
Short name T403
Test name
Test status
Simulation time 470143503 ps
CPU time 1.1 seconds
Started Mar 19 02:40:54 PM PDT 24
Finished Mar 19 02:40:55 PM PDT 24
Peak memory 196020 kb
Host smart-daa95863-ad18-42c2-a78d-bdebafcdcef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944366026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.944366026
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3303931696
Short name T298
Test name
Test status
Simulation time 27075031 ps
CPU time 1.09 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 195956 kb
Host smart-72af9580-5fcb-49ea-a190-a0eb9dc6818e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303931696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3303931696
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1141423220
Short name T526
Test name
Test status
Simulation time 792856625 ps
CPU time 1.79 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 197936 kb
Host smart-9da46697-7478-4eed-9498-bf20c354d301
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141423220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1141423220
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3140522858
Short name T291
Test name
Test status
Simulation time 172937386 ps
CPU time 1.37 seconds
Started Mar 19 02:40:53 PM PDT 24
Finished Mar 19 02:40:54 PM PDT 24
Peak memory 196596 kb
Host smart-03d3dfde-81ba-4706-94ee-bbe29dddb757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140522858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3140522858
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2513058631
Short name T204
Test name
Test status
Simulation time 166540181 ps
CPU time 0.91 seconds
Started Mar 19 02:40:54 PM PDT 24
Finished Mar 19 02:40:55 PM PDT 24
Peak memory 196456 kb
Host smart-6249921d-549e-4e53-8cbe-34d0763e6bef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513058631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2513058631
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2585398892
Short name T5
Test name
Test status
Simulation time 32237015829 ps
CPU time 185.24 seconds
Started Mar 19 02:40:55 PM PDT 24
Finished Mar 19 02:44:00 PM PDT 24
Peak memory 198200 kb
Host smart-8bf190bd-a531-4b80-9702-f4804d2da083
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585398892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2585398892
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3044633785
Short name T555
Test name
Test status
Simulation time 20281450 ps
CPU time 0.6 seconds
Started Mar 19 02:39:39 PM PDT 24
Finished Mar 19 02:39:40 PM PDT 24
Peak memory 194108 kb
Host smart-fb1f0991-5398-4225-9608-99959ac4e14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044633785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3044633785
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1811734202
Short name T328
Test name
Test status
Simulation time 52614491 ps
CPU time 0.6 seconds
Started Mar 19 02:39:36 PM PDT 24
Finished Mar 19 02:39:36 PM PDT 24
Peak memory 193956 kb
Host smart-abf31ef3-7223-4e54-9bdb-15109b9f4414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811734202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1811734202
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3308438919
Short name T408
Test name
Test status
Simulation time 556747541 ps
CPU time 12.64 seconds
Started Mar 19 02:39:38 PM PDT 24
Finished Mar 19 02:39:51 PM PDT 24
Peak memory 196540 kb
Host smart-56ed3993-257f-45d3-9c2e-ba2dcef3294c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308438919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3308438919
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.812162913
Short name T611
Test name
Test status
Simulation time 51026044 ps
CPU time 0.86 seconds
Started Mar 19 02:39:38 PM PDT 24
Finished Mar 19 02:39:39 PM PDT 24
Peak memory 196708 kb
Host smart-64e7b66e-462e-43c4-b8d2-e6c19797587b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812162913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.812162913
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1086655529
Short name T351
Test name
Test status
Simulation time 86415354 ps
CPU time 0.95 seconds
Started Mar 19 02:39:39 PM PDT 24
Finished Mar 19 02:39:40 PM PDT 24
Peak memory 197508 kb
Host smart-dc83835b-2653-4c6a-924f-076ce7abf8c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086655529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1086655529
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.82866752
Short name T340
Test name
Test status
Simulation time 39081007 ps
CPU time 1.79 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:42 PM PDT 24
Peak memory 196728 kb
Host smart-07390b71-4ff6-4a70-b848-9b3f64e6ce86
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82866752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.gpio_intr_with_filter_rand_intr_event.82866752
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1034783478
Short name T569
Test name
Test status
Simulation time 345112247 ps
CPU time 2.33 seconds
Started Mar 19 02:39:35 PM PDT 24
Finished Mar 19 02:39:38 PM PDT 24
Peak memory 197992 kb
Host smart-bb812f02-adf8-4b04-9b73-c6b3ca114449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034783478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1034783478
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3883991361
Short name T585
Test name
Test status
Simulation time 247775469 ps
CPU time 1.35 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:41 PM PDT 24
Peak memory 196800 kb
Host smart-97f37fad-eaef-4559-b113-a6f08c4a58e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883991361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3883991361
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2406195688
Short name T344
Test name
Test status
Simulation time 42235888 ps
CPU time 0.92 seconds
Started Mar 19 02:39:42 PM PDT 24
Finished Mar 19 02:39:43 PM PDT 24
Peak memory 195952 kb
Host smart-da15ecd6-470b-4ab1-9c3a-eee84f8a08e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406195688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2406195688
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2682412158
Short name T561
Test name
Test status
Simulation time 1106258162 ps
CPU time 4.34 seconds
Started Mar 19 02:39:42 PM PDT 24
Finished Mar 19 02:39:47 PM PDT 24
Peak memory 197992 kb
Host smart-1093bfe5-0a70-4fe9-98e8-e566d26560e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682412158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2682412158
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2057799591
Short name T48
Test name
Test status
Simulation time 164677167 ps
CPU time 1.01 seconds
Started Mar 19 02:39:35 PM PDT 24
Finished Mar 19 02:39:36 PM PDT 24
Peak memory 214936 kb
Host smart-ada34a4a-98b1-4cbe-a566-02991fedfb7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057799591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2057799591
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2872827522
Short name T609
Test name
Test status
Simulation time 159386494 ps
CPU time 1.33 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:41 PM PDT 24
Peak memory 195856 kb
Host smart-6562eeb0-fb28-49c4-9a06-fdf2fe5ca56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872827522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2872827522
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.84940331
Short name T382
Test name
Test status
Simulation time 84201253 ps
CPU time 1.43 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:42 PM PDT 24
Peak memory 196604 kb
Host smart-ce76105e-ace7-48be-9ce6-4390105a135d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84940331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.84940331
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.821205805
Short name T486
Test name
Test status
Simulation time 5680619747 ps
CPU time 86.73 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:41:07 PM PDT 24
Peak memory 198216 kb
Host smart-7d360ca7-67f7-44e8-9c41-924bc86d86fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821205805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.821205805
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2673035331
Short name T576
Test name
Test status
Simulation time 58436634488 ps
CPU time 1107.01 seconds
Started Mar 19 02:39:36 PM PDT 24
Finished Mar 19 02:58:03 PM PDT 24
Peak memory 198304 kb
Host smart-6e3ef931-fb23-4370-a95d-6677fcafb7bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2673035331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2673035331
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1335711396
Short name T39
Test name
Test status
Simulation time 61767870 ps
CPU time 0.59 seconds
Started Mar 19 02:40:57 PM PDT 24
Finished Mar 19 02:40:58 PM PDT 24
Peak memory 195664 kb
Host smart-6f282a77-5da9-42ea-88e9-04950d55206a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335711396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1335711396
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3517399199
Short name T350
Test name
Test status
Simulation time 133253412 ps
CPU time 0.78 seconds
Started Mar 19 02:40:52 PM PDT 24
Finished Mar 19 02:40:53 PM PDT 24
Peak memory 195380 kb
Host smart-1d1dfc61-6c53-43c7-9067-5f82f0af637b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517399199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3517399199
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2446856300
Short name T450
Test name
Test status
Simulation time 3588606614 ps
CPU time 14.95 seconds
Started Mar 19 02:40:55 PM PDT 24
Finished Mar 19 02:41:10 PM PDT 24
Peak memory 197320 kb
Host smart-250272ed-b0f5-4d94-9814-d65c84d55da3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446856300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2446856300
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3910723681
Short name T165
Test name
Test status
Simulation time 280360661 ps
CPU time 0.66 seconds
Started Mar 19 02:40:56 PM PDT 24
Finished Mar 19 02:40:57 PM PDT 24
Peak memory 195316 kb
Host smart-9e766900-d75c-490e-a297-ffe58339cdf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910723681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3910723681
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1336255689
Short name T200
Test name
Test status
Simulation time 25019519 ps
CPU time 0.78 seconds
Started Mar 19 02:40:53 PM PDT 24
Finished Mar 19 02:40:54 PM PDT 24
Peak memory 195620 kb
Host smart-4eeaffbe-2792-4bbd-a15e-ac5d55136bb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336255689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1336255689
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2826695597
Short name T501
Test name
Test status
Simulation time 615004899 ps
CPU time 3.59 seconds
Started Mar 19 02:40:55 PM PDT 24
Finished Mar 19 02:40:59 PM PDT 24
Peak memory 198016 kb
Host smart-0b853431-5966-4fbb-83ed-3203178cb5a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826695597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2826695597
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1483335628
Short name T367
Test name
Test status
Simulation time 26366450 ps
CPU time 0.94 seconds
Started Mar 19 02:40:55 PM PDT 24
Finished Mar 19 02:40:56 PM PDT 24
Peak memory 195572 kb
Host smart-ecf01c74-6a19-44e5-86d7-55805108ac11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483335628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1483335628
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2612734205
Short name T614
Test name
Test status
Simulation time 117682930 ps
CPU time 1.21 seconds
Started Mar 19 02:40:52 PM PDT 24
Finished Mar 19 02:40:53 PM PDT 24
Peak memory 196552 kb
Host smart-0d5fa08e-3c16-4786-be42-ef3992bc3e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612734205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2612734205
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.894024617
Short name T691
Test name
Test status
Simulation time 77972398 ps
CPU time 1.1 seconds
Started Mar 19 02:40:54 PM PDT 24
Finished Mar 19 02:40:56 PM PDT 24
Peak memory 196856 kb
Host smart-0128a87d-10e6-4c3d-9dc1-81de78392093
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894024617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.894024617
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2712205566
Short name T51
Test name
Test status
Simulation time 2742916162 ps
CPU time 6.46 seconds
Started Mar 19 02:40:55 PM PDT 24
Finished Mar 19 02:41:02 PM PDT 24
Peak memory 198128 kb
Host smart-d322d004-1903-409a-bba5-b8af8da6d8b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712205566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2712205566
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.479843499
Short name T380
Test name
Test status
Simulation time 45917301 ps
CPU time 1.4 seconds
Started Mar 19 02:40:55 PM PDT 24
Finished Mar 19 02:40:57 PM PDT 24
Peak memory 196204 kb
Host smart-4ea777f2-9d97-4a4e-b214-61d67e2c7f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479843499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.479843499
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2235824474
Short name T662
Test name
Test status
Simulation time 83412099 ps
CPU time 1.31 seconds
Started Mar 19 02:40:55 PM PDT 24
Finished Mar 19 02:40:56 PM PDT 24
Peak memory 195496 kb
Host smart-f0a2c98f-ec08-42a7-a4f2-afa7e758b122
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235824474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2235824474
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2219181648
Short name T384
Test name
Test status
Simulation time 19319390984 ps
CPU time 139.68 seconds
Started Mar 19 02:40:58 PM PDT 24
Finished Mar 19 02:43:18 PM PDT 24
Peak memory 198180 kb
Host smart-c95f4658-85b3-4dc2-a5fd-ddf539af97b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219181648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2219181648
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2941636899
Short name T305
Test name
Test status
Simulation time 40037938 ps
CPU time 0.6 seconds
Started Mar 19 02:41:02 PM PDT 24
Finished Mar 19 02:41:02 PM PDT 24
Peak memory 193912 kb
Host smart-fdc71954-f2cb-49bc-b888-5c7279cbb40b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941636899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2941636899
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2625098450
Short name T321
Test name
Test status
Simulation time 31675394 ps
CPU time 0.96 seconds
Started Mar 19 02:41:02 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 195796 kb
Host smart-19803f40-19b3-4617-81d1-ce80fedf04cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625098450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2625098450
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2700515138
Short name T646
Test name
Test status
Simulation time 473814619 ps
CPU time 13.32 seconds
Started Mar 19 02:40:56 PM PDT 24
Finished Mar 19 02:41:10 PM PDT 24
Peak memory 195504 kb
Host smart-20472d4a-4ce7-4bf4-ae76-32892429b102
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700515138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2700515138
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1160297440
Short name T452
Test name
Test status
Simulation time 159356456 ps
CPU time 0.94 seconds
Started Mar 19 02:40:58 PM PDT 24
Finished Mar 19 02:40:59 PM PDT 24
Peak memory 196228 kb
Host smart-bf1750da-c059-4759-9d3e-8a9c68689c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160297440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1160297440
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1701838119
Short name T247
Test name
Test status
Simulation time 183915367 ps
CPU time 0.94 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:02 PM PDT 24
Peak memory 195480 kb
Host smart-216d8e06-3636-439b-80e2-4a6e076cdd95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701838119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1701838119
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1253151397
Short name T251
Test name
Test status
Simulation time 79088077 ps
CPU time 0.96 seconds
Started Mar 19 02:40:55 PM PDT 24
Finished Mar 19 02:40:56 PM PDT 24
Peak memory 196188 kb
Host smart-257f0480-ceee-4cdd-b874-8a89a681ac34
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253151397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1253151397
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1867168736
Short name T296
Test name
Test status
Simulation time 1813103712 ps
CPU time 3.27 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:05 PM PDT 24
Peak memory 196748 kb
Host smart-4e1a20fd-6d6f-42d7-8e4b-ce38a28c2f6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867168736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1867168736
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.61806003
Short name T424
Test name
Test status
Simulation time 30106709 ps
CPU time 1.24 seconds
Started Mar 19 02:40:53 PM PDT 24
Finished Mar 19 02:40:54 PM PDT 24
Peak memory 196048 kb
Host smart-58737d25-cf02-4bfb-b6d5-650ac5a2a68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61806003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.61806003
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2612635900
Short name T359
Test name
Test status
Simulation time 139744151 ps
CPU time 1.02 seconds
Started Mar 19 02:40:53 PM PDT 24
Finished Mar 19 02:40:54 PM PDT 24
Peak memory 195916 kb
Host smart-8468fcb2-c8b0-43e0-b1b1-a565d9524a3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612635900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2612635900
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3388765201
Short name T521
Test name
Test status
Simulation time 99471250 ps
CPU time 4.59 seconds
Started Mar 19 02:40:57 PM PDT 24
Finished Mar 19 02:41:01 PM PDT 24
Peak memory 197940 kb
Host smart-d590b0f2-615f-48c0-9b6a-bdde75625225
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388765201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3388765201
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1946085027
Short name T535
Test name
Test status
Simulation time 38161883 ps
CPU time 1.08 seconds
Started Mar 19 02:40:53 PM PDT 24
Finished Mar 19 02:40:54 PM PDT 24
Peak memory 195760 kb
Host smart-3c084f70-8db3-4df8-b1af-199e81fed599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946085027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1946085027
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.333880012
Short name T148
Test name
Test status
Simulation time 194211125 ps
CPU time 1.41 seconds
Started Mar 19 02:40:55 PM PDT 24
Finished Mar 19 02:40:57 PM PDT 24
Peak memory 198220 kb
Host smart-b84e7f1d-8053-49da-85ee-621df8950a55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333880012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.333880012
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1067358461
Short name T698
Test name
Test status
Simulation time 10477033940 ps
CPU time 147.98 seconds
Started Mar 19 02:41:03 PM PDT 24
Finished Mar 19 02:43:31 PM PDT 24
Peak memory 198212 kb
Host smart-b13f3f8d-02fb-42aa-838c-3cf283426121
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067358461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1067358461
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1455085863
Short name T362
Test name
Test status
Simulation time 13901519 ps
CPU time 0.59 seconds
Started Mar 19 02:41:02 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 194640 kb
Host smart-a4828eeb-6b5b-474f-90c9-66663cc19d18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455085863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1455085863
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2818059412
Short name T590
Test name
Test status
Simulation time 321071607 ps
CPU time 0.78 seconds
Started Mar 19 02:41:02 PM PDT 24
Finished Mar 19 02:41:02 PM PDT 24
Peak memory 196016 kb
Host smart-cbcb1664-86f8-4c2d-a337-ce3883502dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818059412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2818059412
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.4253999238
Short name T245
Test name
Test status
Simulation time 415488402 ps
CPU time 8.88 seconds
Started Mar 19 02:41:04 PM PDT 24
Finished Mar 19 02:41:13 PM PDT 24
Peak memory 196504 kb
Host smart-5e423203-9ab1-4f1b-a376-408d02e1127a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253999238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.4253999238
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3848556206
Short name T402
Test name
Test status
Simulation time 68374391 ps
CPU time 0.89 seconds
Started Mar 19 02:41:07 PM PDT 24
Finished Mar 19 02:41:08 PM PDT 24
Peak memory 196184 kb
Host smart-17e788be-c0f1-4845-885d-836d6f1c7544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848556206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3848556206
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2878217167
Short name T338
Test name
Test status
Simulation time 36285794 ps
CPU time 0.79 seconds
Started Mar 19 02:41:03 PM PDT 24
Finished Mar 19 02:41:04 PM PDT 24
Peak memory 195464 kb
Host smart-a1200362-ca7d-4c0b-b57c-d2425378b35e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878217167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2878217167
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.4290108016
Short name T263
Test name
Test status
Simulation time 144843077 ps
CPU time 3.15 seconds
Started Mar 19 02:41:03 PM PDT 24
Finished Mar 19 02:41:06 PM PDT 24
Peak memory 198036 kb
Host smart-e7b50431-866e-47b8-946f-389932133e76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290108016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.4290108016
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2647799386
Short name T538
Test name
Test status
Simulation time 580250548 ps
CPU time 2.99 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:05 PM PDT 24
Peak memory 195780 kb
Host smart-37ea22fc-7dfe-41f7-9ff4-acd2a6fd538b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647799386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2647799386
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2386082156
Short name T650
Test name
Test status
Simulation time 93361342 ps
CPU time 0.76 seconds
Started Mar 19 02:41:03 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 195340 kb
Host smart-743c9c49-6471-4732-b0ed-67f2da3d5a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386082156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2386082156
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3258498336
Short name T597
Test name
Test status
Simulation time 97407193 ps
CPU time 0.93 seconds
Started Mar 19 02:41:02 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 195564 kb
Host smart-fc749199-fd1d-4fe8-a50d-f67be33285d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258498336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3258498336
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.214073884
Short name T256
Test name
Test status
Simulation time 161829449 ps
CPU time 3.17 seconds
Started Mar 19 02:41:05 PM PDT 24
Finished Mar 19 02:41:08 PM PDT 24
Peak memory 197924 kb
Host smart-9f076f7b-e37a-45e1-a12b-f84258f81022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214073884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.214073884
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3953120162
Short name T163
Test name
Test status
Simulation time 91723873 ps
CPU time 1.36 seconds
Started Mar 19 02:41:07 PM PDT 24
Finished Mar 19 02:41:08 PM PDT 24
Peak memory 196636 kb
Host smart-77f92ed5-9b94-4f4e-b006-b5435a57e765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953120162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3953120162
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2184449404
Short name T372
Test name
Test status
Simulation time 73269976 ps
CPU time 1.48 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 198020 kb
Host smart-46cfdbc1-4d8a-4c99-9aa4-72d6e3ac635a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184449404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2184449404
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.305187311
Short name T459
Test name
Test status
Simulation time 1336582217 ps
CPU time 36.15 seconds
Started Mar 19 02:41:07 PM PDT 24
Finished Mar 19 02:41:43 PM PDT 24
Peak memory 197996 kb
Host smart-e87b092e-43a7-4bdf-9850-f05ca95d3526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305187311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.305187311
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2646155107
Short name T65
Test name
Test status
Simulation time 80829774827 ps
CPU time 1034.86 seconds
Started Mar 19 02:41:02 PM PDT 24
Finished Mar 19 02:58:17 PM PDT 24
Peak memory 198304 kb
Host smart-dc10ad40-29af-43b2-94dd-02744519d6a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2646155107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2646155107
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1581033346
Short name T518
Test name
Test status
Simulation time 19923788 ps
CPU time 0.61 seconds
Started Mar 19 02:41:13 PM PDT 24
Finished Mar 19 02:41:14 PM PDT 24
Peak memory 194608 kb
Host smart-45bc3940-1a9b-4dc1-9ff4-854d953a3857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581033346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1581033346
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3959512051
Short name T502
Test name
Test status
Simulation time 33084345 ps
CPU time 0.88 seconds
Started Mar 19 02:41:02 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 195352 kb
Host smart-4b000cd6-ec07-4fc5-b570-0b1bf2ee5928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959512051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3959512051
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1849511266
Short name T519
Test name
Test status
Simulation time 1491334666 ps
CPU time 24.72 seconds
Started Mar 19 02:41:12 PM PDT 24
Finished Mar 19 02:41:37 PM PDT 24
Peak memory 195484 kb
Host smart-b3721f7b-8576-4af2-82d9-5ff31fefdd47
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849511266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1849511266
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1330097747
Short name T370
Test name
Test status
Simulation time 290425979 ps
CPU time 1.08 seconds
Started Mar 19 02:41:15 PM PDT 24
Finished Mar 19 02:41:16 PM PDT 24
Peak memory 196588 kb
Host smart-264b58ec-a507-400f-9356-a9f7450017f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330097747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1330097747
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.245834911
Short name T334
Test name
Test status
Simulation time 41741080 ps
CPU time 1.16 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 196096 kb
Host smart-2490616a-3193-473d-a45e-aca8fb3cac04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245834911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.245834911
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.4050333650
Short name T651
Test name
Test status
Simulation time 73142755 ps
CPU time 2.98 seconds
Started Mar 19 02:41:07 PM PDT 24
Finished Mar 19 02:41:10 PM PDT 24
Peak memory 197944 kb
Host smart-d07be65b-d3e5-493c-bc8e-1d2be234947e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050333650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.4050333650
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3113545543
Short name T411
Test name
Test status
Simulation time 118280265 ps
CPU time 1.95 seconds
Started Mar 19 02:41:01 PM PDT 24
Finished Mar 19 02:41:04 PM PDT 24
Peak memory 196224 kb
Host smart-4f524c1d-5a1f-4e7b-9c49-8abff9281067
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113545543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3113545543
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3769061969
Short name T53
Test name
Test status
Simulation time 227012917 ps
CPU time 1.13 seconds
Started Mar 19 02:41:02 PM PDT 24
Finished Mar 19 02:41:03 PM PDT 24
Peak memory 195720 kb
Host smart-8591dd71-4d15-436f-ade8-030c84e8d881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769061969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3769061969
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3176901306
Short name T391
Test name
Test status
Simulation time 58652247 ps
CPU time 0.99 seconds
Started Mar 19 02:41:07 PM PDT 24
Finished Mar 19 02:41:08 PM PDT 24
Peak memory 195776 kb
Host smart-35af92a6-1f3c-416d-93fa-ab6b7de3616d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176901306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3176901306
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1045066734
Short name T119
Test name
Test status
Simulation time 44379538 ps
CPU time 1.98 seconds
Started Mar 19 02:41:13 PM PDT 24
Finished Mar 19 02:41:15 PM PDT 24
Peak memory 197904 kb
Host smart-571b8a3c-def0-49a1-a084-3bb97f157db7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045066734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1045066734
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1772540869
Short name T386
Test name
Test status
Simulation time 172035029 ps
CPU time 0.93 seconds
Started Mar 19 02:41:03 PM PDT 24
Finished Mar 19 02:41:04 PM PDT 24
Peak memory 196480 kb
Host smart-99280ee2-dca1-462f-81bd-014d68b5da67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772540869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1772540869
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1338505148
Short name T218
Test name
Test status
Simulation time 86471711 ps
CPU time 1.33 seconds
Started Mar 19 02:41:04 PM PDT 24
Finished Mar 19 02:41:06 PM PDT 24
Peak memory 197936 kb
Host smart-8f8eea04-e31d-4070-bfcb-56c3d1c3472d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338505148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1338505148
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.4150440777
Short name T628
Test name
Test status
Simulation time 26832430386 ps
CPU time 95.55 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:42:49 PM PDT 24
Peak memory 198172 kb
Host smart-9af413b7-94cc-4d9b-b314-16fe97c4ddff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150440777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.4150440777
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3140529661
Short name T294
Test name
Test status
Simulation time 10814571 ps
CPU time 0.58 seconds
Started Mar 19 02:41:12 PM PDT 24
Finished Mar 19 02:41:13 PM PDT 24
Peak memory 194648 kb
Host smart-12207b1b-d80d-4233-b2d2-301f59b56ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140529661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3140529661
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3959972679
Short name T407
Test name
Test status
Simulation time 60391561 ps
CPU time 0.62 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:41:15 PM PDT 24
Peak memory 194672 kb
Host smart-e644310d-2545-45d3-a19b-07a0cb44abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959972679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3959972679
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3759379321
Short name T11
Test name
Test status
Simulation time 414786618 ps
CPU time 21.08 seconds
Started Mar 19 02:41:12 PM PDT 24
Finished Mar 19 02:41:33 PM PDT 24
Peak memory 195536 kb
Host smart-506c60d1-a9af-432c-9cfb-c6b44ed4f8a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759379321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3759379321
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2109758777
Short name T656
Test name
Test status
Simulation time 84781699 ps
CPU time 1.1 seconds
Started Mar 19 02:41:12 PM PDT 24
Finished Mar 19 02:41:13 PM PDT 24
Peak memory 196688 kb
Host smart-ff6d2eb6-8551-4ab1-92de-69bb6bb0b066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109758777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2109758777
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1554676709
Short name T637
Test name
Test status
Simulation time 160416035 ps
CPU time 1.23 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:41:15 PM PDT 24
Peak memory 196132 kb
Host smart-24cd271e-f01d-4dcf-b58c-978bcb7be9c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554676709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1554676709
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.4189323532
Short name T548
Test name
Test status
Simulation time 31295491 ps
CPU time 1.24 seconds
Started Mar 19 02:41:12 PM PDT 24
Finished Mar 19 02:41:14 PM PDT 24
Peak memory 196548 kb
Host smart-bd22a013-fbbd-40ad-8e9f-c35fab59ff90
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189323532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.4189323532
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2035095238
Short name T58
Test name
Test status
Simulation time 265184136 ps
CPU time 3.19 seconds
Started Mar 19 02:41:15 PM PDT 24
Finished Mar 19 02:41:18 PM PDT 24
Peak memory 195776 kb
Host smart-4198d93b-6be6-4489-ac75-f8108496479c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035095238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2035095238
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2585765777
Short name T345
Test name
Test status
Simulation time 163332601 ps
CPU time 0.85 seconds
Started Mar 19 02:41:13 PM PDT 24
Finished Mar 19 02:41:14 PM PDT 24
Peak memory 197356 kb
Host smart-f4e17785-0531-4c78-90fe-e721c5853808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585765777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2585765777
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3886702914
Short name T634
Test name
Test status
Simulation time 74379740 ps
CPU time 1.1 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:41:15 PM PDT 24
Peak memory 196700 kb
Host smart-dd90b907-2462-40eb-b3b9-c46afb7d0d0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886702914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3886702914
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3072533843
Short name T322
Test name
Test status
Simulation time 130866518 ps
CPU time 3.45 seconds
Started Mar 19 02:41:11 PM PDT 24
Finished Mar 19 02:41:15 PM PDT 24
Peak memory 197940 kb
Host smart-a568143f-1d84-4553-9e9b-e267ff16b0da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072533843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3072533843
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.363384897
Short name T221
Test name
Test status
Simulation time 101629755 ps
CPU time 0.95 seconds
Started Mar 19 02:41:12 PM PDT 24
Finished Mar 19 02:41:13 PM PDT 24
Peak memory 196984 kb
Host smart-261cce6c-9eaf-40a0-b2ff-f741ec1d00a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363384897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.363384897
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3742815314
Short name T212
Test name
Test status
Simulation time 134832877 ps
CPU time 1 seconds
Started Mar 19 02:41:13 PM PDT 24
Finished Mar 19 02:41:14 PM PDT 24
Peak memory 195776 kb
Host smart-2a7d17e8-0e78-4630-a49c-2588a166e37f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742815314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3742815314
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1665783948
Short name T392
Test name
Test status
Simulation time 64181577799 ps
CPU time 143.07 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:43:37 PM PDT 24
Peak memory 198216 kb
Host smart-0dd23972-9450-42c5-9f27-41c63895a6b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665783948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1665783948
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.4217707359
Short name T629
Test name
Test status
Simulation time 76060078018 ps
CPU time 2094.15 seconds
Started Mar 19 02:41:13 PM PDT 24
Finished Mar 19 03:16:08 PM PDT 24
Peak memory 198292 kb
Host smart-8c168f35-c257-4ca4-bb99-fd046d3c1474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4217707359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.4217707359
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.626900576
Short name T222
Test name
Test status
Simulation time 13612401 ps
CPU time 0.61 seconds
Started Mar 19 02:41:15 PM PDT 24
Finished Mar 19 02:41:15 PM PDT 24
Peak memory 193892 kb
Host smart-796c9502-bd39-48dc-98af-dae33f3bb8a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626900576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.626900576
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1978700654
Short name T337
Test name
Test status
Simulation time 77579276 ps
CPU time 0.77 seconds
Started Mar 19 02:41:16 PM PDT 24
Finished Mar 19 02:41:17 PM PDT 24
Peak memory 195256 kb
Host smart-97c7bd8f-7fc9-4594-abaa-ec6e4f557607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978700654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1978700654
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2289818373
Short name T613
Test name
Test status
Simulation time 538728749 ps
CPU time 28.62 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:41:43 PM PDT 24
Peak memory 197116 kb
Host smart-d5098c46-c005-4622-8132-8b41202653cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289818373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2289818373
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2053312794
Short name T507
Test name
Test status
Simulation time 23011698 ps
CPU time 0.64 seconds
Started Mar 19 02:41:15 PM PDT 24
Finished Mar 19 02:41:15 PM PDT 24
Peak memory 195164 kb
Host smart-99e940ee-38b9-498e-9bed-d3c09858b264
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053312794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2053312794
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3533553860
Short name T539
Test name
Test status
Simulation time 37854578 ps
CPU time 0.86 seconds
Started Mar 19 02:41:16 PM PDT 24
Finished Mar 19 02:41:17 PM PDT 24
Peak memory 195468 kb
Host smart-88de09df-1812-4f1a-8e65-36c616bbafc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533553860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3533553860
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.4118318949
Short name T293
Test name
Test status
Simulation time 71831995 ps
CPU time 1.08 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:41:15 PM PDT 24
Peak memory 196952 kb
Host smart-b8043cfd-36d3-4b52-b9d5-08a375769fce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118318949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.4118318949
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2159798051
Short name T207
Test name
Test status
Simulation time 286441437 ps
CPU time 2.24 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:41:16 PM PDT 24
Peak memory 197956 kb
Host smart-968bd53c-ee88-48dd-86c3-e052e6825849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159798051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2159798051
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.747815450
Short name T215
Test name
Test status
Simulation time 78820561 ps
CPU time 0.91 seconds
Started Mar 19 02:41:12 PM PDT 24
Finished Mar 19 02:41:13 PM PDT 24
Peak memory 195784 kb
Host smart-02bc0568-459a-453e-a00d-4dad490e9fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747815450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.747815450
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.464372499
Short name T192
Test name
Test status
Simulation time 63507265 ps
CPU time 1.21 seconds
Started Mar 19 02:41:14 PM PDT 24
Finished Mar 19 02:41:15 PM PDT 24
Peak memory 198020 kb
Host smart-52505d39-7322-4700-a2c0-a820464026cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464372499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.464372499
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.293085292
Short name T118
Test name
Test status
Simulation time 346936395 ps
CPU time 2.4 seconds
Started Mar 19 02:41:16 PM PDT 24
Finished Mar 19 02:41:19 PM PDT 24
Peak memory 197912 kb
Host smart-07451458-951f-42ea-b7eb-e33ea405ca85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293085292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.293085292
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1019425826
Short name T575
Test name
Test status
Simulation time 162314713 ps
CPU time 1.55 seconds
Started Mar 19 02:41:12 PM PDT 24
Finished Mar 19 02:41:14 PM PDT 24
Peak memory 196788 kb
Host smart-62676ddd-7608-46d8-90a9-81e54674f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019425826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1019425826
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1175953199
Short name T580
Test name
Test status
Simulation time 123285017 ps
CPU time 0.78 seconds
Started Mar 19 02:41:13 PM PDT 24
Finished Mar 19 02:41:14 PM PDT 24
Peak memory 195976 kb
Host smart-c4deebdb-1a4a-4219-a295-881434d53e6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175953199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1175953199
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2014066272
Short name T167
Test name
Test status
Simulation time 24306861 ps
CPU time 0.6 seconds
Started Mar 19 02:41:28 PM PDT 24
Finished Mar 19 02:41:28 PM PDT 24
Peak memory 194120 kb
Host smart-ac1d1a30-1e8c-4df3-bcbf-22e1594aedee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014066272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2014066272
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1911861688
Short name T242
Test name
Test status
Simulation time 34121278 ps
CPU time 0.8 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 195344 kb
Host smart-bf2b5d3a-2c43-4de8-9478-781565d3aa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911861688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1911861688
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2569594308
Short name T416
Test name
Test status
Simulation time 3119299008 ps
CPU time 17.23 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:38 PM PDT 24
Peak memory 196928 kb
Host smart-5981dda7-b15b-44b3-a98a-ef532128a490
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569594308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2569594308
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3851573601
Short name T289
Test name
Test status
Simulation time 171509891 ps
CPU time 0.84 seconds
Started Mar 19 02:41:23 PM PDT 24
Finished Mar 19 02:41:24 PM PDT 24
Peak memory 195948 kb
Host smart-303341f2-c2da-49a8-8588-8c04e21aed92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851573601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3851573601
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3296779259
Short name T603
Test name
Test status
Simulation time 146956821 ps
CPU time 1.2 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 195964 kb
Host smart-617ea23e-20fa-4483-85d1-10d6d221566d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296779259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3296779259
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3537095313
Short name T421
Test name
Test status
Simulation time 97292556 ps
CPU time 1.31 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 196484 kb
Host smart-8fa7da34-2533-49cd-86e8-0f85d7d4bc0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537095313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3537095313
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1735077800
Short name T680
Test name
Test status
Simulation time 178259856 ps
CPU time 1.12 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:41:24 PM PDT 24
Peak memory 196516 kb
Host smart-dc39c33a-67f1-4b4c-aa15-8fff1c8ad28f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735077800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1735077800
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2491595433
Short name T331
Test name
Test status
Simulation time 92370925 ps
CPU time 0.96 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:41:24 PM PDT 24
Peak memory 195988 kb
Host smart-c935e66b-6141-440b-a6a9-c12c34025fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491595433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2491595433
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1850872158
Short name T491
Test name
Test status
Simulation time 199071334 ps
CPU time 1.02 seconds
Started Mar 19 02:41:29 PM PDT 24
Finished Mar 19 02:41:30 PM PDT 24
Peak memory 196476 kb
Host smart-20134b39-8115-4263-9444-a1c318f322a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850872158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1850872158
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3329546397
Short name T7
Test name
Test status
Simulation time 582519728 ps
CPU time 3.92 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:41:34 PM PDT 24
Peak memory 197924 kb
Host smart-c00fe1a3-72ef-47ac-956c-65c63bc71a49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329546397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3329546397
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3137620159
Short name T235
Test name
Test status
Simulation time 69521657 ps
CPU time 1.28 seconds
Started Mar 19 02:41:20 PM PDT 24
Finished Mar 19 02:41:21 PM PDT 24
Peak memory 195648 kb
Host smart-abedf7ff-f016-464c-a8bc-e2dbe1c7daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137620159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3137620159
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3333871204
Short name T299
Test name
Test status
Simulation time 466863528 ps
CPU time 1.05 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:22 PM PDT 24
Peak memory 195616 kb
Host smart-aee34242-8e65-4211-b254-9c54e2fc5386
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333871204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3333871204
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.915647087
Short name T360
Test name
Test status
Simulation time 15029050558 ps
CPU time 49.84 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:42:12 PM PDT 24
Peak memory 198020 kb
Host smart-a40c6f93-716f-4992-be85-792934c6b322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915647087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.915647087
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1149038142
Short name T61
Test name
Test status
Simulation time 22306522235 ps
CPU time 536.35 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:50:18 PM PDT 24
Peak memory 198104 kb
Host smart-5f926577-8dcd-48fb-89e2-78e3a8e5fa38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1149038142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1149038142
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.560914164
Short name T203
Test name
Test status
Simulation time 36417962 ps
CPU time 0.56 seconds
Started Mar 19 02:41:23 PM PDT 24
Finished Mar 19 02:41:24 PM PDT 24
Peak memory 193912 kb
Host smart-3eaa3ea1-c4de-40bd-977e-0c475e5054a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560914164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.560914164
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.883138794
Short name T510
Test name
Test status
Simulation time 83149544 ps
CPU time 0.78 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 195384 kb
Host smart-9ab3c8cc-0e08-436a-b7fa-220db9855f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883138794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.883138794
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1530978895
Short name T310
Test name
Test status
Simulation time 669309419 ps
CPU time 16.77 seconds
Started Mar 19 02:41:27 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 196248 kb
Host smart-5512d3dc-2860-4d4e-9da2-a0666d659314
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530978895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1530978895
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3985830579
Short name T20
Test name
Test status
Simulation time 92893776 ps
CPU time 1.09 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:22 PM PDT 24
Peak memory 197748 kb
Host smart-9492ea40-ac6e-466f-8b74-62ab3bb33e0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985830579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3985830579
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1754073573
Short name T224
Test name
Test status
Simulation time 52253789 ps
CPU time 1.38 seconds
Started Mar 19 02:41:27 PM PDT 24
Finished Mar 19 02:41:29 PM PDT 24
Peak memory 196940 kb
Host smart-49b188d2-a519-4f61-b7d6-45e31a79ea0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754073573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1754073573
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2502740074
Short name T231
Test name
Test status
Simulation time 81810810 ps
CPU time 3.07 seconds
Started Mar 19 02:41:25 PM PDT 24
Finished Mar 19 02:41:29 PM PDT 24
Peak memory 197316 kb
Host smart-4d49c782-97ce-460e-b3bd-7045aa2c7779
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502740074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2502740074
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.806606979
Short name T430
Test name
Test status
Simulation time 113470441 ps
CPU time 1.83 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 196488 kb
Host smart-0e5adc72-d010-410c-b6f7-7d83fa8c4fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806606979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
806606979
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.805719379
Short name T317
Test name
Test status
Simulation time 31501979 ps
CPU time 0.83 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:21 PM PDT 24
Peak memory 195576 kb
Host smart-14613612-efb1-4d43-b298-90187b62d614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805719379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.805719379
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2089614090
Short name T352
Test name
Test status
Simulation time 133826209 ps
CPU time 1.19 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 198012 kb
Host smart-c5df8d3e-d0cb-4d28-a56c-87654a08d811
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089614090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2089614090
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3564145715
Short name T532
Test name
Test status
Simulation time 87907701 ps
CPU time 1.19 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:22 PM PDT 24
Peak memory 197976 kb
Host smart-3661d2a4-c9cc-4b6f-90e0-0c9ac7a9ae40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564145715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3564145715
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3643905277
Short name T616
Test name
Test status
Simulation time 126683428 ps
CPU time 1.32 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 195512 kb
Host smart-65159bdd-0990-4037-a454-faba042b26f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643905277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3643905277
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1417714843
Short name T504
Test name
Test status
Simulation time 47278993 ps
CPU time 1.35 seconds
Started Mar 19 02:41:26 PM PDT 24
Finished Mar 19 02:41:28 PM PDT 24
Peak memory 196728 kb
Host smart-67fc875b-2c0d-4f92-8f9c-4a4cb307f746
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417714843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1417714843
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2150842441
Short name T172
Test name
Test status
Simulation time 28579316377 ps
CPU time 73.37 seconds
Started Mar 19 02:41:27 PM PDT 24
Finished Mar 19 02:42:41 PM PDT 24
Peak memory 198156 kb
Host smart-26ed6ec1-37f5-4628-8e65-f7d36a046fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150842441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2150842441
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.156022172
Short name T500
Test name
Test status
Simulation time 19335020 ps
CPU time 0.56 seconds
Started Mar 19 02:41:27 PM PDT 24
Finished Mar 19 02:41:28 PM PDT 24
Peak memory 193916 kb
Host smart-90080a14-9c67-4cc9-a3e8-3ff4cacf5ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156022172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.156022172
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.812689158
Short name T146
Test name
Test status
Simulation time 34051595 ps
CPU time 0.93 seconds
Started Mar 19 02:41:28 PM PDT 24
Finished Mar 19 02:41:29 PM PDT 24
Peak memory 196132 kb
Host smart-d6800fd5-7797-43c9-8756-a02fdf60c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812689158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.812689158
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.497643332
Short name T358
Test name
Test status
Simulation time 1396827109 ps
CPU time 12.19 seconds
Started Mar 19 02:41:27 PM PDT 24
Finished Mar 19 02:41:40 PM PDT 24
Peak memory 197952 kb
Host smart-9f528eab-b145-49cd-aa24-cb9d62135651
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497643332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.497643332
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2984499492
Short name T672
Test name
Test status
Simulation time 88193654 ps
CPU time 1.08 seconds
Started Mar 19 02:41:26 PM PDT 24
Finished Mar 19 02:41:28 PM PDT 24
Peak memory 196412 kb
Host smart-54adbb90-5f0a-4d15-ae93-b63181b797d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984499492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2984499492
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2045351797
Short name T336
Test name
Test status
Simulation time 100989185 ps
CPU time 0.74 seconds
Started Mar 19 02:41:24 PM PDT 24
Finished Mar 19 02:41:25 PM PDT 24
Peak memory 194432 kb
Host smart-1dd2348d-0ef3-480b-9191-1b5aefd1ce21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045351797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2045351797
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2969067148
Short name T688
Test name
Test status
Simulation time 495365756 ps
CPU time 2.82 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:24 PM PDT 24
Peak memory 198020 kb
Host smart-cd06571d-7fcb-4dea-a677-25cf1de04a4c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969067148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2969067148
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.4279407503
Short name T542
Test name
Test status
Simulation time 76488125 ps
CPU time 2.36 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:24 PM PDT 24
Peak memory 197116 kb
Host smart-48cd50d5-e02e-4f85-a660-5af0e5d5095c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279407503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.4279407503
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2420781304
Short name T621
Test name
Test status
Simulation time 103710507 ps
CPU time 0.84 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 196456 kb
Host smart-e1e8fc4e-a26b-45e6-a240-09109a2d3d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420781304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2420781304
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1194040541
Short name T480
Test name
Test status
Simulation time 69362188 ps
CPU time 1.39 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 198000 kb
Host smart-81ae8b87-8773-438f-8d31-309bf941b667
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194040541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1194040541
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2513103832
Short name T123
Test name
Test status
Simulation time 140420087 ps
CPU time 5.93 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:27 PM PDT 24
Peak memory 198000 kb
Host smart-dd5e2338-3607-4b66-ab45-80915676c134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513103832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2513103832
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.639022459
Short name T383
Test name
Test status
Simulation time 227702929 ps
CPU time 1.47 seconds
Started Mar 19 02:41:21 PM PDT 24
Finished Mar 19 02:41:23 PM PDT 24
Peak memory 197964 kb
Host smart-e83915ba-c9b9-48be-ae50-e2aa9674cee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639022459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.639022459
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3456968740
Short name T227
Test name
Test status
Simulation time 32438021 ps
CPU time 0.78 seconds
Started Mar 19 02:41:29 PM PDT 24
Finished Mar 19 02:41:30 PM PDT 24
Peak memory 195100 kb
Host smart-266aa3c0-5d4c-418d-8e80-65a9e7ed7b14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456968740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3456968740
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1040861818
Short name T111
Test name
Test status
Simulation time 98392722862 ps
CPU time 133.03 seconds
Started Mar 19 02:41:22 PM PDT 24
Finished Mar 19 02:43:35 PM PDT 24
Peak memory 198140 kb
Host smart-814acef9-b3bd-494b-b1b7-8b1ed11bbe26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040861818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1040861818
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1617555846
Short name T330
Test name
Test status
Simulation time 103515078 ps
CPU time 0.59 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:41:31 PM PDT 24
Peak memory 194040 kb
Host smart-7c5e073a-5fdf-4a88-83e5-72936e0fb948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617555846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1617555846
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3474666510
Short name T531
Test name
Test status
Simulation time 141119408 ps
CPU time 0.92 seconds
Started Mar 19 02:41:28 PM PDT 24
Finished Mar 19 02:41:29 PM PDT 24
Peak memory 196192 kb
Host smart-4c9d00b7-0a9b-4d9f-bcab-0def06f0ebdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474666510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3474666510
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.177958146
Short name T270
Test name
Test status
Simulation time 515324994 ps
CPU time 19.69 seconds
Started Mar 19 02:41:29 PM PDT 24
Finished Mar 19 02:41:49 PM PDT 24
Peak memory 195468 kb
Host smart-4cb9f5ca-1092-46da-ad23-4283c01791ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177958146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.177958146
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1387972149
Short name T462
Test name
Test status
Simulation time 70979118 ps
CPU time 0.74 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:41:31 PM PDT 24
Peak memory 194680 kb
Host smart-74357237-d02f-4bae-955b-8c79076e4e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387972149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1387972149
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.990681884
Short name T130
Test name
Test status
Simulation time 33318160 ps
CPU time 1.1 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:32 PM PDT 24
Peak memory 196492 kb
Host smart-7ec0802e-2b2f-4101-8839-e5365cc16eba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990681884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.990681884
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3398212251
Short name T704
Test name
Test status
Simulation time 88756151 ps
CPU time 3.6 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:35 PM PDT 24
Peak memory 196316 kb
Host smart-30b4d42c-6874-43c1-8640-0539b29d9880
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398212251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3398212251
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2274113898
Short name T17
Test name
Test status
Simulation time 378241742 ps
CPU time 2.3 seconds
Started Mar 19 02:41:28 PM PDT 24
Finished Mar 19 02:41:30 PM PDT 24
Peak memory 196180 kb
Host smart-27f9805a-ad75-4ee4-9bc6-6271945bbe25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274113898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2274113898
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.309074485
Short name T568
Test name
Test status
Simulation time 95487851 ps
CPU time 1.06 seconds
Started Mar 19 02:41:28 PM PDT 24
Finished Mar 19 02:41:29 PM PDT 24
Peak memory 195940 kb
Host smart-dfb0cdcf-76c8-487a-92f9-703ea973b6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309074485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.309074485
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1396571915
Short name T659
Test name
Test status
Simulation time 108824082 ps
CPU time 1.05 seconds
Started Mar 19 02:41:20 PM PDT 24
Finished Mar 19 02:41:21 PM PDT 24
Peak memory 195936 kb
Host smart-89e3c23a-ef50-41fb-90aa-a62b3a46fe15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396571915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1396571915
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2876014139
Short name T404
Test name
Test status
Simulation time 2187233063 ps
CPU time 1.87 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:33 PM PDT 24
Peak memory 198036 kb
Host smart-f4857128-4cc0-437e-9847-cbdcc81a03e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876014139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2876014139
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4192170668
Short name T478
Test name
Test status
Simulation time 28020234 ps
CPU time 1.04 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:41:31 PM PDT 24
Peak memory 195672 kb
Host smart-0c79756e-31a3-40ee-8eab-193338cd997b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192170668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4192170668
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.730631209
Short name T183
Test name
Test status
Simulation time 56537216 ps
CPU time 1.5 seconds
Started Mar 19 02:41:27 PM PDT 24
Finished Mar 19 02:41:29 PM PDT 24
Peak memory 195476 kb
Host smart-8f664a35-7166-400e-928e-101d74d55d50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730631209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.730631209
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1202695589
Short name T505
Test name
Test status
Simulation time 47778814126 ps
CPU time 174.53 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:44:26 PM PDT 24
Peak memory 198176 kb
Host smart-cc4a787e-ff78-4b4a-b52d-95fbffc5c579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202695589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1202695589
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3192594913
Short name T286
Test name
Test status
Simulation time 33580697 ps
CPU time 0.57 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:37 PM PDT 24
Peak memory 193944 kb
Host smart-6a759093-409d-47e9-a257-6bba1544e04d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192594913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3192594913
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4127984728
Short name T701
Test name
Test status
Simulation time 98701621 ps
CPU time 0.77 seconds
Started Mar 19 02:39:36 PM PDT 24
Finished Mar 19 02:39:37 PM PDT 24
Peak memory 194240 kb
Host smart-8bf14d05-52df-44c1-8371-f57ac7ad447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127984728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4127984728
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1491197850
Short name T709
Test name
Test status
Simulation time 217960328 ps
CPU time 11.71 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:48 PM PDT 24
Peak memory 197988 kb
Host smart-5885b0f3-a512-4211-bd57-f3ae7c9016eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491197850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1491197850
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2557800392
Short name T608
Test name
Test status
Simulation time 150084694 ps
CPU time 1.15 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:41 PM PDT 24
Peak memory 197840 kb
Host smart-0abe5ab6-8f7e-4fa0-adce-71c53c3730e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557800392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2557800392
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2174689235
Short name T208
Test name
Test status
Simulation time 109058892 ps
CPU time 1.14 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:38 PM PDT 24
Peak memory 195808 kb
Host smart-3cf733e4-7384-43c8-993a-9d82dffb5fc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174689235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2174689235
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.4033469620
Short name T225
Test name
Test status
Simulation time 66938210 ps
CPU time 2.54 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:40 PM PDT 24
Peak memory 198024 kb
Host smart-f5d3eb14-0258-46e3-81ee-dc2d634a0742
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033469620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.4033469620
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3626196323
Short name T324
Test name
Test status
Simulation time 609130733 ps
CPU time 3.56 seconds
Started Mar 19 02:39:42 PM PDT 24
Finished Mar 19 02:39:46 PM PDT 24
Peak memory 195816 kb
Host smart-7cad44c5-d724-4533-b2ee-abae2b4500a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626196323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3626196323
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.791316884
Short name T169
Test name
Test status
Simulation time 15754463 ps
CPU time 0.7 seconds
Started Mar 19 02:39:40 PM PDT 24
Finished Mar 19 02:39:41 PM PDT 24
Peak memory 195040 kb
Host smart-4caff84e-eafa-4923-967a-a1ca65b7994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791316884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.791316884
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3126701375
Short name T445
Test name
Test status
Simulation time 252244185 ps
CPU time 0.75 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:37 PM PDT 24
Peak memory 195368 kb
Host smart-89bc75ae-7587-4c63-b7f6-c4a36fc91bc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126701375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3126701375
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2723005596
Short name T426
Test name
Test status
Simulation time 209647830 ps
CPU time 1.4 seconds
Started Mar 19 02:39:38 PM PDT 24
Finished Mar 19 02:39:39 PM PDT 24
Peak memory 197976 kb
Host smart-f9250744-3254-4e22-98f0-186f26cf3c55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723005596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2723005596
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.939251740
Short name T49
Test name
Test status
Simulation time 105570516 ps
CPU time 0.96 seconds
Started Mar 19 02:39:38 PM PDT 24
Finished Mar 19 02:39:39 PM PDT 24
Peak memory 213688 kb
Host smart-44bbd639-96d6-4a47-93cb-70a8dfc3f98c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939251740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.939251740
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3503264101
Short name T677
Test name
Test status
Simulation time 204154406 ps
CPU time 1.25 seconds
Started Mar 19 02:39:35 PM PDT 24
Finished Mar 19 02:39:37 PM PDT 24
Peak memory 195724 kb
Host smart-c29f09a7-d431-4d31-aa7b-908ba5f8181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503264101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3503264101
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.9922217
Short name T588
Test name
Test status
Simulation time 136034051 ps
CPU time 1.03 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:38 PM PDT 24
Peak memory 196564 kb
Host smart-46b7c977-05a5-45ca-86fb-4e73c7fa36c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9922217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.9922217
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.433206033
Short name T353
Test name
Test status
Simulation time 6212496921 ps
CPU time 80.02 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:40:58 PM PDT 24
Peak memory 198184 kb
Host smart-a8a5113f-2a83-4367-a4ec-28985e23fecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433206033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.433206033
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2519171603
Short name T139
Test name
Test status
Simulation time 17209093 ps
CPU time 0.58 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:33 PM PDT 24
Peak memory 194608 kb
Host smart-5e8bcf18-84ad-439c-abd0-96e635e83ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519171603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2519171603
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.4219118338
Short name T516
Test name
Test status
Simulation time 73043373 ps
CPU time 0.7 seconds
Started Mar 19 02:41:33 PM PDT 24
Finished Mar 19 02:41:34 PM PDT 24
Peak memory 195200 kb
Host smart-a0cd05c0-c460-490f-a37b-63469969574e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219118338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.4219118338
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3180899929
Short name T197
Test name
Test status
Simulation time 7354403857 ps
CPU time 26.97 seconds
Started Mar 19 02:41:28 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 197064 kb
Host smart-153baa75-4f26-4b3b-bce6-4997f22d4cf2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180899929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3180899929
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2123588434
Short name T562
Test name
Test status
Simulation time 444156857 ps
CPU time 1.02 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:32 PM PDT 24
Peak memory 197796 kb
Host smart-60e84920-5f02-474f-b532-fb0f7e0b6620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123588434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2123588434
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1155444784
Short name T557
Test name
Test status
Simulation time 49002606 ps
CPU time 0.86 seconds
Started Mar 19 02:41:29 PM PDT 24
Finished Mar 19 02:41:30 PM PDT 24
Peak memory 196308 kb
Host smart-3663df6d-b88a-4e2b-9af1-34c555ed596f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155444784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1155444784
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1298583441
Short name T329
Test name
Test status
Simulation time 62615065 ps
CPU time 2.43 seconds
Started Mar 19 02:41:37 PM PDT 24
Finished Mar 19 02:41:40 PM PDT 24
Peak memory 198036 kb
Host smart-db19ad8f-64d7-46c1-a658-afd89c6bc87a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298583441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1298583441
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2593913866
Short name T342
Test name
Test status
Simulation time 31370391 ps
CPU time 1.03 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:32 PM PDT 24
Peak memory 196232 kb
Host smart-4e1d7735-5e0d-4b71-bfe2-f234bd83f459
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593913866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2593913866
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.768847516
Short name T633
Test name
Test status
Simulation time 40043569 ps
CPU time 0.93 seconds
Started Mar 19 02:41:29 PM PDT 24
Finished Mar 19 02:41:31 PM PDT 24
Peak memory 196104 kb
Host smart-848e84fe-c3c2-4ca2-b419-86c8d88e1fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768847516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.768847516
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3052680293
Short name T206
Test name
Test status
Simulation time 56890461 ps
CPU time 1.07 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:33 PM PDT 24
Peak memory 196008 kb
Host smart-cb72a4f6-f552-4e3f-9cee-1cba856193c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052680293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3052680293
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3202531276
Short name T579
Test name
Test status
Simulation time 341658503 ps
CPU time 6.12 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:37 PM PDT 24
Peak memory 197964 kb
Host smart-27da8fc6-0d19-40a3-bf42-18887028ee31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202531276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3202531276
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2333413855
Short name T109
Test name
Test status
Simulation time 46786423 ps
CPU time 0.91 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:32 PM PDT 24
Peak memory 195436 kb
Host smart-74a97a16-8dd0-4b2a-8860-5770dfb9ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333413855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2333413855
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2385724450
Short name T540
Test name
Test status
Simulation time 103749165 ps
CPU time 1.14 seconds
Started Mar 19 02:41:29 PM PDT 24
Finished Mar 19 02:41:31 PM PDT 24
Peak memory 196380 kb
Host smart-6bd95796-bf98-4e20-b0c4-fc84d53d7b29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385724450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2385724450
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2216293494
Short name T323
Test name
Test status
Simulation time 23715077655 ps
CPU time 168.95 seconds
Started Mar 19 02:41:29 PM PDT 24
Finished Mar 19 02:44:18 PM PDT 24
Peak memory 198208 kb
Host smart-8cb7b10f-b37f-4274-9468-4f9498eb68c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216293494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2216293494
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3324208998
Short name T335
Test name
Test status
Simulation time 35649517 ps
CPU time 0.58 seconds
Started Mar 19 02:41:29 PM PDT 24
Finished Mar 19 02:41:30 PM PDT 24
Peak memory 194604 kb
Host smart-ac6eed29-2dc0-482c-98d2-725951c7741e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324208998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3324208998
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4181693530
Short name T160
Test name
Test status
Simulation time 18333110 ps
CPU time 0.68 seconds
Started Mar 19 02:41:27 PM PDT 24
Finished Mar 19 02:41:28 PM PDT 24
Peak memory 194740 kb
Host smart-1da5d2f1-dd45-4f8f-88bb-b5a3823cd1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181693530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4181693530
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3044082420
Short name T202
Test name
Test status
Simulation time 809670959 ps
CPU time 15.14 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:41:45 PM PDT 24
Peak memory 196812 kb
Host smart-78d86636-57c5-40c9-8baa-f614c031acfe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044082420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3044082420
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3086539569
Short name T161
Test name
Test status
Simulation time 116668370 ps
CPU time 0.98 seconds
Started Mar 19 02:41:35 PM PDT 24
Finished Mar 19 02:41:36 PM PDT 24
Peak memory 196356 kb
Host smart-1db00421-0bba-472e-a21d-f1d1cff7445b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086539569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3086539569
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3358775051
Short name T466
Test name
Test status
Simulation time 205315926 ps
CPU time 1.46 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:34 PM PDT 24
Peak memory 197096 kb
Host smart-4da47adf-b842-4a82-a383-9f00f703ad7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358775051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3358775051
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2588029014
Short name T302
Test name
Test status
Simulation time 234027728 ps
CPU time 2.54 seconds
Started Mar 19 02:41:34 PM PDT 24
Finished Mar 19 02:41:37 PM PDT 24
Peak memory 198080 kb
Host smart-ddb367bd-4465-4691-a732-4e38b0cde215
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588029014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2588029014
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.813728096
Short name T369
Test name
Test status
Simulation time 39086631 ps
CPU time 1.13 seconds
Started Mar 19 02:41:33 PM PDT 24
Finished Mar 19 02:41:34 PM PDT 24
Peak memory 195700 kb
Host smart-63b15c56-c0ed-4563-b834-2bbf8d885c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813728096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
813728096
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3644302408
Short name T587
Test name
Test status
Simulation time 228725588 ps
CPU time 1.44 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:33 PM PDT 24
Peak memory 196944 kb
Host smart-9c72ba99-e4db-4f38-a0ae-6f1b78bc294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644302408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3644302408
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.227409546
Short name T697
Test name
Test status
Simulation time 50443566 ps
CPU time 0.73 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:41:31 PM PDT 24
Peak memory 195468 kb
Host smart-8e8ef2de-2ee1-4dbe-a726-b2225d665707
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227409546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.227409546
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3242902415
Short name T211
Test name
Test status
Simulation time 282606237 ps
CPU time 5.07 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:37 PM PDT 24
Peak memory 197956 kb
Host smart-a51bf0b1-4c40-4d48-a8bf-22e5a294f3cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242902415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3242902415
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.763229392
Short name T26
Test name
Test status
Simulation time 35517518 ps
CPU time 0.83 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:32 PM PDT 24
Peak memory 195288 kb
Host smart-9cb54219-b0a3-48cb-94a3-90933ed38cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763229392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.763229392
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1570231517
Short name T444
Test name
Test status
Simulation time 63548140 ps
CPU time 1.37 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:41:31 PM PDT 24
Peak memory 195776 kb
Host smart-c4acf94e-ae22-4edf-9d6c-db52ceb14f7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570231517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1570231517
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.936310593
Short name T258
Test name
Test status
Simulation time 5875857909 ps
CPU time 58.62 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:42:29 PM PDT 24
Peak memory 198132 kb
Host smart-73935178-8a43-49da-8dff-e6c94be62857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936310593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.936310593
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3714453493
Short name T62
Test name
Test status
Simulation time 26359515028 ps
CPU time 372.56 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:47:42 PM PDT 24
Peak memory 198264 kb
Host smart-0451b966-b8a6-4e54-9854-b3c02209a064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3714453493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3714453493
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1166092499
Short name T173
Test name
Test status
Simulation time 12431843 ps
CPU time 0.57 seconds
Started Mar 19 02:41:37 PM PDT 24
Finished Mar 19 02:41:38 PM PDT 24
Peak memory 193916 kb
Host smart-42e20c75-44b4-4074-a399-095a37903c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166092499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1166092499
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3698679077
Short name T217
Test name
Test status
Simulation time 156075044 ps
CPU time 0.94 seconds
Started Mar 19 02:41:37 PM PDT 24
Finished Mar 19 02:41:39 PM PDT 24
Peak memory 196600 kb
Host smart-5ca1fbf9-40e3-4df5-8b96-3e4686c893d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698679077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3698679077
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4013084883
Short name T213
Test name
Test status
Simulation time 1042807853 ps
CPU time 27.42 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:59 PM PDT 24
Peak memory 197984 kb
Host smart-e10d7260-a93f-416c-8dd0-655846099d7e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013084883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4013084883
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.734438136
Short name T368
Test name
Test status
Simulation time 29716300 ps
CPU time 0.67 seconds
Started Mar 19 02:41:35 PM PDT 24
Finished Mar 19 02:41:35 PM PDT 24
Peak memory 194572 kb
Host smart-97b0ba77-51a6-4c9c-8108-0ba67c6cd3c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734438136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.734438136
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2786463155
Short name T267
Test name
Test status
Simulation time 143136348 ps
CPU time 1.14 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:34 PM PDT 24
Peak memory 195840 kb
Host smart-0ebfd5fe-9cfa-4119-b427-86e6a821b048
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786463155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2786463155
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3199779011
Short name T182
Test name
Test status
Simulation time 74141004 ps
CPU time 1.67 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:33 PM PDT 24
Peak memory 198012 kb
Host smart-a86d59be-8955-4c6e-8ce7-16bc43ebb99e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199779011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3199779011
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1802334322
Short name T431
Test name
Test status
Simulation time 155903268 ps
CPU time 2.78 seconds
Started Mar 19 02:41:29 PM PDT 24
Finished Mar 19 02:41:32 PM PDT 24
Peak memory 197212 kb
Host smart-cffa2aa8-300c-41fb-8d3c-6a6cc077a165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802334322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1802334322
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1937390035
Short name T679
Test name
Test status
Simulation time 143265617 ps
CPU time 1.45 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:33 PM PDT 24
Peak memory 197092 kb
Host smart-bc7314bb-7772-4bb9-a010-48f49e9f6b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937390035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1937390035
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1696398811
Short name T400
Test name
Test status
Simulation time 73811884 ps
CPU time 1.35 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:33 PM PDT 24
Peak memory 197104 kb
Host smart-6da9168f-8936-46ee-bf1a-c5076fb53c34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696398811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1696398811
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1369745594
Short name T339
Test name
Test status
Simulation time 501416148 ps
CPU time 3.9 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:41:34 PM PDT 24
Peak memory 197952 kb
Host smart-1e2f1cbf-5283-47f6-9f69-8a4bb325783d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369745594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1369745594
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3525232588
Short name T56
Test name
Test status
Simulation time 148601152 ps
CPU time 1.28 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:41:31 PM PDT 24
Peak memory 195816 kb
Host smart-814a6417-b51f-4a36-abff-9793b8329f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525232588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3525232588
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3242313213
Short name T71
Test name
Test status
Simulation time 169048066 ps
CPU time 1.4 seconds
Started Mar 19 02:41:31 PM PDT 24
Finished Mar 19 02:41:33 PM PDT 24
Peak memory 195496 kb
Host smart-d3dec44e-a0b9-4dac-a628-ea2aa36d66fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242313213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3242313213
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3151274698
Short name T520
Test name
Test status
Simulation time 4015832635 ps
CPU time 23.49 seconds
Started Mar 19 02:41:32 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 198188 kb
Host smart-ba2713d1-d915-4eae-ba31-f705295ee7d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151274698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3151274698
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2695310785
Short name T63
Test name
Test status
Simulation time 33907223127 ps
CPU time 363.61 seconds
Started Mar 19 02:41:30 PM PDT 24
Finished Mar 19 02:47:34 PM PDT 24
Peak memory 198244 kb
Host smart-61f50050-ab8f-4205-8922-fb371b99fc26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2695310785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2695310785
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.918755889
Short name T306
Test name
Test status
Simulation time 11895908 ps
CPU time 0.58 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 193940 kb
Host smart-d5176b43-e52b-4c65-822e-5ec9ac03b165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918755889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.918755889
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3127685373
Short name T240
Test name
Test status
Simulation time 95271295 ps
CPU time 0.72 seconds
Started Mar 19 02:41:42 PM PDT 24
Finished Mar 19 02:41:43 PM PDT 24
Peak memory 194888 kb
Host smart-e3776691-d5c5-4087-9764-4591e3a6221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127685373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3127685373
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1365543245
Short name T399
Test name
Test status
Simulation time 2158103440 ps
CPU time 22.2 seconds
Started Mar 19 02:41:44 PM PDT 24
Finished Mar 19 02:42:06 PM PDT 24
Peak memory 198056 kb
Host smart-192cf101-ab28-4cee-bf71-656b4f1f3cc4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365543245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1365543245
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2053617724
Short name T363
Test name
Test status
Simulation time 189795617 ps
CPU time 0.96 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 196188 kb
Host smart-4097579c-944a-4a13-b932-587f63c05af8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053617724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2053617724
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1352569079
Short name T315
Test name
Test status
Simulation time 46062530 ps
CPU time 1.22 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 197452 kb
Host smart-3c51b70d-4d87-456a-a202-2689eb76a7be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352569079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1352569079
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3105064568
Short name T170
Test name
Test status
Simulation time 204491298 ps
CPU time 2.24 seconds
Started Mar 19 02:41:44 PM PDT 24
Finished Mar 19 02:41:46 PM PDT 24
Peak memory 197972 kb
Host smart-a81440c7-84a9-4f9f-a7c1-e78aee5d2abd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105064568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3105064568
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1042008388
Short name T670
Test name
Test status
Simulation time 284422023 ps
CPU time 2.38 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:45 PM PDT 24
Peak memory 197132 kb
Host smart-d60e5a5a-4394-4194-bb61-5f3c697aa9e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042008388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1042008388
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1241935695
Short name T619
Test name
Test status
Simulation time 44257263 ps
CPU time 0.95 seconds
Started Mar 19 02:41:44 PM PDT 24
Finished Mar 19 02:41:45 PM PDT 24
Peak memory 195904 kb
Host smart-86a13252-fc9e-4c91-a07e-047c0eb64857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241935695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1241935695
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2119617893
Short name T273
Test name
Test status
Simulation time 38430835 ps
CPU time 0.72 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 195044 kb
Host smart-3fe11b63-3f4f-4833-837d-393c62e629d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119617893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2119617893
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1036665750
Short name T262
Test name
Test status
Simulation time 2064476101 ps
CPU time 4.7 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:48 PM PDT 24
Peak memory 197924 kb
Host smart-33eeddbc-bbf2-4bd9-9cf5-da4f614e2d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036665750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1036665750
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2249229043
Short name T696
Test name
Test status
Simulation time 65155595 ps
CPU time 1.22 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 196292 kb
Host smart-fc0a1bab-5082-426c-8b15-194a22d23f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249229043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2249229043
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2625607540
Short name T269
Test name
Test status
Simulation time 122214431 ps
CPU time 1.03 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 195672 kb
Host smart-d8105f58-c809-4a04-80bd-207110872614
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625607540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2625607540
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3459735989
Short name T441
Test name
Test status
Simulation time 18666235881 ps
CPU time 79.24 seconds
Started Mar 19 02:41:45 PM PDT 24
Finished Mar 19 02:43:05 PM PDT 24
Peak memory 198184 kb
Host smart-91696bea-bd9d-4313-a080-dfc126fd0f0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459735989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3459735989
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3898000426
Short name T29
Test name
Test status
Simulation time 693989569994 ps
CPU time 2147.72 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 03:17:31 PM PDT 24
Peak memory 198240 kb
Host smart-24012c3a-2b2a-461e-b52f-f4584422c1f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3898000426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3898000426
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3440346274
Short name T378
Test name
Test status
Simulation time 43432009 ps
CPU time 0.61 seconds
Started Mar 19 02:41:44 PM PDT 24
Finished Mar 19 02:41:45 PM PDT 24
Peak memory 193940 kb
Host smart-0dd30659-6b38-44cc-aea2-ad817966b2fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440346274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3440346274
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.141673466
Short name T205
Test name
Test status
Simulation time 39290958 ps
CPU time 0.81 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 195404 kb
Host smart-43c00466-c198-4fa8-8594-c46e463232ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141673466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.141673466
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2672726758
Short name T223
Test name
Test status
Simulation time 1373346063 ps
CPU time 13.75 seconds
Started Mar 19 02:41:46 PM PDT 24
Finished Mar 19 02:42:00 PM PDT 24
Peak memory 196764 kb
Host smart-214038a3-9a7e-408a-96fa-c0a24f9634a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672726758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2672726758
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.141571476
Short name T433
Test name
Test status
Simulation time 100491189 ps
CPU time 0.68 seconds
Started Mar 19 02:41:44 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 195276 kb
Host smart-3cb13a2e-f9e4-4a2a-8ad6-bba6cd35231f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141571476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.141571476
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2501186797
Short name T512
Test name
Test status
Simulation time 225700846 ps
CPU time 1.33 seconds
Started Mar 19 02:41:45 PM PDT 24
Finished Mar 19 02:41:46 PM PDT 24
Peak memory 196644 kb
Host smart-80390918-0a0a-4fa8-aaed-44462432455f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501186797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2501186797
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.4023470746
Short name T104
Test name
Test status
Simulation time 340336849 ps
CPU time 3.55 seconds
Started Mar 19 02:41:41 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 198120 kb
Host smart-2fc010fd-c44c-4b69-95e3-c3f8f3c33b1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023470746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.4023470746
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2187713706
Short name T327
Test name
Test status
Simulation time 511099511 ps
CPU time 3.01 seconds
Started Mar 19 02:41:44 PM PDT 24
Finished Mar 19 02:41:48 PM PDT 24
Peak memory 196484 kb
Host smart-961137c5-1cd5-48a4-b1c3-af963d8851d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187713706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2187713706
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3977299673
Short name T530
Test name
Test status
Simulation time 34351479 ps
CPU time 0.85 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 195552 kb
Host smart-8019c619-becc-4bb9-9ffc-d00dcdb36ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977299673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3977299673
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2951472886
Short name T297
Test name
Test status
Simulation time 46483279 ps
CPU time 1.19 seconds
Started Mar 19 02:41:44 PM PDT 24
Finished Mar 19 02:41:46 PM PDT 24
Peak memory 196732 kb
Host smart-a06dc5f3-248e-44fb-8219-32e3f15fdb98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951472886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2951472886
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.831367061
Short name T547
Test name
Test status
Simulation time 308311485 ps
CPU time 1.33 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 197792 kb
Host smart-eb6d1a03-05e9-42af-8a27-0c98480368c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831367061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.831367061
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.4095484568
Short name T425
Test name
Test status
Simulation time 44909608 ps
CPU time 0.83 seconds
Started Mar 19 02:41:44 PM PDT 24
Finished Mar 19 02:41:45 PM PDT 24
Peak memory 195420 kb
Host smart-3ab36bd1-3c6c-4fcc-91ce-1cde73f7dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095484568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.4095484568
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1843431473
Short name T422
Test name
Test status
Simulation time 86770915 ps
CPU time 0.95 seconds
Started Mar 19 02:41:42 PM PDT 24
Finished Mar 19 02:41:43 PM PDT 24
Peak memory 197300 kb
Host smart-dc474d75-53f8-456f-8ea2-d738a37c591c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843431473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1843431473
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2612951056
Short name T248
Test name
Test status
Simulation time 20301015335 ps
CPU time 76.02 seconds
Started Mar 19 02:41:45 PM PDT 24
Finished Mar 19 02:43:01 PM PDT 24
Peak memory 198180 kb
Host smart-73bedda1-98bb-4434-96cf-730ff74be1e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612951056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2612951056
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.264399437
Short name T412
Test name
Test status
Simulation time 13551522 ps
CPU time 0.57 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:54 PM PDT 24
Peak memory 193884 kb
Host smart-d1d53c44-e0ed-4488-b7fd-78fbd7827894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264399437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.264399437
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2817512984
Short name T496
Test name
Test status
Simulation time 90094995 ps
CPU time 0.95 seconds
Started Mar 19 02:41:51 PM PDT 24
Finished Mar 19 02:41:52 PM PDT 24
Peak memory 195716 kb
Host smart-2f3f9c53-ff9e-4442-8142-2950b601e457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817512984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2817512984
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1434376107
Short name T636
Test name
Test status
Simulation time 752603734 ps
CPU time 20.07 seconds
Started Mar 19 02:41:55 PM PDT 24
Finished Mar 19 02:42:16 PM PDT 24
Peak memory 196756 kb
Host smart-6e808915-c6dd-40ae-a1be-6e94b74b923c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434376107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1434376107
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2363651265
Short name T142
Test name
Test status
Simulation time 85671763 ps
CPU time 1.06 seconds
Started Mar 19 02:41:54 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 197008 kb
Host smart-1b568530-0c28-4d5a-b59d-5f96edd4acc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363651265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2363651265
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1345565494
Short name T643
Test name
Test status
Simulation time 35030099 ps
CPU time 1.15 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 196848 kb
Host smart-734e594d-d48b-4e58-bd2a-042c04546031
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345565494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1345565494
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1079292909
Short name T229
Test name
Test status
Simulation time 237548241 ps
CPU time 2.84 seconds
Started Mar 19 02:41:57 PM PDT 24
Finished Mar 19 02:42:01 PM PDT 24
Peak memory 198056 kb
Host smart-07835813-f568-4a74-aacf-3ab2db152afd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079292909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1079292909
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3096542432
Short name T427
Test name
Test status
Simulation time 60900027 ps
CPU time 1.63 seconds
Started Mar 19 02:42:01 PM PDT 24
Finished Mar 19 02:42:03 PM PDT 24
Peak memory 196876 kb
Host smart-031c47b8-5f5b-4e74-ad94-0f05c87e5c07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096542432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3096542432
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2257977120
Short name T607
Test name
Test status
Simulation time 151294040 ps
CPU time 1.23 seconds
Started Mar 19 02:41:59 PM PDT 24
Finished Mar 19 02:42:00 PM PDT 24
Peak memory 197028 kb
Host smart-38c61097-288a-42f7-9366-67d523a405b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257977120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2257977120
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2406117264
Short name T686
Test name
Test status
Simulation time 37647272 ps
CPU time 0.95 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 195920 kb
Host smart-396ffc5a-bb16-4b69-9ef3-0c645f9f8ce1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406117264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2406117264
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1569253727
Short name T264
Test name
Test status
Simulation time 134259321 ps
CPU time 2.36 seconds
Started Mar 19 02:41:58 PM PDT 24
Finished Mar 19 02:42:01 PM PDT 24
Peak memory 197932 kb
Host smart-6b64be24-4c49-4c28-8459-d15d00a11d10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569253727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1569253727
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1326188556
Short name T418
Test name
Test status
Simulation time 33053089 ps
CPU time 0.86 seconds
Started Mar 19 02:41:43 PM PDT 24
Finished Mar 19 02:41:44 PM PDT 24
Peak memory 196392 kb
Host smart-d438ba84-7361-471c-b3e6-1bd15cfb9a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326188556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1326188556
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1299606492
Short name T554
Test name
Test status
Simulation time 47548231 ps
CPU time 1.44 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 195532 kb
Host smart-cc320262-23f2-4c92-b573-b953de94a3c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299606492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1299606492
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3144702103
Short name T325
Test name
Test status
Simulation time 8893652694 ps
CPU time 141.98 seconds
Started Mar 19 02:41:52 PM PDT 24
Finished Mar 19 02:44:15 PM PDT 24
Peak memory 198228 kb
Host smart-44d88510-f4da-4f9a-80ce-e863ec1cb7d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144702103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3144702103
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.750434718
Short name T346
Test name
Test status
Simulation time 49793991 ps
CPU time 0.56 seconds
Started Mar 19 02:41:58 PM PDT 24
Finished Mar 19 02:41:59 PM PDT 24
Peak memory 193912 kb
Host smart-5e7a142e-b7c7-4bad-8722-bd8af8b8ff4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750434718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.750434718
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1225949625
Short name T415
Test name
Test status
Simulation time 59638560 ps
CPU time 0.77 seconds
Started Mar 19 02:41:54 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 195324 kb
Host smart-c7b5c19b-fe33-4e5e-9dd3-a094ae0180b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225949625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1225949625
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2739757446
Short name T503
Test name
Test status
Simulation time 451751918 ps
CPU time 23.23 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:42:17 PM PDT 24
Peak memory 197976 kb
Host smart-68143708-6db0-4bd5-b3bb-8852cc634889
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739757446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2739757446
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1944035067
Short name T147
Test name
Test status
Simulation time 354470143 ps
CPU time 0.76 seconds
Started Mar 19 02:41:54 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 194724 kb
Host smart-af2bc733-503b-4985-829d-13a0a3f6fa47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944035067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1944035067
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3816244230
Short name T467
Test name
Test status
Simulation time 83553278 ps
CPU time 1.45 seconds
Started Mar 19 02:41:52 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 198088 kb
Host smart-0bb9d1a4-74ab-4893-83e4-fea039d4a866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816244230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3816244230
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3022937301
Short name T710
Test name
Test status
Simulation time 63093090 ps
CPU time 2.7 seconds
Started Mar 19 02:42:01 PM PDT 24
Finished Mar 19 02:42:04 PM PDT 24
Peak memory 198020 kb
Host smart-70719b59-d311-4859-b6ce-95923935d4a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022937301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3022937301
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3451537506
Short name T594
Test name
Test status
Simulation time 1886879917 ps
CPU time 3.82 seconds
Started Mar 19 02:41:56 PM PDT 24
Finished Mar 19 02:42:00 PM PDT 24
Peak memory 196996 kb
Host smart-64988cce-be92-4013-a174-f7a097889d3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451537506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3451537506
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.4069023147
Short name T114
Test name
Test status
Simulation time 217957075 ps
CPU time 1.4 seconds
Started Mar 19 02:41:52 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 196924 kb
Host smart-3e1c018c-edf6-448a-ae91-4a0332344d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069023147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.4069023147
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1628325422
Short name T168
Test name
Test status
Simulation time 102129969 ps
CPU time 1.23 seconds
Started Mar 19 02:41:52 PM PDT 24
Finished Mar 19 02:41:53 PM PDT 24
Peak memory 195828 kb
Host smart-53a3e439-9572-4bdc-b9b7-ab21d8ea2b3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628325422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1628325422
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3555539257
Short name T132
Test name
Test status
Simulation time 1431995830 ps
CPU time 6.21 seconds
Started Mar 19 02:41:52 PM PDT 24
Finished Mar 19 02:41:58 PM PDT 24
Peak memory 197900 kb
Host smart-fc6e3b7b-8f35-419a-afcb-75c0abe47b31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555539257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3555539257
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.862579925
Short name T122
Test name
Test status
Simulation time 103669512 ps
CPU time 1.06 seconds
Started Mar 19 02:41:54 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 196444 kb
Host smart-dab459d8-ad1a-4800-b870-f8cbcd05b29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862579925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.862579925
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.823221525
Short name T249
Test name
Test status
Simulation time 268556687 ps
CPU time 1.12 seconds
Started Mar 19 02:41:58 PM PDT 24
Finished Mar 19 02:41:59 PM PDT 24
Peak memory 195756 kb
Host smart-86c3e2e3-dbb0-48ff-977e-51170d0909df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823221525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.823221525
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3457759106
Short name T332
Test name
Test status
Simulation time 6701415164 ps
CPU time 86.7 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:43:20 PM PDT 24
Peak memory 198156 kb
Host smart-5d1b5a19-de8f-44f0-9508-bb24351862be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457759106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3457759106
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.273384836
Short name T706
Test name
Test status
Simulation time 34913283 ps
CPU time 0.56 seconds
Started Mar 19 02:41:54 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 192772 kb
Host smart-6e2365ec-29e4-4665-bec8-d66dc5ae13fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273384836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.273384836
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2815948147
Short name T191
Test name
Test status
Simulation time 46114552 ps
CPU time 0.97 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 195904 kb
Host smart-158b7d3f-adff-470f-b854-3b0a35f29a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815948147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2815948147
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.950173052
Short name T601
Test name
Test status
Simulation time 332878078 ps
CPU time 16.95 seconds
Started Mar 19 02:41:55 PM PDT 24
Finished Mar 19 02:42:13 PM PDT 24
Peak memory 197980 kb
Host smart-ff950705-cba8-4262-8235-89923c6963ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950173052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.950173052
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3412687645
Short name T536
Test name
Test status
Simulation time 175412905 ps
CPU time 0.79 seconds
Started Mar 19 02:41:55 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 195804 kb
Host smart-b5759469-caa3-48ad-8397-a591c690b8fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412687645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3412687645
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2125831974
Short name T563
Test name
Test status
Simulation time 72391583 ps
CPU time 1.32 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 196656 kb
Host smart-0e1e3b37-5c27-4d0e-98e4-57091a6e1167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125831974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2125831974
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1445228914
Short name T103
Test name
Test status
Simulation time 197587163 ps
CPU time 2.17 seconds
Started Mar 19 02:41:55 PM PDT 24
Finished Mar 19 02:41:58 PM PDT 24
Peak memory 197904 kb
Host smart-af2d9faf-dd08-4127-a0f6-113cca0875f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445228914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1445228914
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3502007980
Short name T667
Test name
Test status
Simulation time 128196607 ps
CPU time 4.01 seconds
Started Mar 19 02:41:54 PM PDT 24
Finished Mar 19 02:41:59 PM PDT 24
Peak memory 195632 kb
Host smart-a4c510e1-7ad7-4707-a71f-e0d6e25efe41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502007980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3502007980
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2155787291
Short name T483
Test name
Test status
Simulation time 115017513 ps
CPU time 1.51 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 196984 kb
Host smart-56c65fbf-e1e8-483d-886e-a3b09c34d14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155787291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2155787291
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1536465020
Short name T671
Test name
Test status
Simulation time 21108994 ps
CPU time 0.85 seconds
Started Mar 19 02:41:54 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 196508 kb
Host smart-f7910989-869f-4c4b-9906-ddae523f0825
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536465020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1536465020
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.898391408
Short name T373
Test name
Test status
Simulation time 156679001 ps
CPU time 3.81 seconds
Started Mar 19 02:42:01 PM PDT 24
Finished Mar 19 02:42:05 PM PDT 24
Peak memory 197952 kb
Host smart-b179f617-5949-43c5-ac02-5536a12028cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898391408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.898391408
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3922311548
Short name T189
Test name
Test status
Simulation time 140506310 ps
CPU time 1.37 seconds
Started Mar 19 02:41:52 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 196788 kb
Host smart-c8a79e05-389f-4b43-88b0-91efcf4807ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922311548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3922311548
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3028200485
Short name T558
Test name
Test status
Simulation time 62941556 ps
CPU time 1.23 seconds
Started Mar 19 02:41:56 PM PDT 24
Finished Mar 19 02:41:58 PM PDT 24
Peak memory 195812 kb
Host smart-14f70a10-cad6-4a62-b153-150cd9c9a682
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028200485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3028200485
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.344722583
Short name T385
Test name
Test status
Simulation time 38429457635 ps
CPU time 215.33 seconds
Started Mar 19 02:41:57 PM PDT 24
Finished Mar 19 02:45:33 PM PDT 24
Peak memory 198156 kb
Host smart-df1cbb71-3b00-41e6-83fa-12e5de3ade1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344722583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.344722583
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3258177441
Short name T527
Test name
Test status
Simulation time 12451005 ps
CPU time 0.6 seconds
Started Mar 19 02:42:02 PM PDT 24
Finished Mar 19 02:42:02 PM PDT 24
Peak memory 193940 kb
Host smart-0d187983-e730-4de6-8b07-9ce5f49a0ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258177441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3258177441
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2910326453
Short name T506
Test name
Test status
Simulation time 54290282 ps
CPU time 0.93 seconds
Started Mar 19 02:41:59 PM PDT 24
Finished Mar 19 02:42:00 PM PDT 24
Peak memory 195920 kb
Host smart-5acaa5ce-e781-4cab-b9f0-ed054a526951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910326453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2910326453
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2835416670
Short name T681
Test name
Test status
Simulation time 1114141379 ps
CPU time 15.58 seconds
Started Mar 19 02:41:54 PM PDT 24
Finished Mar 19 02:42:11 PM PDT 24
Peak memory 196524 kb
Host smart-1558238b-4528-4224-a853-1ef6a0e4d210
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835416670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2835416670
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1709982808
Short name T159
Test name
Test status
Simulation time 31411195 ps
CPU time 0.8 seconds
Started Mar 19 02:41:56 PM PDT 24
Finished Mar 19 02:41:57 PM PDT 24
Peak memory 196484 kb
Host smart-c7ae7052-0c6f-414f-9a62-554ec15c6d76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709982808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1709982808
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1208310411
Short name T454
Test name
Test status
Simulation time 73517276 ps
CPU time 1.24 seconds
Started Mar 19 02:41:52 PM PDT 24
Finished Mar 19 02:41:54 PM PDT 24
Peak memory 196648 kb
Host smart-1a4df187-14a6-4b14-9a16-d720ce017d85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208310411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1208310411
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1962061718
Short name T541
Test name
Test status
Simulation time 97983197 ps
CPU time 2.14 seconds
Started Mar 19 02:41:52 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 197992 kb
Host smart-fb534e9d-029b-4947-a410-286a9fa40781
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962061718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1962061718
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2664878094
Short name T615
Test name
Test status
Simulation time 138318251 ps
CPU time 3.04 seconds
Started Mar 19 02:41:55 PM PDT 24
Finished Mar 19 02:41:59 PM PDT 24
Peak memory 197272 kb
Host smart-66065412-677d-4a92-9e40-46653b63a143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664878094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2664878094
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1957397907
Short name T654
Test name
Test status
Simulation time 22674135 ps
CPU time 0.69 seconds
Started Mar 19 02:41:55 PM PDT 24
Finished Mar 19 02:41:57 PM PDT 24
Peak memory 195044 kb
Host smart-6268c7b9-7f14-4643-b72d-e0c97e22af4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957397907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1957397907
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2960753891
Short name T314
Test name
Test status
Simulation time 148954391 ps
CPU time 0.87 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 196440 kb
Host smart-3fce21ec-167f-4014-8f00-2e5a51cd6271
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960753891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2960753891
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3607010832
Short name T67
Test name
Test status
Simulation time 345515064 ps
CPU time 4.23 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:58 PM PDT 24
Peak memory 197940 kb
Host smart-a21823b2-8f65-4cbc-8235-b26bb8b721b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607010832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3607010832
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2005213376
Short name T15
Test name
Test status
Simulation time 40247618 ps
CPU time 1.23 seconds
Started Mar 19 02:41:54 PM PDT 24
Finished Mar 19 02:41:56 PM PDT 24
Peak memory 195752 kb
Host smart-ca5511f8-62ef-43cc-9230-a1b649f53360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005213376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2005213376
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1495586970
Short name T509
Test name
Test status
Simulation time 35222752 ps
CPU time 0.86 seconds
Started Mar 19 02:41:53 PM PDT 24
Finished Mar 19 02:41:55 PM PDT 24
Peak memory 195276 kb
Host smart-1a600960-e4fd-4eb5-8018-08baba38bb4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495586970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1495586970
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1298800351
Short name T482
Test name
Test status
Simulation time 8825035284 ps
CPU time 136.52 seconds
Started Mar 19 02:41:55 PM PDT 24
Finished Mar 19 02:44:13 PM PDT 24
Peak memory 198080 kb
Host smart-3ac4d594-10f7-478e-a4b7-f9918827da33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298800351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1298800351
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.499192566
Short name T364
Test name
Test status
Simulation time 31502936 ps
CPU time 0.55 seconds
Started Mar 19 02:42:10 PM PDT 24
Finished Mar 19 02:42:11 PM PDT 24
Peak memory 193896 kb
Host smart-3f6eb312-60d5-4699-b269-64202fa1e6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499192566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.499192566
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3241238585
Short name T605
Test name
Test status
Simulation time 61235188 ps
CPU time 0.66 seconds
Started Mar 19 02:41:59 PM PDT 24
Finished Mar 19 02:42:00 PM PDT 24
Peak memory 194112 kb
Host smart-19310579-21a9-4868-9408-db9f812a9df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241238585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3241238585
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3116606777
Short name T133
Test name
Test status
Simulation time 1632284616 ps
CPU time 21.34 seconds
Started Mar 19 02:42:04 PM PDT 24
Finished Mar 19 02:42:26 PM PDT 24
Peak memory 196716 kb
Host smart-d3276c40-2a60-4ea6-bf1a-d736eb8b4c40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116606777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3116606777
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1072304146
Short name T639
Test name
Test status
Simulation time 34775607 ps
CPU time 0.72 seconds
Started Mar 19 02:42:10 PM PDT 24
Finished Mar 19 02:42:11 PM PDT 24
Peak memory 194716 kb
Host smart-0c318ef5-0f67-48ff-b859-6090f8e6007a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072304146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1072304146
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2388490206
Short name T179
Test name
Test status
Simulation time 779455338 ps
CPU time 1.32 seconds
Started Mar 19 02:41:59 PM PDT 24
Finished Mar 19 02:42:01 PM PDT 24
Peak memory 197088 kb
Host smart-bb5a9ede-602d-4a3e-bca5-0f00eaf51810
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388490206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2388490206
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1839790442
Short name T278
Test name
Test status
Simulation time 161025641 ps
CPU time 1.7 seconds
Started Mar 19 02:42:01 PM PDT 24
Finished Mar 19 02:42:03 PM PDT 24
Peak memory 197948 kb
Host smart-26a75deb-c332-428a-8c40-2721e3f9dcce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839790442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1839790442
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2752392616
Short name T534
Test name
Test status
Simulation time 476978181 ps
CPU time 2.08 seconds
Started Mar 19 02:42:03 PM PDT 24
Finished Mar 19 02:42:05 PM PDT 24
Peak memory 196156 kb
Host smart-67eb31bd-2434-4832-aa52-811a5e184110
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752392616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2752392616
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.469417811
Short name T699
Test name
Test status
Simulation time 57620352 ps
CPU time 1.17 seconds
Started Mar 19 02:41:59 PM PDT 24
Finished Mar 19 02:42:01 PM PDT 24
Peak memory 196088 kb
Host smart-94dda3c1-524f-4305-bd19-8eaf79d53b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469417811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.469417811
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2587608909
Short name T158
Test name
Test status
Simulation time 55351410 ps
CPU time 0.88 seconds
Started Mar 19 02:42:11 PM PDT 24
Finished Mar 19 02:42:12 PM PDT 24
Peak memory 195568 kb
Host smart-81524f9c-6018-4e61-a8b2-cbcc7f7f004a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587608909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2587608909
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2572619384
Short name T186
Test name
Test status
Simulation time 51334690 ps
CPU time 2.4 seconds
Started Mar 19 02:42:02 PM PDT 24
Finished Mar 19 02:42:05 PM PDT 24
Peak memory 198004 kb
Host smart-c04dcd36-56ef-4a0f-9451-3900ef8ad945
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572619384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2572619384
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.841873042
Short name T280
Test name
Test status
Simulation time 239388814 ps
CPU time 1.33 seconds
Started Mar 19 02:42:10 PM PDT 24
Finished Mar 19 02:42:12 PM PDT 24
Peak memory 196512 kb
Host smart-dc7f3b0a-37e3-4dce-948c-4d9ae6aea2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841873042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.841873042
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2859983675
Short name T513
Test name
Test status
Simulation time 45501071 ps
CPU time 1.26 seconds
Started Mar 19 02:41:59 PM PDT 24
Finished Mar 19 02:42:01 PM PDT 24
Peak memory 196588 kb
Host smart-1be98938-a43d-40d4-a7e1-10683e95171e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859983675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2859983675
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2334271546
Short name T443
Test name
Test status
Simulation time 3164444549 ps
CPU time 76.13 seconds
Started Mar 19 02:42:10 PM PDT 24
Finished Mar 19 02:43:27 PM PDT 24
Peak memory 198160 kb
Host smart-f570d026-7931-4f55-86e4-df289e67c0dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334271546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2334271546
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3163099186
Short name T652
Test name
Test status
Simulation time 16780871 ps
CPU time 0.57 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 194608 kb
Host smart-9991cc5e-14a2-4e58-ab38-e574efbfe2c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163099186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3163099186
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2660761750
Short name T574
Test name
Test status
Simulation time 26050807 ps
CPU time 0.88 seconds
Started Mar 19 02:39:54 PM PDT 24
Finished Mar 19 02:39:55 PM PDT 24
Peak memory 195420 kb
Host smart-b22137fa-16b2-457d-8aa2-ef1cb7e039fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660761750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2660761750
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.220146601
Short name T171
Test name
Test status
Simulation time 739925123 ps
CPU time 13.24 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:40:02 PM PDT 24
Peak memory 196936 kb
Host smart-e40c7c09-4346-4ac4-85a9-6a82919b24d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220146601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.220146601
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.4286597196
Short name T134
Test name
Test status
Simulation time 57444355 ps
CPU time 1.02 seconds
Started Mar 19 02:39:51 PM PDT 24
Finished Mar 19 02:39:53 PM PDT 24
Peak memory 197996 kb
Host smart-eec3b0ec-56cf-4e47-8528-c71f34a89645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286597196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.4286597196
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1434754052
Short name T70
Test name
Test status
Simulation time 298576770 ps
CPU time 1.39 seconds
Started Mar 19 02:39:51 PM PDT 24
Finished Mar 19 02:39:53 PM PDT 24
Peak memory 198028 kb
Host smart-26d28027-2084-4782-8724-a48f0c2c925b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434754052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1434754052
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.108108362
Short name T190
Test name
Test status
Simulation time 89648918 ps
CPU time 2.99 seconds
Started Mar 19 02:39:49 PM PDT 24
Finished Mar 19 02:39:52 PM PDT 24
Peak memory 198056 kb
Host smart-d461c39d-aa35-42ca-8cc0-f89cb25d436d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108108362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.108108362
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.4292793757
Short name T162
Test name
Test status
Simulation time 65925392 ps
CPU time 1.55 seconds
Started Mar 19 02:39:49 PM PDT 24
Finished Mar 19 02:39:51 PM PDT 24
Peak memory 195976 kb
Host smart-7d3121e2-f493-4ee2-bf26-ce08ac1eb97c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292793757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
4292793757
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.451764806
Short name T623
Test name
Test status
Simulation time 53885780 ps
CPU time 1.26 seconds
Started Mar 19 02:39:47 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 197980 kb
Host smart-311ee8c5-fe9e-45a1-8f12-845c30b4ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451764806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.451764806
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.281008888
Short name T236
Test name
Test status
Simulation time 221842040 ps
CPU time 0.73 seconds
Started Mar 19 02:39:51 PM PDT 24
Finished Mar 19 02:39:51 PM PDT 24
Peak memory 195376 kb
Host smart-0d28f0e9-13d9-4f49-8d4b-259ebbf3ed27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281008888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.281008888
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1768426543
Short name T377
Test name
Test status
Simulation time 271626745 ps
CPU time 5.13 seconds
Started Mar 19 02:39:54 PM PDT 24
Finished Mar 19 02:39:59 PM PDT 24
Peak memory 197996 kb
Host smart-cb728b79-5504-4e9f-8c41-5276a6ca4b27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768426543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1768426543
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1166655447
Short name T472
Test name
Test status
Simulation time 207441207 ps
CPU time 1.08 seconds
Started Mar 19 02:39:38 PM PDT 24
Finished Mar 19 02:39:39 PM PDT 24
Peak memory 195516 kb
Host smart-52ed8798-c044-4b55-9888-ac3e1fce532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166655447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1166655447
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1025509064
Short name T648
Test name
Test status
Simulation time 583127910 ps
CPU time 1.16 seconds
Started Mar 19 02:39:37 PM PDT 24
Finished Mar 19 02:39:38 PM PDT 24
Peak memory 196460 kb
Host smart-b820f237-6123-4252-bb95-975beb60cd2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025509064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1025509064
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.4230602027
Short name T622
Test name
Test status
Simulation time 5158948840 ps
CPU time 142.48 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:42:10 PM PDT 24
Peak memory 198220 kb
Host smart-e0295f61-5277-4015-8870-309e128fc661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230602027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.4230602027
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.539062998
Short name T38
Test name
Test status
Simulation time 10596512 ps
CPU time 0.58 seconds
Started Mar 19 02:39:53 PM PDT 24
Finished Mar 19 02:39:54 PM PDT 24
Peak memory 193896 kb
Host smart-79ed8aea-8818-483d-94a6-ce9215f56bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539062998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.539062998
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3673193742
Short name T149
Test name
Test status
Simulation time 23848104 ps
CPU time 0.67 seconds
Started Mar 19 02:39:50 PM PDT 24
Finished Mar 19 02:39:51 PM PDT 24
Peak memory 194692 kb
Host smart-e98d3c6a-91f1-485d-bc63-7a987c2274d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673193742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3673193742
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1880946679
Short name T405
Test name
Test status
Simulation time 847065308 ps
CPU time 22.39 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:40:11 PM PDT 24
Peak memory 196908 kb
Host smart-4b3565a3-faf4-4a25-b77c-2894d3ce8e4b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880946679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1880946679
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2941247853
Short name T705
Test name
Test status
Simulation time 91256574 ps
CPU time 1.12 seconds
Started Mar 19 02:39:47 PM PDT 24
Finished Mar 19 02:39:48 PM PDT 24
Peak memory 197848 kb
Host smart-953b309b-ef3f-4cfa-afc0-f6544d526048
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941247853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2941247853
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2592162440
Short name T131
Test name
Test status
Simulation time 103582839 ps
CPU time 1.32 seconds
Started Mar 19 02:39:49 PM PDT 24
Finished Mar 19 02:39:50 PM PDT 24
Peak memory 196992 kb
Host smart-cf9c33b1-bc1d-4fb2-9301-5e2edbaa2ba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592162440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2592162440
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1058135903
Short name T665
Test name
Test status
Simulation time 44792716 ps
CPU time 1.13 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 196180 kb
Host smart-b8f22306-dcb4-4c00-a252-421bb9d1ac69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058135903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1058135903
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.197075162
Short name T309
Test name
Test status
Simulation time 277483994 ps
CPU time 2.1 seconds
Started Mar 19 02:39:49 PM PDT 24
Finished Mar 19 02:39:51 PM PDT 24
Peak memory 198052 kb
Host smart-ee18229b-40e9-40d2-8d92-6440c1f2b8d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197075162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.197075162
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1616774872
Short name T376
Test name
Test status
Simulation time 36463731 ps
CPU time 1.37 seconds
Started Mar 19 02:39:50 PM PDT 24
Finished Mar 19 02:39:52 PM PDT 24
Peak memory 196968 kb
Host smart-21816b15-eb54-441a-8392-c328cb0755b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616774872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1616774872
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.97237431
Short name T125
Test name
Test status
Simulation time 101942810 ps
CPU time 1.27 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 197040 kb
Host smart-10f54a3b-4284-4845-bbd0-da6d3fd52c25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97237431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_p
ulldown.97237431
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.211053622
Short name T265
Test name
Test status
Simulation time 316379450 ps
CPU time 2.97 seconds
Started Mar 19 02:39:49 PM PDT 24
Finished Mar 19 02:39:52 PM PDT 24
Peak memory 197924 kb
Host smart-b966d468-b43c-48c5-8640-4623b78be5d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211053622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.211053622
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3710542260
Short name T438
Test name
Test status
Simulation time 92118791 ps
CPU time 0.82 seconds
Started Mar 19 02:39:47 PM PDT 24
Finished Mar 19 02:39:48 PM PDT 24
Peak memory 195888 kb
Host smart-1ec64d30-cafd-4b55-b220-2fac5836030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710542260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3710542260
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.337567608
Short name T129
Test name
Test status
Simulation time 444851627 ps
CPU time 1.23 seconds
Started Mar 19 02:39:50 PM PDT 24
Finished Mar 19 02:39:51 PM PDT 24
Peak memory 196548 kb
Host smart-b2991a01-d943-4bb9-82e7-dd5eab085322
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337567608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.337567608
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3123108659
Short name T460
Test name
Test status
Simulation time 32166802989 ps
CPU time 85.19 seconds
Started Mar 19 02:39:52 PM PDT 24
Finished Mar 19 02:41:18 PM PDT 24
Peak memory 198100 kb
Host smart-505cc7e9-6b56-47df-9e87-ef0fa330278e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123108659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3123108659
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2301713124
Short name T484
Test name
Test status
Simulation time 38927252 ps
CPU time 0.6 seconds
Started Mar 19 02:39:47 PM PDT 24
Finished Mar 19 02:39:48 PM PDT 24
Peak memory 193888 kb
Host smart-bd43357c-a291-4d5e-91dc-1c9dc95a588f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301713124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2301713124
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2739550014
Short name T435
Test name
Test status
Simulation time 285226444 ps
CPU time 0.85 seconds
Started Mar 19 02:39:49 PM PDT 24
Finished Mar 19 02:39:50 PM PDT 24
Peak memory 196544 kb
Host smart-6a46ceae-1b95-413e-8b83-288f2d019a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739550014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2739550014
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1536936927
Short name T692
Test name
Test status
Simulation time 405216459 ps
CPU time 4.24 seconds
Started Mar 19 02:39:52 PM PDT 24
Finished Mar 19 02:39:57 PM PDT 24
Peak memory 196496 kb
Host smart-fe99cc63-213b-4a2d-8d1b-1283566f54ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536936927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1536936927
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3065888243
Short name T446
Test name
Test status
Simulation time 230388210 ps
CPU time 0.78 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 196480 kb
Host smart-ba718fe9-5bd9-4430-b136-04422219b3ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065888243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3065888243
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3576562830
Short name T194
Test name
Test status
Simulation time 54569330 ps
CPU time 1 seconds
Started Mar 19 02:39:53 PM PDT 24
Finished Mar 19 02:39:54 PM PDT 24
Peak memory 195616 kb
Host smart-dccc06fd-dceb-4563-b84b-c7867ac43160
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576562830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3576562830
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2763589157
Short name T627
Test name
Test status
Simulation time 81933996 ps
CPU time 3.28 seconds
Started Mar 19 02:39:53 PM PDT 24
Finished Mar 19 02:39:57 PM PDT 24
Peak memory 198104 kb
Host smart-87e79e11-a3ee-4d72-a577-239eb8ac1424
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763589157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2763589157
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1206655853
Short name T196
Test name
Test status
Simulation time 458632172 ps
CPU time 3.56 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:52 PM PDT 24
Peak memory 198012 kb
Host smart-70f0174a-3277-42dc-b38c-01a38e1cfe40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206655853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1206655853
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1535345961
Short name T313
Test name
Test status
Simulation time 113860218 ps
CPU time 1.22 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 195816 kb
Host smart-5d6d072d-80f4-4eb1-88ed-132542536830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535345961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1535345961
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3865240235
Short name T366
Test name
Test status
Simulation time 54592518 ps
CPU time 1.03 seconds
Started Mar 19 02:39:49 PM PDT 24
Finished Mar 19 02:39:50 PM PDT 24
Peak memory 195796 kb
Host smart-90c87741-c3c0-45f8-ad1e-e48e4a0032d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865240235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3865240235
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2770905042
Short name T3
Test name
Test status
Simulation time 183162445 ps
CPU time 1.52 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 197924 kb
Host smart-bb48a092-ef4d-4b91-aa4b-930c95f5e909
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770905042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2770905042
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3450911561
Short name T381
Test name
Test status
Simulation time 83602785 ps
CPU time 1.2 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 197068 kb
Host smart-0bfd7384-6cdb-439d-9ee8-7121b3d41ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450911561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3450911561
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1894392443
Short name T533
Test name
Test status
Simulation time 204928061 ps
CPU time 0.91 seconds
Started Mar 19 02:39:49 PM PDT 24
Finished Mar 19 02:39:50 PM PDT 24
Peak memory 195508 kb
Host smart-5ae28d7a-22a7-426c-b9ef-51df85fe9af7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894392443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1894392443
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1316089170
Short name T281
Test name
Test status
Simulation time 159532174453 ps
CPU time 129.14 seconds
Started Mar 19 02:39:47 PM PDT 24
Finished Mar 19 02:41:57 PM PDT 24
Peak memory 198192 kb
Host smart-a632de8c-f292-4ad9-814c-852e87ddc8f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316089170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1316089170
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2663746861
Short name T485
Test name
Test status
Simulation time 186233997 ps
CPU time 0.58 seconds
Started Mar 19 02:39:53 PM PDT 24
Finished Mar 19 02:39:53 PM PDT 24
Peak memory 194132 kb
Host smart-332db76b-4cfb-4455-98f4-fceb35fc5673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663746861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2663746861
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.732124769
Short name T401
Test name
Test status
Simulation time 61327221 ps
CPU time 0.78 seconds
Started Mar 19 02:39:50 PM PDT 24
Finished Mar 19 02:39:50 PM PDT 24
Peak memory 195308 kb
Host smart-9691fed7-4f70-499c-9d09-97c1b10a09f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732124769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.732124769
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.566354432
Short name T108
Test name
Test status
Simulation time 231985132 ps
CPU time 7.2 seconds
Started Mar 19 02:39:47 PM PDT 24
Finished Mar 19 02:39:54 PM PDT 24
Peak memory 196612 kb
Host smart-05e050f5-d3f8-48fe-b16b-fd129636cdd7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566354432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.566354432
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3578867679
Short name T529
Test name
Test status
Simulation time 86789154 ps
CPU time 1.11 seconds
Started Mar 19 02:39:53 PM PDT 24
Finished Mar 19 02:39:54 PM PDT 24
Peak memory 196300 kb
Host smart-79469657-7b0b-4eaf-bc3f-15cb834cf014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578867679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3578867679
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2152942203
Short name T252
Test name
Test status
Simulation time 32789091 ps
CPU time 0.92 seconds
Started Mar 19 02:39:53 PM PDT 24
Finished Mar 19 02:39:55 PM PDT 24
Peak memory 196240 kb
Host smart-40bc3a20-4d48-496f-9b55-07bfeb736986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152942203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2152942203
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.213595027
Short name T635
Test name
Test status
Simulation time 72609142 ps
CPU time 3.05 seconds
Started Mar 19 02:39:45 PM PDT 24
Finished Mar 19 02:39:48 PM PDT 24
Peak memory 198052 kb
Host smart-75c7d94e-7fdb-4fc0-946b-bff75f99bc0d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213595027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.213595027
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3385582252
Short name T387
Test name
Test status
Simulation time 357434135 ps
CPU time 2.81 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:51 PM PDT 24
Peak memory 198024 kb
Host smart-66e222df-67e2-4bd7-be57-3c49f65ecafa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385582252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3385582252
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1568405576
Short name T151
Test name
Test status
Simulation time 37019650 ps
CPU time 1.34 seconds
Started Mar 19 02:39:46 PM PDT 24
Finished Mar 19 02:39:47 PM PDT 24
Peak memory 195832 kb
Host smart-2c91dba4-e6be-465f-b007-379b1b51190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568405576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1568405576
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.908746575
Short name T475
Test name
Test status
Simulation time 172849689 ps
CPU time 1.13 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 196024 kb
Host smart-bad47fe3-03aa-4a47-8f11-8ff1384895f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908746575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.908746575
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3516011564
Short name T115
Test name
Test status
Simulation time 334278421 ps
CPU time 1.42 seconds
Started Mar 19 02:39:50 PM PDT 24
Finished Mar 19 02:39:52 PM PDT 24
Peak memory 197920 kb
Host smart-a0e3b007-c632-47ba-93d6-3a54adf444df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516011564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3516011564
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2978674624
Short name T144
Test name
Test status
Simulation time 23606815 ps
CPU time 0.82 seconds
Started Mar 19 02:39:50 PM PDT 24
Finished Mar 19 02:39:51 PM PDT 24
Peak memory 195404 kb
Host smart-83403ea0-2fac-4e50-95f1-708b8baebf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978674624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2978674624
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3979037970
Short name T375
Test name
Test status
Simulation time 60485015 ps
CPU time 1.24 seconds
Started Mar 19 02:39:48 PM PDT 24
Finished Mar 19 02:39:49 PM PDT 24
Peak memory 196428 kb
Host smart-dac865b8-68c6-4992-8812-1f1f38666df1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979037970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3979037970
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1365875417
Short name T255
Test name
Test status
Simulation time 4703675770 ps
CPU time 134.6 seconds
Started Mar 19 02:39:52 PM PDT 24
Finished Mar 19 02:42:07 PM PDT 24
Peak memory 198068 kb
Host smart-7098a61b-9e0a-4da1-8d83-3af71659e3cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365875417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1365875417
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3999511485
Short name T653
Test name
Test status
Simulation time 60557930166 ps
CPU time 834.1 seconds
Started Mar 19 02:39:55 PM PDT 24
Finished Mar 19 02:53:50 PM PDT 24
Peak memory 198128 kb
Host smart-d7d1b4ea-a5ec-4e67-a422-d3917bb2bd71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3999511485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3999511485
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1117037636
Short name T660
Test name
Test status
Simulation time 45069049 ps
CPU time 0.56 seconds
Started Mar 19 02:39:57 PM PDT 24
Finished Mar 19 02:39:58 PM PDT 24
Peak memory 192736 kb
Host smart-77165a7c-776e-40a6-b964-38a53d9d2d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117037636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1117037636
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1867260050
Short name T582
Test name
Test status
Simulation time 82566931 ps
CPU time 0.71 seconds
Started Mar 19 02:39:58 PM PDT 24
Finished Mar 19 02:39:58 PM PDT 24
Peak memory 194916 kb
Host smart-d832f200-1193-4ab7-b227-3cf70a4cb40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867260050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1867260050
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2726370268
Short name T166
Test name
Test status
Simulation time 367916782 ps
CPU time 11.31 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:10 PM PDT 24
Peak memory 196792 kb
Host smart-8839a505-4edd-42fb-b2cb-374dd64e96f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726370268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2726370268
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2299159934
Short name T290
Test name
Test status
Simulation time 195721299 ps
CPU time 0.85 seconds
Started Mar 19 02:39:58 PM PDT 24
Finished Mar 19 02:39:59 PM PDT 24
Peak memory 196584 kb
Host smart-e23c90b5-58f9-4440-a13f-66ea2dbcf2f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299159934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2299159934
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3949526998
Short name T50
Test name
Test status
Simulation time 38940689 ps
CPU time 1.19 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 196056 kb
Host smart-6a557fe0-e95c-45fb-9633-d7a873261434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949526998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3949526998
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2611519986
Short name T604
Test name
Test status
Simulation time 172489214 ps
CPU time 1.99 seconds
Started Mar 19 02:40:02 PM PDT 24
Finished Mar 19 02:40:04 PM PDT 24
Peak memory 198088 kb
Host smart-98d6b171-783c-47ba-949e-e230e3a8ca34
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611519986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2611519986
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1643904783
Short name T316
Test name
Test status
Simulation time 384023752 ps
CPU time 2.87 seconds
Started Mar 19 02:40:03 PM PDT 24
Finished Mar 19 02:40:06 PM PDT 24
Peak memory 195788 kb
Host smart-d01174fb-bf7f-4051-9fc8-9ae45499608e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643904783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1643904783
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.216775694
Short name T184
Test name
Test status
Simulation time 87732212 ps
CPU time 1.02 seconds
Started Mar 19 02:40:05 PM PDT 24
Finished Mar 19 02:40:06 PM PDT 24
Peak memory 195988 kb
Host smart-e8e8e8ee-7897-4cdd-98af-8bd7fd3cd4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216775694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.216775694
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.649519233
Short name T398
Test name
Test status
Simulation time 35426756 ps
CPU time 0.79 seconds
Started Mar 19 02:39:58 PM PDT 24
Finished Mar 19 02:39:59 PM PDT 24
Peak memory 195476 kb
Host smart-28ad09be-2556-4677-8e3f-cef169043b72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649519233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.649519233
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.527969859
Short name T592
Test name
Test status
Simulation time 42561496 ps
CPU time 2.03 seconds
Started Mar 19 02:40:01 PM PDT 24
Finished Mar 19 02:40:03 PM PDT 24
Peak memory 197948 kb
Host smart-fabd935f-2e7d-4832-8b57-147a9ee0025e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527969859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.527969859
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.277952120
Short name T630
Test name
Test status
Simulation time 31746162 ps
CPU time 1.09 seconds
Started Mar 19 02:39:53 PM PDT 24
Finished Mar 19 02:39:54 PM PDT 24
Peak memory 195540 kb
Host smart-cadcca63-04a4-4f74-bb0e-f3140f2af943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277952120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.277952120
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1617836839
Short name T673
Test name
Test status
Simulation time 44377069 ps
CPU time 0.9 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:40:00 PM PDT 24
Peak memory 195324 kb
Host smart-ee4f364e-1ed5-4c3f-909c-619034c0982d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617836839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1617836839
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2476575589
Short name T525
Test name
Test status
Simulation time 6709948189 ps
CPU time 182.44 seconds
Started Mar 19 02:39:59 PM PDT 24
Finished Mar 19 02:43:01 PM PDT 24
Peak memory 198244 kb
Host smart-daf59e32-c5a1-43c0-bab6-8906db14570f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476575589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2476575589
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2160942552
Short name T474
Test name
Test status
Simulation time 110400097253 ps
CPU time 434.35 seconds
Started Mar 19 02:40:02 PM PDT 24
Finished Mar 19 02:47:17 PM PDT 24
Peak memory 198236 kb
Host smart-43ef201b-f8b4-4afa-ab14-e89c3906f4e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2160942552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2160942552
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3329143058
Short name T854
Test name
Test status
Simulation time 346553560 ps
CPU time 1.13 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 196984 kb
Host smart-f1124bdf-a572-4d90-a83a-3dd281c70575
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3329143058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3329143058
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2671860679
Short name T925
Test name
Test status
Simulation time 116894513 ps
CPU time 1.01 seconds
Started Mar 19 02:47:00 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 192396 kb
Host smart-0a07f34f-f150-4ae5-836d-dd9ddec3b742
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671860679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2671860679
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.710956629
Short name T892
Test name
Test status
Simulation time 34980744 ps
CPU time 0.91 seconds
Started Mar 19 02:46:59 PM PDT 24
Finished Mar 19 02:47:00 PM PDT 24
Peak memory 192172 kb
Host smart-6d76923b-5b83-4966-90ec-c670a0f7c2f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=710956629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.710956629
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3454738890
Short name T856
Test name
Test status
Simulation time 81560976 ps
CPU time 1.3 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 192324 kb
Host smart-4e9ab5c9-6850-4e46-a14d-9017e09e3c95
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454738890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3454738890
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2117081757
Short name T841
Test name
Test status
Simulation time 271153276 ps
CPU time 1.45 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:08 PM PDT 24
Peak memory 192328 kb
Host smart-eedcf872-a792-41f1-aca8-35cb2a6fc78b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2117081757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2117081757
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2149839179
Short name T867
Test name
Test status
Simulation time 30111118 ps
CPU time 0.77 seconds
Started Mar 19 02:47:08 PM PDT 24
Finished Mar 19 02:47:09 PM PDT 24
Peak memory 196752 kb
Host smart-dad25765-415e-4686-ac04-26dbefd27b44
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149839179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2149839179
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1961334077
Short name T884
Test name
Test status
Simulation time 145002195 ps
CPU time 1.08 seconds
Started Mar 19 02:47:07 PM PDT 24
Finished Mar 19 02:47:09 PM PDT 24
Peak memory 192320 kb
Host smart-1f68320a-eb5c-4ec4-8dcb-78b12527e419
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1961334077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1961334077
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999917272
Short name T880
Test name
Test status
Simulation time 194197927 ps
CPU time 1.09 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192276 kb
Host smart-66ee5914-23fc-465c-af7b-126cfce68e74
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999917272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2999917272
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3882080014
Short name T913
Test name
Test status
Simulation time 1076184658 ps
CPU time 1.45 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192348 kb
Host smart-22a1eed7-1765-4c37-8d7c-47fa9f492393
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3882080014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3882080014
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.839374192
Short name T909
Test name
Test status
Simulation time 97776575 ps
CPU time 1.16 seconds
Started Mar 19 02:47:03 PM PDT 24
Finished Mar 19 02:47:04 PM PDT 24
Peak memory 192340 kb
Host smart-c66fc0cd-79c0-437e-84f7-879c6bbd4d3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839374192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.839374192
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3552854733
Short name T842
Test name
Test status
Simulation time 43210113 ps
CPU time 0.99 seconds
Started Mar 19 02:47:09 PM PDT 24
Finished Mar 19 02:47:10 PM PDT 24
Peak memory 192116 kb
Host smart-b5a02970-3e52-4b18-9f3e-743d2ef2c155
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3552854733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3552854733
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.817976063
Short name T881
Test name
Test status
Simulation time 78041847 ps
CPU time 1.33 seconds
Started Mar 19 02:47:08 PM PDT 24
Finished Mar 19 02:47:09 PM PDT 24
Peak memory 192364 kb
Host smart-5c895a82-d298-47ad-92ed-6e512e2ecfb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817976063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.817976063
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3677152431
Short name T893
Test name
Test status
Simulation time 41288988 ps
CPU time 1.26 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 192308 kb
Host smart-b95a04a6-7d44-4d16-bf2d-294dbaa32fa5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3677152431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3677152431
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3445512293
Short name T908
Test name
Test status
Simulation time 37863800 ps
CPU time 1.04 seconds
Started Mar 19 02:47:08 PM PDT 24
Finished Mar 19 02:47:10 PM PDT 24
Peak memory 192260 kb
Host smart-609fbf9f-771d-4159-892b-751f14fb3f12
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445512293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3445512293
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3792146932
Short name T901
Test name
Test status
Simulation time 133261063 ps
CPU time 1.08 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 192352 kb
Host smart-984d6827-cb58-45b9-bea5-3bea03d546c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3792146932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3792146932
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3174154624
Short name T885
Test name
Test status
Simulation time 40491285 ps
CPU time 1.27 seconds
Started Mar 19 02:47:08 PM PDT 24
Finished Mar 19 02:47:10 PM PDT 24
Peak memory 197152 kb
Host smart-04ba0b50-fe8b-4f0f-bf5e-be2975eafd6f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174154624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3174154624
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1612303252
Short name T905
Test name
Test status
Simulation time 65928421 ps
CPU time 0.96 seconds
Started Mar 19 02:47:10 PM PDT 24
Finished Mar 19 02:47:11 PM PDT 24
Peak memory 192172 kb
Host smart-cdaf2192-e8db-47ee-b622-b7d8653e2e52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1612303252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1612303252
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1115056711
Short name T938
Test name
Test status
Simulation time 72034851 ps
CPU time 1.1 seconds
Started Mar 19 02:47:07 PM PDT 24
Finished Mar 19 02:47:08 PM PDT 24
Peak memory 192564 kb
Host smart-4b497aa4-1d2e-43c1-a61e-eb175563938e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115056711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1115056711
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.400999402
Short name T888
Test name
Test status
Simulation time 80723035 ps
CPU time 1.58 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192292 kb
Host smart-3bc8fdf8-42a8-4b7c-b0c1-92460c72ca67
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=400999402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.400999402
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749258954
Short name T899
Test name
Test status
Simulation time 347828167 ps
CPU time 1.32 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192280 kb
Host smart-3f158252-6344-403b-9817-fe79cf1a7a2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749258954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3749258954
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3405593550
Short name T853
Test name
Test status
Simulation time 49367265 ps
CPU time 1.16 seconds
Started Mar 19 02:47:04 PM PDT 24
Finished Mar 19 02:47:05 PM PDT 24
Peak memory 192364 kb
Host smart-d8769896-2adf-4ce1-b2a5-ad0b743fd01b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3405593550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3405593550
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3115484704
Short name T895
Test name
Test status
Simulation time 124364325 ps
CPU time 0.84 seconds
Started Mar 19 02:47:07 PM PDT 24
Finished Mar 19 02:47:08 PM PDT 24
Peak memory 192112 kb
Host smart-bbb611f4-fca4-4ba4-a936-88df85ecc2f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115484704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3115484704
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1456024364
Short name T894
Test name
Test status
Simulation time 85656784 ps
CPU time 1.39 seconds
Started Mar 19 02:47:08 PM PDT 24
Finished Mar 19 02:47:10 PM PDT 24
Peak memory 192300 kb
Host smart-301c9607-ad42-4925-98da-c8faa4956152
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1456024364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1456024364
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3563046669
Short name T848
Test name
Test status
Simulation time 326443373 ps
CPU time 1.51 seconds
Started Mar 19 02:47:09 PM PDT 24
Finished Mar 19 02:47:11 PM PDT 24
Peak memory 198888 kb
Host smart-e62baea2-506d-4d9c-bf88-841f20c67c1f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563046669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3563046669
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3842517250
Short name T928
Test name
Test status
Simulation time 102139593 ps
CPU time 1.52 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 192344 kb
Host smart-4d444932-a71c-42f4-bfbf-a24c5734f7bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3842517250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3842517250
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2568188423
Short name T912
Test name
Test status
Simulation time 30207482 ps
CPU time 0.98 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 192180 kb
Host smart-857e215d-406c-421b-bfd6-3cbaa8404fcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568188423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2568188423
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.661457159
Short name T874
Test name
Test status
Simulation time 64035729 ps
CPU time 1.14 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 197112 kb
Host smart-2acf963d-3bd7-4a6c-92ca-4f515d7e7757
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=661457159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.661457159
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2553620761
Short name T864
Test name
Test status
Simulation time 100464045 ps
CPU time 0.93 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 192152 kb
Host smart-eb1a240f-2aa1-47c9-b2cc-4f19ee05a346
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553620761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2553620761
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1951172751
Short name T879
Test name
Test status
Simulation time 62429414 ps
CPU time 1.2 seconds
Started Mar 19 02:47:04 PM PDT 24
Finished Mar 19 02:47:05 PM PDT 24
Peak memory 192248 kb
Host smart-e8ddf88b-073a-440b-8a7a-4505963de54e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1951172751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1951172751
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1969255328
Short name T906
Test name
Test status
Simulation time 133196033 ps
CPU time 1.14 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 198616 kb
Host smart-d4f4bae0-f234-4de9-aca5-778bb5f16d35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969255328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1969255328
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4173495194
Short name T858
Test name
Test status
Simulation time 310836235 ps
CPU time 1.55 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:08 PM PDT 24
Peak memory 192328 kb
Host smart-580e6f3f-27d1-4fcd-827a-495949285bba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4173495194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.4173495194
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3650251179
Short name T927
Test name
Test status
Simulation time 200865652 ps
CPU time 1.44 seconds
Started Mar 19 02:47:09 PM PDT 24
Finished Mar 19 02:47:10 PM PDT 24
Peak memory 192380 kb
Host smart-a3f953c9-bf4f-4065-aa50-ea89109b4fb5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650251179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3650251179
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.640088734
Short name T924
Test name
Test status
Simulation time 87324962 ps
CPU time 1.35 seconds
Started Mar 19 02:47:09 PM PDT 24
Finished Mar 19 02:47:10 PM PDT 24
Peak memory 192288 kb
Host smart-77fdd9b9-133e-4a3b-9c13-ceb944643215
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=640088734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.640088734
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3362073502
Short name T851
Test name
Test status
Simulation time 107146135 ps
CPU time 1.07 seconds
Started Mar 19 02:47:04 PM PDT 24
Finished Mar 19 02:47:05 PM PDT 24
Peak memory 198668 kb
Host smart-ad9847d4-d0c9-48e3-bf9e-2d45a44adb00
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362073502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3362073502
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.464548630
Short name T857
Test name
Test status
Simulation time 47592919 ps
CPU time 1.37 seconds
Started Mar 19 02:47:07 PM PDT 24
Finished Mar 19 02:47:08 PM PDT 24
Peak memory 192284 kb
Host smart-16043b58-e7b2-4fbf-b8b4-6a41e3863dc1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=464548630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.464548630
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3756612191
Short name T875
Test name
Test status
Simulation time 196446088 ps
CPU time 1.54 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192328 kb
Host smart-ae3ca9f1-1843-4d06-9e4a-7e858949389b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756612191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3756612191
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2388341600
Short name T936
Test name
Test status
Simulation time 63498531 ps
CPU time 1.28 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192272 kb
Host smart-a62c9b77-4270-4e15-bac8-dd1bf9d45aec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2388341600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2388341600
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98001314
Short name T873
Test name
Test status
Simulation time 42266245 ps
CPU time 1.25 seconds
Started Mar 19 02:47:03 PM PDT 24
Finished Mar 19 02:47:04 PM PDT 24
Peak memory 198600 kb
Host smart-07632aa0-2389-4a8d-a9ba-99785a834791
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98001314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.98001314
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2266742835
Short name T935
Test name
Test status
Simulation time 116353761 ps
CPU time 1.26 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:08 PM PDT 24
Peak memory 192296 kb
Host smart-a52ab062-c49f-4bec-b658-c53fb42a0e86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2266742835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2266742835
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2956559079
Short name T896
Test name
Test status
Simulation time 49888536 ps
CPU time 1.35 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192300 kb
Host smart-0e01417f-010d-463a-a689-ad23e3f3a8a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956559079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2956559079
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.449492074
Short name T914
Test name
Test status
Simulation time 60809085 ps
CPU time 1.42 seconds
Started Mar 19 02:47:07 PM PDT 24
Finished Mar 19 02:47:09 PM PDT 24
Peak memory 192308 kb
Host smart-adccf38e-7ca7-4166-a3eb-b5f01ae6e0de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=449492074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.449492074
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1107908630
Short name T844
Test name
Test status
Simulation time 103261543 ps
CPU time 1.35 seconds
Started Mar 19 02:47:08 PM PDT 24
Finished Mar 19 02:47:09 PM PDT 24
Peak memory 198688 kb
Host smart-7e87ac29-a868-49b3-9c98-8bee002e9ba7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107908630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1107908630
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1381547258
Short name T898
Test name
Test status
Simulation time 328409331 ps
CPU time 1.16 seconds
Started Mar 19 02:47:02 PM PDT 24
Finished Mar 19 02:47:04 PM PDT 24
Peak memory 192296 kb
Host smart-daf34bc9-b27c-4c05-9a7d-0312d1f5068a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1381547258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1381547258
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3641291811
Short name T916
Test name
Test status
Simulation time 36531143 ps
CPU time 0.83 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 192084 kb
Host smart-f020be93-f952-4de7-ba4f-032beafe8ab0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641291811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3641291811
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3478460104
Short name T910
Test name
Test status
Simulation time 124923763 ps
CPU time 1.32 seconds
Started Mar 19 02:47:19 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192344 kb
Host smart-477f3d53-160c-445d-b33f-ddfed81da2c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3478460104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3478460104
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1479235331
Short name T849
Test name
Test status
Simulation time 125455101 ps
CPU time 1.36 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 198644 kb
Host smart-b77fd6c6-5dc2-4961-85f2-35bab285cb47
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479235331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1479235331
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2355225493
Short name T932
Test name
Test status
Simulation time 183289618 ps
CPU time 1.24 seconds
Started Mar 19 02:47:04 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 192336 kb
Host smart-e9f54cac-680d-4e06-9c78-37f32e317c30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2355225493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2355225493
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.288501954
Short name T929
Test name
Test status
Simulation time 28477194 ps
CPU time 0.88 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192160 kb
Host smart-321c69fa-8953-4b74-98e6-67a98a5b7287
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288501954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.288501954
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3827249299
Short name T903
Test name
Test status
Simulation time 84507458 ps
CPU time 1.47 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192128 kb
Host smart-2b1eaa31-be03-463b-9b4d-0e9d321e77e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3827249299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3827249299
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3065100036
Short name T889
Test name
Test status
Simulation time 46184853 ps
CPU time 1.26 seconds
Started Mar 19 02:47:16 PM PDT 24
Finished Mar 19 02:47:17 PM PDT 24
Peak memory 192332 kb
Host smart-eea15412-f52c-47f0-a405-1a92d66251fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065100036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3065100036
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3222682212
Short name T891
Test name
Test status
Simulation time 312955312 ps
CPU time 1.36 seconds
Started Mar 19 02:47:19 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192336 kb
Host smart-5f70893e-6c43-44e6-a6b5-d1234cdb0b73
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3222682212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3222682212
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2986197616
Short name T933
Test name
Test status
Simulation time 83893037 ps
CPU time 1.05 seconds
Started Mar 19 02:47:19 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 198640 kb
Host smart-421a4651-9080-4d45-a597-ef857a003f46
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986197616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2986197616
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.155456676
Short name T865
Test name
Test status
Simulation time 365675582 ps
CPU time 1.3 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192384 kb
Host smart-4a8832da-ef6a-4c75-add4-2aba8ff61168
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=155456676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.155456676
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1104754765
Short name T870
Test name
Test status
Simulation time 65477384 ps
CPU time 0.87 seconds
Started Mar 19 02:47:21 PM PDT 24
Finished Mar 19 02:47:22 PM PDT 24
Peak memory 196580 kb
Host smart-da6fe78f-25ef-485f-ba99-93a46bf54cfe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104754765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1104754765
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1569442329
Short name T926
Test name
Test status
Simulation time 169577657 ps
CPU time 0.94 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 197684 kb
Host smart-6489d0a2-cecf-4067-b71b-c1827dba02eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1569442329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1569442329
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2915149214
Short name T861
Test name
Test status
Simulation time 304999941 ps
CPU time 0.9 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 192176 kb
Host smart-492959b6-acf4-4d04-80f4-f4fa6d212502
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915149214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2915149214
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2997719923
Short name T878
Test name
Test status
Simulation time 70780188 ps
CPU time 0.83 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 192152 kb
Host smart-360c5f46-8367-4ad9-a152-437508d1998c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2997719923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2997719923
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.660555743
Short name T931
Test name
Test status
Simulation time 382734869 ps
CPU time 1.45 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192328 kb
Host smart-ed4eaf21-2422-4571-90e9-25ca565b614a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660555743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.660555743
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1517310007
Short name T890
Test name
Test status
Simulation time 166545449 ps
CPU time 1.35 seconds
Started Mar 19 02:47:16 PM PDT 24
Finished Mar 19 02:47:17 PM PDT 24
Peak memory 192312 kb
Host smart-233155b0-f1ec-42dc-a73e-14614f6c5d49
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1517310007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1517310007
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.91287780
Short name T852
Test name
Test status
Simulation time 53133283 ps
CPU time 1.14 seconds
Started Mar 19 02:47:20 PM PDT 24
Finished Mar 19 02:47:21 PM PDT 24
Peak memory 192264 kb
Host smart-3e6da153-945d-441e-96ab-d8b596aec718
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91287780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.91287780
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2165445198
Short name T843
Test name
Test status
Simulation time 767202028 ps
CPU time 1.31 seconds
Started Mar 19 02:47:16 PM PDT 24
Finished Mar 19 02:47:17 PM PDT 24
Peak memory 198664 kb
Host smart-cbf397e4-8ec1-4f23-8357-88242511773f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2165445198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2165445198
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2061304789
Short name T915
Test name
Test status
Simulation time 51154620 ps
CPU time 1.28 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 198648 kb
Host smart-f5a5a230-ce90-4d79-b4d0-63e09841dc38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061304789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2061304789
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1922650665
Short name T930
Test name
Test status
Simulation time 38766117 ps
CPU time 1.2 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192288 kb
Host smart-5bc05d05-7df0-4671-94ad-8b1cec1827a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1922650665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1922650665
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2135922315
Short name T882
Test name
Test status
Simulation time 49024340 ps
CPU time 1.09 seconds
Started Mar 19 02:47:16 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 192312 kb
Host smart-5b29fdda-f961-4724-ae41-8d3cc42db8b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135922315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2135922315
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1868823475
Short name T887
Test name
Test status
Simulation time 109101768 ps
CPU time 1.09 seconds
Started Mar 19 02:47:19 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192336 kb
Host smart-2c69029a-a0b4-46df-acda-7a31e769c5dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1868823475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1868823475
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2210098
Short name T923
Test name
Test status
Simulation time 38826705 ps
CPU time 1.22 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192324 kb
Host smart-0b836cea-3ae9-4b5b-bd4c-f9c3069b6fca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.2210098
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1223315182
Short name T876
Test name
Test status
Simulation time 226156728 ps
CPU time 1.25 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 198652 kb
Host smart-8c3d4640-0c8a-43a1-9ab1-b86b35f42399
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1223315182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1223315182
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2390266647
Short name T872
Test name
Test status
Simulation time 71091311 ps
CPU time 1.26 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192304 kb
Host smart-522e6a15-86f3-4ef3-b3fb-4bdff4377342
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390266647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2390266647
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.49345289
Short name T846
Test name
Test status
Simulation time 389060625 ps
CPU time 0.8 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192128 kb
Host smart-7a0ad1c9-f0c9-4c30-90bd-8a6cd37caad7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=49345289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.49345289
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1811353376
Short name T877
Test name
Test status
Simulation time 93730181 ps
CPU time 1.02 seconds
Started Mar 19 02:47:07 PM PDT 24
Finished Mar 19 02:47:08 PM PDT 24
Peak memory 192068 kb
Host smart-59325211-ba9a-4fec-8331-14dbcfba993e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811353376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1811353376
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3382373528
Short name T868
Test name
Test status
Simulation time 159324192 ps
CPU time 0.86 seconds
Started Mar 19 02:47:19 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192116 kb
Host smart-2e4f59b9-2281-4ae3-a78a-fb57be1b4bb8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3382373528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3382373528
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2497138585
Short name T907
Test name
Test status
Simulation time 53247808 ps
CPU time 1.41 seconds
Started Mar 19 02:47:19 PM PDT 24
Finished Mar 19 02:47:21 PM PDT 24
Peak memory 192312 kb
Host smart-269f66da-d484-452c-936a-e389feb29843
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497138585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2497138585
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.478595761
Short name T918
Test name
Test status
Simulation time 330092090 ps
CPU time 0.7 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192124 kb
Host smart-9ddbaaa6-0334-4d3a-a5c6-a785228eb698
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=478595761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.478595761
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2192375776
Short name T840
Test name
Test status
Simulation time 36201205 ps
CPU time 0.8 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 196764 kb
Host smart-84301106-7494-4f33-a6eb-cad1bb656ad8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192375776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2192375776
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.39030553
Short name T902
Test name
Test status
Simulation time 48226294 ps
CPU time 1.24 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192340 kb
Host smart-7910c4a1-2393-4360-b5a1-ff105d51f3dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=39030553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.39030553
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3619522759
Short name T863
Test name
Test status
Simulation time 71505946 ps
CPU time 1.37 seconds
Started Mar 19 02:47:20 PM PDT 24
Finished Mar 19 02:47:21 PM PDT 24
Peak memory 198724 kb
Host smart-bdb6e0f9-7ef8-49ed-a87a-ac0d17b9baab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619522759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3619522759
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1838931749
Short name T917
Test name
Test status
Simulation time 45400386 ps
CPU time 1.27 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 192328 kb
Host smart-f243c8d1-7e74-4ede-9bf9-fb43e12c1908
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1838931749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1838931749
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1916555746
Short name T869
Test name
Test status
Simulation time 109411760 ps
CPU time 1.65 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192376 kb
Host smart-feaa1673-52fe-4221-8580-5c0bd1797473
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916555746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1916555746
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3601610351
Short name T862
Test name
Test status
Simulation time 172797133 ps
CPU time 1.34 seconds
Started Mar 19 02:47:16 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 198680 kb
Host smart-341429ec-d03d-48fb-a502-d104207de46b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3601610351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3601610351
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.69859137
Short name T847
Test name
Test status
Simulation time 42272590 ps
CPU time 1.2 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 192128 kb
Host smart-3d1e0f31-665a-483b-82f0-1bd8a8eeabdc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69859137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.69859137
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.8727838
Short name T900
Test name
Test status
Simulation time 106862847 ps
CPU time 1.06 seconds
Started Mar 19 02:47:15 PM PDT 24
Finished Mar 19 02:47:17 PM PDT 24
Peak memory 198476 kb
Host smart-18007432-fcfa-495e-8ede-0bf71017e357
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=8727838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.8727838
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1799261827
Short name T897
Test name
Test status
Simulation time 205679058 ps
CPU time 1.64 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 192332 kb
Host smart-475b1bf4-0b5f-4f9d-a64a-c22a101e727b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799261827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1799261827
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1936926388
Short name T859
Test name
Test status
Simulation time 72187809 ps
CPU time 0.8 seconds
Started Mar 19 02:47:19 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192132 kb
Host smart-97401230-f6c4-48dd-968b-6ae2e3439b16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1936926388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1936926388
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037978729
Short name T937
Test name
Test status
Simulation time 271109818 ps
CPU time 1.38 seconds
Started Mar 19 02:47:19 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192316 kb
Host smart-e607ffc0-b391-4ec7-a480-4be624413109
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037978729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3037978729
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.916732827
Short name T920
Test name
Test status
Simulation time 52170917 ps
CPU time 1.39 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192308 kb
Host smart-39a9aa00-4de7-4c41-b26e-f8a5acd0fd88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=916732827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.916732827
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3544228952
Short name T919
Test name
Test status
Simulation time 168636572 ps
CPU time 1 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192152 kb
Host smart-b4a811d5-1ca7-4624-bfd0-c55c118d7a61
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544228952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3544228952
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3128789132
Short name T855
Test name
Test status
Simulation time 307838354 ps
CPU time 1.43 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192368 kb
Host smart-6de01284-333c-4de7-bb08-39ae118df934
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3128789132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3128789132
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.502855888
Short name T883
Test name
Test status
Simulation time 329349805 ps
CPU time 1.09 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 192360 kb
Host smart-2808e6fb-0afb-41df-8342-e92428232146
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502855888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.502855888
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2485414118
Short name T904
Test name
Test status
Simulation time 318502439 ps
CPU time 1.51 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 192280 kb
Host smart-a7b70ba1-3fc2-42ef-8250-1dc6ea228e47
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2485414118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2485414118
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3941609424
Short name T871
Test name
Test status
Simulation time 59142926 ps
CPU time 1.18 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 192320 kb
Host smart-7c01410b-b140-4e3c-87c4-8826d2ef8ed7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941609424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3941609424
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4096960231
Short name T866
Test name
Test status
Simulation time 734020505 ps
CPU time 1.49 seconds
Started Mar 19 02:47:07 PM PDT 24
Finished Mar 19 02:47:09 PM PDT 24
Peak memory 192336 kb
Host smart-fded21d4-592c-41d5-b9ab-600b728b04b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4096960231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.4096960231
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2857846997
Short name T839
Test name
Test status
Simulation time 54665239 ps
CPU time 1.1 seconds
Started Mar 19 02:47:07 PM PDT 24
Finished Mar 19 02:47:09 PM PDT 24
Peak memory 196988 kb
Host smart-80d1dda6-7153-4147-b1ac-f2a08c1cd4ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857846997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2857846997
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3266442112
Short name T921
Test name
Test status
Simulation time 230040919 ps
CPU time 1.36 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 198648 kb
Host smart-63ed1887-c78e-45a7-a747-e37cbd8e7a28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3266442112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3266442112
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4108922062
Short name T934
Test name
Test status
Simulation time 116290500 ps
CPU time 0.83 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 196728 kb
Host smart-aa96eed7-6565-45b9-9187-d3cb7b980f07
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108922062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4108922062
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.238896752
Short name T845
Test name
Test status
Simulation time 166059664 ps
CPU time 1.42 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:08 PM PDT 24
Peak memory 192328 kb
Host smart-5d3efb01-8dbf-4dac-89f8-a7ce882da1ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=238896752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.238896752
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2269418433
Short name T911
Test name
Test status
Simulation time 407292313 ps
CPU time 1.47 seconds
Started Mar 19 02:47:09 PM PDT 24
Finished Mar 19 02:47:10 PM PDT 24
Peak memory 192356 kb
Host smart-3ff8258d-f6f7-48dc-bf90-cf312a1d397d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269418433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2269418433
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3885462742
Short name T886
Test name
Test status
Simulation time 84970037 ps
CPU time 1.38 seconds
Started Mar 19 02:47:08 PM PDT 24
Finished Mar 19 02:47:09 PM PDT 24
Peak memory 192312 kb
Host smart-a008df54-e884-4f9e-b1ed-32b2b94b0516
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3885462742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3885462742
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2319186816
Short name T860
Test name
Test status
Simulation time 172530236 ps
CPU time 1.27 seconds
Started Mar 19 02:47:07 PM PDT 24
Finished Mar 19 02:47:08 PM PDT 24
Peak memory 192348 kb
Host smart-f2d4cc90-9eb4-43d3-a8e3-9c3ea9c9fd54
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319186816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2319186816
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1224327666
Short name T850
Test name
Test status
Simulation time 74118720 ps
CPU time 1.43 seconds
Started Mar 19 02:47:05 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 198584 kb
Host smart-3418d79d-02bf-4b6e-87ca-2abf1e220ec5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1224327666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1224327666
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894431963
Short name T922
Test name
Test status
Simulation time 197655944 ps
CPU time 1.37 seconds
Started Mar 19 02:47:06 PM PDT 24
Finished Mar 19 02:47:07 PM PDT 24
Peak memory 192308 kb
Host smart-86d77a3b-152f-42f8-a015-a20d8e30c9e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894431963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2894431963
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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